1 =============================================================================
2 Freescale Frame Manager Device Bindings
8 - FMan dTSEC/XGEC/mEMAC Node
13 =============================================================================
18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 etc.) the FMan node will have child nodes for each of them.
25 Value type: <stringlist>
26 Definition: Must include "fsl,fman"
27 FMan version can be determined via FM_IP_REV_1 register in the
28 FMan block. The offset is 0xc4 from the beginning of the
29 Frame Processing Manager memory map (0xc3000 from the
30 beginning of the FMan node).
35 Definition: Specifies the index of the FMan unit.
37 The cell-index value may be used by the SoC, to identify the
38 FMan unit in the SoC memory map. In the table bellow,
39 there's a description of the cell-index use in each SoC:
42 register[bit] FMan unit cell-index
43 ============================================================
46 - P2041, P3041, P4080 P5020, P5040:
47 register[bit] FMan unit cell-index
48 ============================================================
51 (Second FM available only in P4080 and P5040)
53 - B4860, T1040, T2080, T4240:
54 register[bit] FMan unit cell-index
55 ============================================================
56 DCFG_CCSR_DEVDISR2[24] 1 0
57 DCFG_CCSR_DEVDISR2[25] 2 1
58 (Second FM available only in T4240)
60 DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
61 the specific SoC "Device Configuration/Pin Control" Memory
66 Value type: <prop-encoded-array>
67 Definition: A standard property. Specifies the offset of the
68 following configuration registers:
69 - BMI configuration registers.
70 - QMI configuration registers.
71 - DMA configuration registers.
72 - FPM configuration registers.
73 - FMan controller configuration registers.
77 Value type: <prop-encoded-array>
78 Definition: A standard property.
82 Value type: <prop-encoded-array>
83 Definition: phandle for the fman input clock.
87 Value type: <stringlist>
88 Definition: "fmanclk" for the fman input clock.
92 Value type: <prop-encoded-array>
93 Definition: A pair of IRQs are specified in this property.
94 The first element is associated with the event interrupts and
95 the second element is associated with the error interrupts.
97 - fsl,qman-channel-range
99 Value type: <prop-encoded-array>
100 Definition: Specifies the range of the available dedicated
101 channels in the FMan. The first cell specifies the beginning
102 of the range and the second cell specifies the number of
104 Further information available at:
105 "Work Queue (WQ) Channel Assignments in the QMan" section
106 in DPAA Reference Manual.
111 Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
113 - fsl,erratum-a050385
116 Definition: A boolean property. Indicates the presence of the
117 erratum A050385 which indicates that DMA transactions that are
118 split can result in a FMan lock.
120 =============================================================================
125 FMan Internal memory - shared between all the FMan modules.
126 It contains data structures that are common and written to or read by
128 FMan internal memory is split into the following parts:
129 Packet buffering (Tx/Rx FIFOs)
130 Frames internal context
136 Value type: <stringlist>
137 Definition: Must include "fsl,fman-muram"
141 Value type: <prop-encoded-array>
142 Definition: A standard property.
143 Specifies the multi-user memory offset and the size within
149 compatible = "fsl,fman-muram";
150 ranges = <0 0x000000 0x28000>;
153 =============================================================================
158 The Frame Manager (FMan) supports several types of hardware ports:
159 Ethernet receiver (RX)
160 Ethernet transmitter (TX)
161 Offline/Host command (O/H)
167 Value type: <stringlist>
168 Definition: A standard property.
169 Must include one of the following:
170 - "fsl,fman-v2-port-oh" for FManV2 OH ports
171 - "fsl,fman-v2-port-rx" for FManV2 RX ports
172 - "fsl,fman-v2-port-tx" for FManV2 TX ports
173 - "fsl,fman-v3-port-oh" for FManV3 OH ports
174 - "fsl,fman-v3-port-rx" for FManV3 RX ports
175 - "fsl,fman-v3-port-tx" for FManV3 TX ports
180 Definition: Specifies the hardware port id.
181 Each hardware port on the FMan has its own hardware PortID.
182 Super set of all hardware Port IDs available at FMan Reference
183 Manual under "FMan Hardware Ports in Freescale Devices" table.
185 Each hardware port is assigned a 4KB, port-specific page in
186 the FMan hardware port memory region (which is part of the
187 FMan memory map). The first 4 KB in the FMan hardware ports
188 memory region is used for what are called common registers.
189 The subsequent 63 4KB pages are allocated to the hardware
191 The page of a specific port is determined by the cell-index.
195 Value type: <prop-encoded-array>
196 Definition: There is one reg region describing the port
197 configuration registers.
202 Definition: The default port rate is 1G.
203 If this property exists, the port is s 10G port.
205 - fsl,fman-best-effort-port
208 Definition: Can be defined only if 10G-support is set.
209 This property marks a best-effort 10G port (10G port that
210 may not be capable of line rate).
216 compatible = "fsl,fman-v2-port-tx";
217 reg = <0xa8000 0x1000>;
222 compatible = "fsl,fman-v2-port-rx";
223 reg = <0x88000 0x1000>;
228 compatible = "fsl,fman-v2-port-oh";
229 reg = <0x81000 0x1000>;
232 =============================================================================
233 FMan dTSEC/XGEC/mEMAC Node
237 mEMAC/dTSEC/XGEC are the Ethernet network interfaces
243 Value type: <stringlist>
244 Definition: A standard property.
245 Must include one of the following:
246 - "fsl,fman-dtsec" for dTSEC MAC
247 - "fsl,fman-xgec" for XGEC MAC
248 - "fsl,fman-memac for mEMAC MAC
253 Definition: Specifies the MAC id.
255 The cell-index value may be used by the FMan or the SoC, to
256 identify the MAC unit in the FMan (or SoC) memory map.
257 In the tables bellow there's a description of the cell-index
258 use, there are two tables, one describes the use of cell-index
259 by the FMan, the second describes the use by the SoC:
264 register[bit] MAC cell-index
265 ============================================================
267 FM_EPI[16+n] dTSECn n-1
268 FM_NPI[11+n] dTSECn n-1
272 register[bit] MAC cell-index
273 ============================================================
274 FM_EPI[16+n] mEMACn n-1
277 FM_NPI[11+n] mEMACn n-1
282 FM_EPI and FM_NPI are located in the FMan memory map.
286 - P2041, P3041, P4080 P5020, P5040:
287 register[bit] FMan MAC cell
289 ============================================================
290 DCFG_DEVDISR2[7] 1 XGEC 8
291 DCFG_DEVDISR2[7+n] 1 dTSECn n-1
292 DCFG_DEVDISR2[15] 2 XGEC 8
293 DCFG_DEVDISR2[15+n] 2 dTSECn n-1
296 - T1040, T2080, T4240, B4860:
297 register[bit] FMan MAC cell
299 ============================================================
300 DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1
301 DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1
304 EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
305 the specific SoC "Device Configuration/Pin Control" Memory
310 Value type: <prop-encoded-array>
311 Definition: A standard property.
315 Value type: <prop-encoded-array>
316 Definition: An array of two phandles - the first references is
317 the FMan RX port and the second is the TX port used by this
322 Value type: <phandle>
323 Definition: A phandle for 1EEE1588 timer.
327 fman1_tx28: port@a8000 {
329 compatible = "fsl,fman-v2-port-tx";
330 reg = <0xa8000 0x1000>;
333 fman1_rx8: port@88000 {
335 compatible = "fsl,fman-v2-port-rx";
336 reg = <0x88000 0x1000>;
339 ptp-timer: ptp_timer@fe000 {
340 compatible = "fsl,fman-ptp-timer";
341 reg = <0xfe000 0x1000>;
345 compatible = "fsl,fman-dtsec";
347 reg = <0xe0000 0x1000>;
348 fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
349 ptp-timer = <&ptp-timer>;
352 ============================================================================
357 The FMan interface to support IEEE 1588
364 Value type: <stringlist>
365 Definition: A standard property.
366 Must include "fsl,fman-ptp-timer".
370 Value type: <prop-encoded-array>
371 Definition: A standard property.
376 compatible = "fsl,fman-ptp-timer";
377 reg = <0xfe000 0x1000>;
380 =============================================================================
385 The MDIO is a bus to which the PHY devices are connected.
391 Value type: <stringlist>
392 Definition: A standard property.
393 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
394 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
395 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
400 Value type: <prop-encoded-array>
401 Definition: A standard property.
406 Definition: Specifies the external MDIO bus clock speed to
407 be used, if different from the standard 2.5 MHz.
408 This may be due to the standard speed being unsupported (e.g.
409 due to a hardware problem), or to advertise that all relevant
410 components in the system support a faster speed.
413 Usage: required for external MDIO
414 Value type: <prop-encoded-array>
415 Definition: Event interrupt of external MDIO controller.
417 - fsl,fman-internal-mdio
418 Usage: required for internal MDIO
420 Definition: Fman has internal MDIO for internal PCS(Physical
421 Coding Sublayer) PHYs and external MDIO for external PHYs.
422 The settings and programming routines for internal/external
423 MDIO are different. Must be included for internal MDIO.
427 Example for FMan v2 external MDIO:
430 compatible = "fsl,fman-xmdio";
431 reg = <0xf1000 0x1000>;
432 interrupts = <101 2 0 0>;
435 Example for FMan v3 internal MDIO:
438 compatible = "fsl,fman-memac-mdio";
439 reg = <0xf1000 0x1000>;
440 fsl,fman-internal-mdio;
443 =============================================================================
447 #address-cells = <1>;
450 compatible = "fsl,fman"
451 ranges = <0 0x400000 0x100000>;
452 reg = <0x400000 0x100000>;
453 clocks = <&fman_clk>;
454 clock-names = "fmanclk";
458 fsl,qman-channel-range = <0x40 0xc>;
461 compatible = "fsl,fman-muram";
467 compatible = "fsl,fman-v2-port-oh";
468 reg = <0x81000 0x1000>;
473 compatible = "fsl,fman-v2-port-oh";
474 reg = <0x82000 0x1000>;
479 compatible = "fsl,fman-v2-port-oh";
480 reg = <0x83000 0x1000>;
485 compatible = "fsl,fman-v2-port-oh";
486 reg = <0x84000 0x1000>;
491 compatible = "fsl,fman-v2-port-oh";
492 reg = <0x85000 0x1000>;
497 compatible = "fsl,fman-v2-port-oh";
498 reg = <0x86000 0x1000>;
501 fman1_rx_0x8: port@88000 {
503 compatible = "fsl,fman-v2-port-rx";
504 reg = <0x88000 0x1000>;
507 fman1_rx_0x9: port@89000 {
509 compatible = "fsl,fman-v2-port-rx";
510 reg = <0x89000 0x1000>;
513 fman1_rx_0xa: port@8a000 {
515 compatible = "fsl,fman-v2-port-rx";
516 reg = <0x8a000 0x1000>;
519 fman1_rx_0xb: port@8b000 {
521 compatible = "fsl,fman-v2-port-rx";
522 reg = <0x8b000 0x1000>;
525 fman1_rx_0xc: port@8c000 {
527 compatible = "fsl,fman-v2-port-rx";
528 reg = <0x8c000 0x1000>;
531 fman1_rx_0x10: port@90000 {
533 compatible = "fsl,fman-v2-port-rx";
534 reg = <0x90000 0x1000>;
537 fman1_tx_0x28: port@a8000 {
539 compatible = "fsl,fman-v2-port-tx";
540 reg = <0xa8000 0x1000>;
543 fman1_tx_0x29: port@a9000 {
545 compatible = "fsl,fman-v2-port-tx";
546 reg = <0xa9000 0x1000>;
549 fman1_tx_0x2a: port@aa000 {
551 compatible = "fsl,fman-v2-port-tx";
552 reg = <0xaa000 0x1000>;
555 fman1_tx_0x2b: port@ab000 {
557 compatible = "fsl,fman-v2-port-tx";
558 reg = <0xab000 0x1000>;
561 fman1_tx_0x2c: port@ac0000 {
563 compatible = "fsl,fman-v2-port-tx";
564 reg = <0xac000 0x1000>;
567 fman1_tx_0x30: port@b0000 {
569 compatible = "fsl,fman-v2-port-tx";
570 reg = <0xb0000 0x1000>;
574 compatible = "fsl,fman-dtsec";
576 reg = <0xe0000 0x1000>;
577 fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
581 compatible = "fsl,fman-dtsec";
583 reg = <0xe2000 0x1000>;
584 fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
588 compatible = "fsl,fman-dtsec";
590 reg = <0xe4000 0x1000>;
591 fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
595 compatible = "fsl,fman-dtsec";
597 reg = <0xe6000 0x1000>;
598 fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
602 compatible = "fsl,fman-dtsec";
604 reg = <0xf0000 0x1000>;
605 fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
609 compatible = "fsl,fman-xgec";
610 reg = <0xf0000 0x1000>;
611 fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
615 compatible = "fsl,fman-ptp-timer";
616 reg = <0xfe000 0x1000>;
620 compatible = "fsl,fman-xmdio";
621 reg = <0xf1000 0x1000>;
622 interrupts = <101 2 0 0>;