arch/arc/boot/dts/axs10x_mb.dtsi

   1 /*
   2  * Support for peripherals on the AXS10x mainboard
   3  *
   4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 / {
  12         aliases {
  13                 ethernet = &gmac;
  14         };
  15
  16         axs10x_mb {
  17                 compatible = "simple-bus";
  18                 #address-cells = <1>;
  19                 #size-cells = <1>;
  20                 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
  21                 interrupt-parent = <&mb_intc>;
  22
  23                 creg_rst: reset-controller@11220 {
  24                         compatible = "snps,axs10x-reset";
  25                         #reset-cells = <1>;
  26                         reg = <0x11220 0x4>;
  27                 };
  28
  29                 i2sclk: i2sclk@100a0 {
  30                         compatible = "snps,axs10x-i2s-pll-clock";
  31                         reg = <0x100a0 0x10>;
  32                         clocks = <&i2spll_clk>;
  33                         #clock-cells = <0>;
  34                 };
  35
  36                 clocks {
  37                         i2spll_clk: i2spll_clk {
  38                                 compatible = "fixed-clock";
  39                                 clock-frequency = <27000000>;
  40                                 #clock-cells = <0>;
  41                         };
  42
  43                         i2cclk: i2cclk {
  44                                 compatible = "fixed-clock";
  45                                 clock-frequency = <50000000>;
  46                                 #clock-cells = <0>;
  47                         };
  48
  49                         apbclk: apbclk {
  50                                 compatible = "fixed-clock";
  51                                 clock-frequency = <50000000>;
  52                                 #clock-cells = <0>;
  53                         };
  54
  55                         mmcclk: mmcclk {
  56                                 compatible = "fixed-clock";
  57                                 /*
  58                                  * DW sdio controller has external ciu clock divider
  59                                  * controlled via register in SDIO IP. It divides
  60                                  * sdio_ref_clk (which comes from CGU) by 16 for
  61                                  * default. So default mmcclk clock (which comes
  62                                  * to sdk_in) is 25000000 Hz.
  63                                  */
  64                                 clock-frequency = <25000000>;
  65                                 #clock-cells = <0>;
  66                         };
  67
  68                         pguclk: pguclk {
  69                                 #clock-cells = <0>;
  70                                 compatible = "fixed-clock";
  71                                 clock-frequency = <74250000>;
  72                         };
  73                 };
  74
  75                 gmac: ethernet@0x18000 {
  76                         #interrupt-cells = <1>;
  77                         compatible = "snps,dwmac";
  78                         reg = < 0x18000 0x2000 >;
  79                         interrupts = < 4 >;
  80                         interrupt-names = "macirq";
  81                         phy-mode = "rgmii";
  82                         snps,pbl = < 32 >;
  83                         snps,multicast-filter-bins = <256>;
  84                         clocks = <&apbclk>;
  85                         clock-names = "stmmaceth";
  86                         max-speed = <100>;
  87                         resets = <&creg_rst 5>;
  88                         reset-names = "stmmaceth";
  89                         mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
  90                 };
  91
  92                 ehci@0x40000 {
  93                         compatible = "generic-ehci";
  94                         reg = < 0x40000 0x100 >;
  95                         interrupts = < 8 >;
  96                 };
  97
  98                 ohci@0x60000 {
  99                         compatible = "generic-ohci";
 100                         reg = < 0x60000 0x100 >;
 101                         interrupts = < 8 >;
 102                 };
 103
 104                 /*
 105                  * According to DW Mobile Storage databook it is required
 106                  * to use  "Hold Register" if card is enumerated in SDR12 or
 107                  * SDR25 modes.
 108                  *
 109                  * Utilization of "Hold Register" is already implemented via
 110                  * dw_mci_pltfm_prepare_command() which in its turn gets
 111                  * used through dw_mci_drv_data->prepare_command call-back.
 112                  * This call-back is used in Altera Socfpga platform and so
 113                  * we may reuse it saying that we're compatible with their
 114                  * "altr,socfpga-dw-mshc".
 115                  *
 116                  * Most probably "Hold Register" utilization is platform-
 117                  * independent requirement which means that single unified
 118                  * "snps,dw-mshc" should be enough for all users of DW MMC once
 119                  * dw_mci_pltfm_prepare_command() is used in generic platform
 120                  * code.
 121                  */
 122                 mmc@0x15000 {
 123                         compatible = "altr,socfpga-dw-mshc";
 124                         reg = < 0x15000 0x400 >;
 125                         fifo-depth = < 16 >;
 126                         card-detect-delay = < 200 >;
 127                         clocks = <&apbclk>, <&mmcclk>;
 128                         clock-names = "biu", "ciu";
 129                         interrupts = < 7 >;
 130                         bus-width = < 4 >;
 131                 };
 132
 133                 uart@0x20000 {
 134                         compatible = "snps,dw-apb-uart";
 135                         reg = <0x20000 0x100>;
 136                         clock-frequency = <33333333>;
 137                         interrupts = <17>;
 138                         baud = <115200>;
 139                         reg-shift = <2>;
 140                         reg-io-width = <4>;
 141                 };
 142
 143                 uart@0x21000 {
 144                         compatible = "snps,dw-apb-uart";
 145                         reg = <0x21000 0x100>;
 146                         clock-frequency = <33333333>;
 147                         interrupts = <18>;
 148                         baud = <115200>;
 149                         reg-shift = <2>;
 150                         reg-io-width = <4>;
 151                 };
 152
 153                 /* UART muxed with USB data port (ttyS3) */
 154                 uart@0x22000 {
 155                         compatible = "snps,dw-apb-uart";
 156                         reg = <0x22000 0x100>;
 157                         clock-frequency = <33333333>;
 158                         interrupts = <19>;
 159                         baud = <115200>;
 160                         reg-shift = <2>;
 161                         reg-io-width = <4>;
 162                 };
 163
 164                 i2c@0x1d000 {
 165                         compatible = "snps,designware-i2c";
 166                         reg = <0x1d000 0x100>;
 167                         clock-frequency = <400000>;
 168                         clocks = <&i2cclk>;
 169                         interrupts = <14>;
 170                 };
 171
 172                 i2s: i2s@1e000 {
 173                         compatible = "snps,designware-i2s";
 174                         reg = <0x1e000 0x100>;
 175                         clocks = <&i2sclk 0>;
 176                         clock-names = "i2sclk";
 177                         interrupts = <15>;
 178                         #sound-dai-cells = <0>;
 179                 };
 180
 181                 i2c@0x1f000 {
 182                         compatible = "snps,designware-i2c";
 183                         #address-cells = <1>;
 184                         #size-cells = <0>;
 185                         reg = <0x1f000 0x100>;
 186                         clock-frequency = <400000>;
 187                         clocks = <&i2cclk>;
 188                         interrupts = <16>;
 189
 190                         adv7511:adv7511@39{
 191                                 compatible="adi,adv7511";
 192                                 reg = <0x39>;
 193                                 interrupts = <23>;
 194                                 adi,input-depth = <8>;
 195                                 adi,input-colorspace = "rgb";
 196                                 adi,input-clock = "1x";
 197                                 adi,clock-delay = <0x03>;
 198                                 #sound-dai-cells = <0>;
 199
 200                                 ports {
 201                                         #address-cells = <1>;
 202                                         #size-cells = <0>;
 203
 204                                         /* RGB/YUV input */
 205                                         port@0 {
 206                                                 reg = <0>;
 207                                                 adv7511_input:endpoint {
 208                                                 remote-endpoint = <&pgu_output>;
 209                                                 };
 210                                         };
 211
 212                                         /* HDMI output */
 213                                         port@1 {
 214                                                 reg = <1>;
 215                                                 adv7511_output: endpoint {
 216                                                         remote-endpoint = <&hdmi_connector_in>;
 217                                                 };
 218                                         };
 219                                 };
 220                         };
 221
 222                         eeprom@0x54{
 223                                 compatible = "atmel,24c01";
 224                                 reg = <0x54>;
 225                                 pagesize = <0x8>;
 226                         };
 227
 228                         eeprom@0x57{
 229                                 compatible = "atmel,24c04";
 230                                 reg = <0x57>;
 231                                 pagesize = <0x8>;
 232                         };
 233                 };
 234
 235                 hdmi0: connector {
 236                         compatible = "hdmi-connector";
 237                         type = "a";
 238                         port {
 239                                 hdmi_connector_in: endpoint {
 240                                         remote-endpoint = <&adv7511_output>;
 241                                 };
 242                         };
 243                 };
 244
 245                 gpio0:gpio@13000 {
 246                         compatible = "snps,dw-apb-gpio";
 247                         reg = <0x13000 0x1000>;
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250
 251                         gpio0_banka: gpio-controller@0 {
 252                                 compatible = "snps,dw-apb-gpio-port";
 253                                 gpio-controller;
 254                                 #gpio-cells = <2>;
 255                                 snps,nr-gpios = <32>;
 256                                 reg = <0>;
 257                         };
 258
 259                         gpio0_bankb: gpio-controller@1 {
 260                                 compatible = "snps,dw-apb-gpio-port";
 261                                 gpio-controller;
 262                                 #gpio-cells = <2>;
 263                                 snps,nr-gpios = <8>;
 264                                 reg = <1>;
 265                         };
 266
 267                         gpio0_bankc: gpio-controller@2 {
 268                                 compatible = "snps,dw-apb-gpio-port";
 269                                 gpio-controller;
 270                                 #gpio-cells = <2>;
 271                                 snps,nr-gpios = <8>;
 272                                 reg = <2>;
 273                         };
 274                 };
 275
 276                 gpio1:gpio@14000 {
 277                         compatible = "snps,dw-apb-gpio";
 278                         reg = <0x14000 0x1000>;
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281
 282                         gpio1_banka: gpio-controller@0 {
 283                                 compatible = "snps,dw-apb-gpio-port";
 284                                 gpio-controller;
 285                                 #gpio-cells = <2>;
 286                                 snps,nr-gpios = <30>;
 287                                 reg = <0>;
 288                         };
 289
 290                         gpio1_bankb: gpio-controller@1 {
 291                                 compatible = "snps,dw-apb-gpio-port";
 292                                 gpio-controller;
 293                                 #gpio-cells = <2>;
 294                                 snps,nr-gpios = <10>;
 295                                 reg = <1>;
 296                         };
 297
 298                         gpio1_bankc: gpio-controller@2 {
 299                                 compatible = "snps,dw-apb-gpio-port";
 300                                 gpio-controller;
 301                                 #gpio-cells = <2>;
 302                                 snps,nr-gpios = <8>;
 303                                 reg = <2>;
 304                         };
 305                 };
 306
 307                 pgu@17000 {
 308                         compatible = "snps,arcpgu";
 309                         reg = <0x17000 0x400>;
 310                         encoder-slave = <&adv7511>;
 311                         clocks = <&pguclk>;
 312                         clock-names = "pxlclk";
 313                         memory-region = <&frame_buffer>;
 314                         port {
 315                                 pgu_output: endpoint {
 316                                         remote-endpoint = <&adv7511_input>;
 317                                 };
 318                         };
 319                 };
 320
 321                 sound_playback {
 322                         compatible = "simple-audio-card";
 323                         simple-audio-card,name = "AXS10x HDMI Audio";
 324                         simple-audio-card,format = "i2s";
 325                         simple-audio-card,cpu {
 326                                 sound-dai = <&i2s>;
 327                         };
 328                         simple-audio-card,codec {
 329                                 sound-dai = <&adv7511>;
 330                         };
 331                 };
 332         };
 333 };