arch/arc/kernel/setup.c

   1 /*
   2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/seq_file.h>
  10 #include <linux/fs.h>
  11 #include <linux/delay.h>
  12 #include <linux/root_dev.h>
  13 #include <linux/console.h>
  14 #include <linux/module.h>
  15 #include <linux/sizes.h>
  16 #include <linux/cpu.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/of_fdt.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/cache.h>
  21 #include <asm/sections.h>
  22 #include <asm/arcregs.h>
  23 #include <asm/tlb.h>
  24 #include <asm/setup.h>
  25 #include <asm/page.h>
  26 #include <asm/irq.h>
  27 #include <asm/unwind.h>
  28 #include <asm/clk.h>
  29 #include <asm/mach_desc.h>
  30 #include <asm/smp.h>
  31
  32 #define FIX_PTR(x)  __asm__ __volatile__(";" : "+r"(x))
  33
  34 unsigned int intr_to_DE_cnt;
  35
  36 /* Part of U-boot ABI: see head.S */
  37 int __initdata uboot_tag;
  38 char __initdata *uboot_arg;
  39
  40 const struct machine_desc *machine_desc;
  41
  42 struct task_struct *_current_task[NR_CPUS];     /* For stack switching */
  43
  44 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
  45
  46 static void read_arc_build_cfg_regs(void)
  47 {
  48         struct bcr_perip uncached_space;
  49         struct bcr_generic bcr;
  50         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
  51         unsigned long perip_space;
  52         FIX_PTR(cpu);
  53
  54         READ_BCR(AUX_IDENTITY, cpu->core);
  55         READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
  56
  57         READ_BCR(ARC_REG_TIMERS_BCR, cpu->timers);
  58         cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
  59
  60         READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
  61         if (uncached_space.ver < 3)
  62                 perip_space = uncached_space.start << 24;
  63         else
  64                 perip_space = read_aux_reg(AUX_NON_VOL) & 0xF0000000;
  65
  66         BUG_ON(perip_space != ARC_UNCACHED_ADDR_SPACE);
  67
  68         READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
  69
  70         cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */
  71         cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */
  72         cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0;        /* 1,3 */
  73         cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0;
  74         cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */
  75
  76         /* Note that we read the CCM BCRs independent of kernel config
  77          * This is to catch the cases where user doesn't know that
  78          * CCMs are present in hardware build
  79          */
  80         {
  81                 struct bcr_iccm iccm;
  82                 struct bcr_dccm dccm;
  83                 struct bcr_dccm_base dccm_base;
  84                 unsigned int bcr_32bit_val;
  85
  86                 bcr_32bit_val = read_aux_reg(ARC_REG_ICCM_BCR);
  87                 if (bcr_32bit_val) {
  88                         iccm = *((struct bcr_iccm *)&bcr_32bit_val);
  89                         cpu->iccm.base_addr = iccm.base << 16;
  90                         cpu->iccm.sz = 0x2000 << (iccm.sz - 1);
  91                 }
  92
  93                 bcr_32bit_val = read_aux_reg(ARC_REG_DCCM_BCR);
  94                 if (bcr_32bit_val) {
  95                         dccm = *((struct bcr_dccm *)&bcr_32bit_val);
  96                         cpu->dccm.sz = 0x800 << (dccm.sz);
  97
  98                         READ_BCR(ARC_REG_DCCMBASE_BCR, dccm_base);
  99                         cpu->dccm.base_addr = dccm_base.addr << 8;
 100                 }
 101         }
 102
 103         READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);
 104
 105         read_decode_mmu_bcr();
 106         read_decode_cache_bcr();
 107
 108         if (is_isa_arcompact()) {
 109                 struct bcr_fp_arcompact sp, dp;
 110                 struct bcr_bpu_arcompact bpu;
 111
 112                 READ_BCR(ARC_REG_FP_BCR, sp);
 113                 READ_BCR(ARC_REG_DPFP_BCR, dp);
 114                 cpu->extn.fpu_sp = sp.ver ? 1 : 0;
 115                 cpu->extn.fpu_dp = dp.ver ? 1 : 0;
 116
 117                 READ_BCR(ARC_REG_BPU_BCR, bpu);
 118                 cpu->bpu.ver = bpu.ver;
 119                 cpu->bpu.full = bpu.fam ? 1 : 0;
 120                 if (bpu.ent) {
 121                         cpu->bpu.num_cache = 256 << (bpu.ent - 1);
 122                         cpu->bpu.num_pred = 256 << (bpu.ent - 1);
 123                 }
 124         } else {
 125                 struct bcr_fp_arcv2 spdp;
 126                 struct bcr_bpu_arcv2 bpu;
 127
 128                 READ_BCR(ARC_REG_FP_V2_BCR, spdp);
 129                 cpu->extn.fpu_sp = spdp.sp ? 1 : 0;
 130                 cpu->extn.fpu_dp = spdp.dp ? 1 : 0;
 131
 132                 READ_BCR(ARC_REG_BPU_BCR, bpu);
 133                 cpu->bpu.ver = bpu.ver;
 134                 cpu->bpu.full = bpu.ft;
 135                 cpu->bpu.num_cache = 256 << bpu.bce;
 136                 cpu->bpu.num_pred = 2048 << bpu.pte;
 137         }
 138
 139         READ_BCR(ARC_REG_AP_BCR, bcr);
 140         cpu->extn.ap = bcr.ver ? 1 : 0;
 141
 142         READ_BCR(ARC_REG_SMART_BCR, bcr);
 143         cpu->extn.smart = bcr.ver ? 1 : 0;
 144
 145         READ_BCR(ARC_REG_RTT_BCR, bcr);
 146         cpu->extn.rtt = bcr.ver ? 1 : 0;
 147
 148         cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
 149 }
 150
 151 static const struct cpuinfo_data arc_cpu_tbl[] = {
 152 #ifdef CONFIG_ISA_ARCOMPACT
 153         { {0x20, "ARC 600"      }, 0x2F},
 154         { {0x30, "ARC 700"      }, 0x33},
 155         { {0x34, "ARC 700 R4.10"}, 0x34},
 156         { {0x35, "ARC 700 R4.11"}, 0x35},
 157 #else
 158         { {0x50, "ARC HS38 R2.0"}, 0x51},
 159         { {0x52, "ARC HS38 R2.1"}, 0x52},
 160 #endif
 161         { {0x00, NULL           } }
 162 };
 163
 164
 165 static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
 166 {
 167         struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
 168         struct bcr_identity *core = &cpu->core;
 169         const struct cpuinfo_data *tbl;
 170         char *isa_nm;
 171         int i, be, atomic;
 172         int n = 0;
 173
 174         FIX_PTR(cpu);
 175
 176         if (is_isa_arcompact()) {
 177                 isa_nm = "ARCompact";
 178                 be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
 179
 180                 atomic = cpu->isa.atomic1;
 181                 if (!cpu->isa.ver)      /* ISA BCR absent, use Kconfig info */
 182                         atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
 183         } else {
 184                 isa_nm = "ARCv2";
 185                 be = cpu->isa.be;
 186                 atomic = cpu->isa.atomic;
 187         }
 188
 189         n += scnprintf(buf + n, len - n,
 190                        "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
 191                        core->family, core->cpu_id, core->chip_id);
 192
 193         for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) {
 194                 if ((core->family >= tbl->info.id) &&
 195                     (core->family <= tbl->up_range)) {
 196                         n += scnprintf(buf + n, len - n,
 197                                        "processor [%d]\t: %s (%s ISA) %s\n",
 198                                        cpu_id, tbl->info.str, isa_nm,
 199                                        IS_AVAIL1(be, "[Big-Endian]"));
 200                         break;
 201                 }
 202         }
 203
 204         if (tbl->info.id == 0)
 205                 n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n");
 206
 207         n += scnprintf(buf + n, len - n, "CPU speed\t: %u.%02u Mhz\n",
 208                        (unsigned int)(arc_get_core_freq() / 1000000),
 209                        (unsigned int)(arc_get_core_freq() / 10000) % 100);
 210
 211         n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
 212                        IS_AVAIL1(cpu->timers.t0, "Timer0 "),
 213                        IS_AVAIL1(cpu->timers.t1, "Timer1 "),
 214                        IS_AVAIL2(cpu->timers.rtc, "64-bit RTC ",
 215                                  CONFIG_ARC_HAS_RTC));
 216
 217         n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",
 218                            IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
 219                            IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
 220                            IS_AVAIL1(cpu->isa.unalign, "unalign (not used)"));
 221
 222         if (i)
 223                 n += scnprintf(buf + n, len - n, "\n\t\t: ");
 224
 225         if (cpu->extn_mpy.ver) {
 226                 if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */
 227                         n += scnprintf(buf + n, len - n, "mpy ");
 228                 } else {
 229                         int opt = 2;    /* stock MPY/MPYH */
 230
 231                         if (cpu->extn_mpy.dsp)  /* OPT 7-9 */
 232                                 opt = cpu->extn_mpy.dsp + 6;
 233
 234                         n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt);
 235                 }
 236         }
 237
 238         n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
 239                        IS_AVAIL1(cpu->isa.div_rem, "div_rem "),
 240                        IS_AVAIL1(cpu->extn.norm, "norm "),
 241                        IS_AVAIL1(cpu->extn.barrel, "barrel-shift "),
 242                        IS_AVAIL1(cpu->extn.swap, "swap "),
 243                        IS_AVAIL1(cpu->extn.minmax, "minmax "),
 244                        IS_AVAIL1(cpu->extn.crc, "crc "),
 245                        IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE));
 246
 247         if (cpu->bpu.ver)
 248                 n += scnprintf(buf + n, len - n,
 249                               "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n",
 250                               IS_AVAIL1(cpu->bpu.full, "full"),
 251                               IS_AVAIL1(!cpu->bpu.full, "partial"),
 252                               cpu->bpu.num_cache, cpu->bpu.num_pred);
 253
 254         return buf;
 255 }
 256
 257 static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
 258 {
 259         int n = 0;
 260         struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
 261
 262         FIX_PTR(cpu);
 263
 264         n += scnprintf(buf + n, len - n,
 265                        "Vector Table\t: %#x\nUncached Base\t: %#x\n",
 266                        cpu->vec_base, ARC_UNCACHED_ADDR_SPACE);
 267
 268         if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
 269                 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
 270                                IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
 271                                IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
 272
 273         if (cpu->extn.debug)
 274                 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n",
 275                                IS_AVAIL1(cpu->extn.ap, "ActionPoint "),
 276                                IS_AVAIL1(cpu->extn.smart, "smaRT "),
 277                                IS_AVAIL1(cpu->extn.rtt, "RTT "));
 278
 279         if (cpu->dccm.sz || cpu->iccm.sz)
 280                 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
 281                                cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
 282                                cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
 283
 284         n += scnprintf(buf + n, len - n,
 285                        "OS ABI [v3]\t: no-legacy-syscalls\n");
 286
 287         return buf;
 288 }
 289
 290 static void arc_chk_core_config(void)
 291 {
 292         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
 293         int fpu_enabled;
 294
 295         if (!cpu->timers.t0)
 296                 panic("Timer0 is not present!\n");
 297
 298         if (!cpu->timers.t1)
 299                 panic("Timer1 is not present!\n");
 300
 301         if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->timers.rtc)
 302                 panic("RTC is not present\n");
 303
 304 #ifdef CONFIG_ARC_HAS_DCCM
 305         /*
 306          * DCCM can be arbit placed in hardware.
 307          * Make sure it's placement/sz matches what Linux is built with
 308          */
 309         if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
 310                 panic("Linux built with incorrect DCCM Base address\n");
 311
 312         if (CONFIG_ARC_DCCM_SZ * SZ_1K != cpu->dccm.sz)
 313                 panic("Linux built with incorrect DCCM Size\n");
 314 #endif
 315
 316 #ifdef CONFIG_ARC_HAS_ICCM
 317         if (CONFIG_ARC_ICCM_SZ * SZ_1K != cpu->iccm.sz)
 318                 panic("Linux built with incorrect ICCM Size\n");
 319 #endif
 320
 321         /*
 322          * FP hardware/software config sanity
 323          * -If hardware contains DPFP, kernel needs to save/restore FPU state
 324          * -If not, it will crash trying to save/restore the non-existant regs
 325          *
 326          * (only DPDP checked since SP has no arch visible regs)
 327          */
 328         fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
 329
 330         if (cpu->extn.fpu_dp && !fpu_enabled)
 331                 pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n");
 332         else if (!cpu->extn.fpu_dp && fpu_enabled)
 333                 panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
 334 }
 335
 336 /*
 337  * Initialize and setup the processor core
 338  * This is called by all the CPUs thus should not do special case stuff
 339  *    such as only for boot CPU etc
 340  */
 341
 342 void setup_processor(void)
 343 {
 344         char str[512];
 345         int cpu_id = smp_processor_id();
 346
 347         read_arc_build_cfg_regs();
 348         arc_init_IRQ();
 349
 350         printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 351
 352         arc_mmu_init();
 353         arc_cache_init();
 354
 355         printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
 356         printk(arc_platform_smp_cpuinfo());
 357
 358         arc_chk_core_config();
 359 }
 360
 361 static inline int is_kernel(unsigned long addr)
 362 {
 363         if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end)
 364                 return 1;
 365         return 0;
 366 }
 367
 368 void __init setup_arch(char **cmdline_p)
 369 {
 370 #ifdef CONFIG_ARC_UBOOT_SUPPORT
 371         /* make sure that uboot passed pointer to cmdline/dtb is valid */
 372         if (uboot_tag && is_kernel((unsigned long)uboot_arg))
 373                 panic("Invalid uboot arg\n");
 374
 375         /* See if u-boot passed an external Device Tree blob */
 376         machine_desc = setup_machine_fdt(uboot_arg);    /* uboot_tag == 2 */
 377         if (!machine_desc)
 378 #endif
 379         {
 380                 /* No, so try the embedded one */
 381                 machine_desc = setup_machine_fdt(__dtb_start);
 382                 if (!machine_desc)
 383                         panic("Embedded DT invalid\n");
 384
 385                 /*
 386                  * If we are here, it is established that @uboot_arg didn't
 387                  * point to DT blob. Instead if u-boot says it is cmdline,
 388                  * Appent to embedded DT cmdline.
 389                  * setup_machine_fdt() would have populated @boot_command_line
 390                  */
 391                 if (uboot_tag == 1) {
 392                         /* Ensure a whitespace between the 2 cmdlines */
 393                         strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
 394                         strlcat(boot_command_line, uboot_arg,
 395                                 COMMAND_LINE_SIZE);
 396                 }
 397         }
 398
 399         /* Save unparsed command line copy for /proc/cmdline */
 400         *cmdline_p = boot_command_line;
 401
 402         /* To force early parsing of things like mem=xxx */
 403         parse_early_param();
 404
 405         /* Platform/board specific: e.g. early console registration */
 406         if (machine_desc->init_early)
 407                 machine_desc->init_early();
 408
 409         smp_init_cpus();
 410
 411         setup_processor();
 412         setup_arch_memory();
 413
 414         /* copy flat DT out of .init and then unflatten it */
 415         unflatten_and_copy_device_tree();
 416
 417         /* Can be issue if someone passes cmd line arg "ro"
 418          * But that is unlikely so keeping it as it is
 419          */
 420         root_mountflags &= ~MS_RDONLY;
 421
 422 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
 423         conswitchp = &dummy_con;
 424 #endif
 425
 426         arc_unwind_init();
 427 }
 428
 429 static int __init customize_machine(void)
 430 {
 431         of_clk_init(NULL);
 432         /*
 433          * Traverses flattened DeviceTree - registering platform devices
 434          * (if any) complete with their resources
 435          */
 436         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 437
 438         if (machine_desc->init_machine)
 439                 machine_desc->init_machine();
 440
 441         return 0;
 442 }
 443 arch_initcall(customize_machine);
 444
 445 static int __init init_late_machine(void)
 446 {
 447         if (machine_desc->init_late)
 448                 machine_desc->init_late();
 449
 450         return 0;
 451 }
 452 late_initcall(init_late_machine);
 453 /*
 454  *  Get CPU information for use by the procfs.
 455  */
 456
 457 #define cpu_to_ptr(c)   ((void *)(0xFFFF0000 | (unsigned int)(c)))
 458 #define ptr_to_cpu(p)   (~0xFFFF0000UL & (unsigned int)(p))
 459
 460 static int show_cpuinfo(struct seq_file *m, void *v)
 461 {
 462         char *str;
 463         int cpu_id = ptr_to_cpu(v);
 464
 465         if (!cpu_online(cpu_id)) {
 466                 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
 467                 goto done;
 468         }
 469
 470         str = (char *)__get_free_page(GFP_TEMPORARY);
 471         if (!str)
 472                 goto done;
 473
 474         seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
 475
 476         seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
 477                    loops_per_jiffy / (500000 / HZ),
 478                    (loops_per_jiffy / (5000 / HZ)) % 100);
 479
 480         seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
 481         seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
 482         seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
 483         seq_printf(m, arc_platform_smp_cpuinfo());
 484
 485         free_page((unsigned long)str);
 486 done:
 487         seq_printf(m, "\n");
 488
 489         return 0;
 490 }
 491
 492 static void *c_start(struct seq_file *m, loff_t *pos)
 493 {
 494         /*
 495          * Callback returns cpu-id to iterator for show routine, NULL to stop.
 496          * However since NULL is also a valid cpu-id (0), we use a round-about
 497          * way to pass it w/o having to kmalloc/free a 2 byte string.
 498          * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
 499          */
 500         return *pos < num_possible_cpus() ? cpu_to_ptr(*pos) : NULL;
 501 }
 502
 503 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 504 {
 505         ++*pos;
 506         return c_start(m, pos);
 507 }
 508
 509 static void c_stop(struct seq_file *m, void *v)
 510 {
 511 }
 512
 513 const struct seq_operations cpuinfo_op = {
 514         .start  = c_start,
 515         .next   = c_next,
 516         .stop   = c_stop,
 517         .show   = show_cpuinfo
 518 };
 519
 520 static DEFINE_PER_CPU(struct cpu, cpu_topology);
 521
 522 static int __init topology_init(void)
 523 {
 524         int cpu;
 525
 526         for_each_present_cpu(cpu)
 527             register_cpu(&per_cpu(cpu_topology, cpu), cpu);
 528
 529         return 0;
 530 }
 531
 532 subsys_initcall(topology_init);