GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / am33xx-clocks.dtsi
1 /*
2  * Device Tree Source for AM33xx clock data
3  *
4  * Copyright (C) 2013 Texas Instruments, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 &scm_clocks {
11         sys_clkin_ck: sys_clkin_ck@40 {
12                 #clock-cells = <0>;
13                 compatible = "ti,mux-clock";
14                 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
15                 ti,bit-shift = <22>;
16                 reg = <0x0040>;
17         };
18
19         adc_tsc_fck: adc_tsc_fck {
20                 #clock-cells = <0>;
21                 compatible = "fixed-factor-clock";
22                 clocks = <&sys_clkin_ck>;
23                 clock-mult = <1>;
24                 clock-div = <1>;
25         };
26
27         dcan0_fck: dcan0_fck {
28                 #clock-cells = <0>;
29                 compatible = "fixed-factor-clock";
30                 clocks = <&sys_clkin_ck>;
31                 clock-mult = <1>;
32                 clock-div = <1>;
33         };
34
35         dcan1_fck: dcan1_fck {
36                 #clock-cells = <0>;
37                 compatible = "fixed-factor-clock";
38                 clocks = <&sys_clkin_ck>;
39                 clock-mult = <1>;
40                 clock-div = <1>;
41         };
42
43         mcasp0_fck: mcasp0_fck {
44                 #clock-cells = <0>;
45                 compatible = "fixed-factor-clock";
46                 clocks = <&sys_clkin_ck>;
47                 clock-mult = <1>;
48                 clock-div = <1>;
49         };
50
51         mcasp1_fck: mcasp1_fck {
52                 #clock-cells = <0>;
53                 compatible = "fixed-factor-clock";
54                 clocks = <&sys_clkin_ck>;
55                 clock-mult = <1>;
56                 clock-div = <1>;
57         };
58
59         smartreflex0_fck: smartreflex0_fck {
60                 #clock-cells = <0>;
61                 compatible = "fixed-factor-clock";
62                 clocks = <&sys_clkin_ck>;
63                 clock-mult = <1>;
64                 clock-div = <1>;
65         };
66
67         smartreflex1_fck: smartreflex1_fck {
68                 #clock-cells = <0>;
69                 compatible = "fixed-factor-clock";
70                 clocks = <&sys_clkin_ck>;
71                 clock-mult = <1>;
72                 clock-div = <1>;
73         };
74
75         sha0_fck: sha0_fck {
76                 #clock-cells = <0>;
77                 compatible = "fixed-factor-clock";
78                 clocks = <&sys_clkin_ck>;
79                 clock-mult = <1>;
80                 clock-div = <1>;
81         };
82
83         aes0_fck: aes0_fck {
84                 #clock-cells = <0>;
85                 compatible = "fixed-factor-clock";
86                 clocks = <&sys_clkin_ck>;
87                 clock-mult = <1>;
88                 clock-div = <1>;
89         };
90
91         rng_fck: rng_fck {
92                 #clock-cells = <0>;
93                 compatible = "fixed-factor-clock";
94                 clocks = <&sys_clkin_ck>;
95                 clock-mult = <1>;
96                 clock-div = <1>;
97         };
98
99         ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
100                 #clock-cells = <0>;
101                 compatible = "ti,gate-clock";
102                 clocks = <&l4ls_gclk>;
103                 ti,bit-shift = <0>;
104                 reg = <0x0664>;
105         };
106
107         ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
108                 #clock-cells = <0>;
109                 compatible = "ti,gate-clock";
110                 clocks = <&l4ls_gclk>;
111                 ti,bit-shift = <1>;
112                 reg = <0x0664>;
113         };
114
115         ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
116                 #clock-cells = <0>;
117                 compatible = "ti,gate-clock";
118                 clocks = <&l4ls_gclk>;
119                 ti,bit-shift = <2>;
120                 reg = <0x0664>;
121         };
122 };
123 &prcm_clocks {
124         clk_32768_ck: clk_32768_ck {
125                 #clock-cells = <0>;
126                 compatible = "fixed-clock";
127                 clock-frequency = <32768>;
128         };
129
130         clk_rc32k_ck: clk_rc32k_ck {
131                 #clock-cells = <0>;
132                 compatible = "fixed-clock";
133                 clock-frequency = <32000>;
134         };
135
136         virt_19200000_ck: virt_19200000_ck {
137                 #clock-cells = <0>;
138                 compatible = "fixed-clock";
139                 clock-frequency = <19200000>;
140         };
141
142         virt_24000000_ck: virt_24000000_ck {
143                 #clock-cells = <0>;
144                 compatible = "fixed-clock";
145                 clock-frequency = <24000000>;
146         };
147
148         virt_25000000_ck: virt_25000000_ck {
149                 #clock-cells = <0>;
150                 compatible = "fixed-clock";
151                 clock-frequency = <25000000>;
152         };
153
154         virt_26000000_ck: virt_26000000_ck {
155                 #clock-cells = <0>;
156                 compatible = "fixed-clock";
157                 clock-frequency = <26000000>;
158         };
159
160         tclkin_ck: tclkin_ck {
161                 #clock-cells = <0>;
162                 compatible = "fixed-clock";
163                 clock-frequency = <12000000>;
164         };
165
166         dpll_core_ck: dpll_core_ck@490 {
167                 #clock-cells = <0>;
168                 compatible = "ti,am3-dpll-core-clock";
169                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
170                 reg = <0x0490>, <0x045c>, <0x0468>;
171         };
172
173         dpll_core_x2_ck: dpll_core_x2_ck {
174                 #clock-cells = <0>;
175                 compatible = "ti,am3-dpll-x2-clock";
176                 clocks = <&dpll_core_ck>;
177         };
178
179         dpll_core_m4_ck: dpll_core_m4_ck@480 {
180                 #clock-cells = <0>;
181                 compatible = "ti,divider-clock";
182                 clocks = <&dpll_core_x2_ck>;
183                 ti,max-div = <31>;
184                 reg = <0x0480>;
185                 ti,index-starts-at-one;
186         };
187
188         dpll_core_m5_ck: dpll_core_m5_ck@484 {
189                 #clock-cells = <0>;
190                 compatible = "ti,divider-clock";
191                 clocks = <&dpll_core_x2_ck>;
192                 ti,max-div = <31>;
193                 reg = <0x0484>;
194                 ti,index-starts-at-one;
195         };
196
197         dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
198                 #clock-cells = <0>;
199                 compatible = "ti,divider-clock";
200                 clocks = <&dpll_core_x2_ck>;
201                 ti,max-div = <31>;
202                 reg = <0x04d8>;
203                 ti,index-starts-at-one;
204         };
205
206         dpll_mpu_ck: dpll_mpu_ck@488 {
207                 #clock-cells = <0>;
208                 compatible = "ti,am3-dpll-clock";
209                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
210                 reg = <0x0488>, <0x0420>, <0x042c>;
211         };
212
213         dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
214                 #clock-cells = <0>;
215                 compatible = "ti,divider-clock";
216                 clocks = <&dpll_mpu_ck>;
217                 ti,max-div = <31>;
218                 reg = <0x04a8>;
219                 ti,index-starts-at-one;
220         };
221
222         dpll_ddr_ck: dpll_ddr_ck@494 {
223                 #clock-cells = <0>;
224                 compatible = "ti,am3-dpll-no-gate-clock";
225                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
226                 reg = <0x0494>, <0x0434>, <0x0440>;
227         };
228
229         dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
230                 #clock-cells = <0>;
231                 compatible = "ti,divider-clock";
232                 clocks = <&dpll_ddr_ck>;
233                 ti,max-div = <31>;
234                 reg = <0x04a0>;
235                 ti,index-starts-at-one;
236         };
237
238         dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
239                 #clock-cells = <0>;
240                 compatible = "fixed-factor-clock";
241                 clocks = <&dpll_ddr_m2_ck>;
242                 clock-mult = <1>;
243                 clock-div = <2>;
244         };
245
246         dpll_disp_ck: dpll_disp_ck@498 {
247                 #clock-cells = <0>;
248                 compatible = "ti,am3-dpll-no-gate-clock";
249                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
250                 reg = <0x0498>, <0x0448>, <0x0454>;
251         };
252
253         dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
254                 #clock-cells = <0>;
255                 compatible = "ti,divider-clock";
256                 clocks = <&dpll_disp_ck>;
257                 ti,max-div = <31>;
258                 reg = <0x04a4>;
259                 ti,index-starts-at-one;
260                 ti,set-rate-parent;
261         };
262
263         dpll_per_ck: dpll_per_ck@48c {
264                 #clock-cells = <0>;
265                 compatible = "ti,am3-dpll-no-gate-j-type-clock";
266                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
267                 reg = <0x048c>, <0x0470>, <0x049c>;
268         };
269
270         dpll_per_m2_ck: dpll_per_m2_ck@4ac {
271                 #clock-cells = <0>;
272                 compatible = "ti,divider-clock";
273                 clocks = <&dpll_per_ck>;
274                 ti,max-div = <31>;
275                 reg = <0x04ac>;
276                 ti,index-starts-at-one;
277         };
278
279         dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
280                 #clock-cells = <0>;
281                 compatible = "fixed-factor-clock";
282                 clocks = <&dpll_per_m2_ck>;
283                 clock-mult = <1>;
284                 clock-div = <4>;
285         };
286
287         dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
288                 #clock-cells = <0>;
289                 compatible = "fixed-factor-clock";
290                 clocks = <&dpll_per_m2_ck>;
291                 clock-mult = <1>;
292                 clock-div = <4>;
293         };
294
295         clk_24mhz: clk_24mhz {
296                 #clock-cells = <0>;
297                 compatible = "fixed-factor-clock";
298                 clocks = <&dpll_per_m2_ck>;
299                 clock-mult = <1>;
300                 clock-div = <8>;
301         };
302
303         clkdiv32k_ck: clkdiv32k_ck {
304                 #clock-cells = <0>;
305                 compatible = "fixed-factor-clock";
306                 clocks = <&clk_24mhz>;
307                 clock-mult = <1>;
308                 clock-div = <732>;
309         };
310
311         l3_gclk: l3_gclk {
312                 #clock-cells = <0>;
313                 compatible = "fixed-factor-clock";
314                 clocks = <&dpll_core_m4_ck>;
315                 clock-mult = <1>;
316                 clock-div = <1>;
317         };
318
319         pruss_ocp_gclk: pruss_ocp_gclk@530 {
320                 #clock-cells = <0>;
321                 compatible = "ti,mux-clock";
322                 clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
323                 reg = <0x0530>;
324         };
325
326         mmu_fck: mmu_fck@914 {
327                 #clock-cells = <0>;
328                 compatible = "ti,gate-clock";
329                 clocks = <&dpll_core_m4_ck>;
330                 ti,bit-shift = <1>;
331                 reg = <0x0914>;
332         };
333
334         timer1_fck: timer1_fck@528 {
335                 #clock-cells = <0>;
336                 compatible = "ti,mux-clock";
337                 clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
338                 reg = <0x0528>;
339         };
340
341         timer2_fck: timer2_fck@508 {
342                 #clock-cells = <0>;
343                 compatible = "ti,mux-clock";
344                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
345                 reg = <0x0508>;
346         };
347
348         timer3_fck: timer3_fck@50c {
349                 #clock-cells = <0>;
350                 compatible = "ti,mux-clock";
351                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
352                 reg = <0x050c>;
353         };
354
355         timer4_fck: timer4_fck@510 {
356                 #clock-cells = <0>;
357                 compatible = "ti,mux-clock";
358                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
359                 reg = <0x0510>;
360         };
361
362         timer5_fck: timer5_fck@518 {
363                 #clock-cells = <0>;
364                 compatible = "ti,mux-clock";
365                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
366                 reg = <0x0518>;
367         };
368
369         timer6_fck: timer6_fck@51c {
370                 #clock-cells = <0>;
371                 compatible = "ti,mux-clock";
372                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
373                 reg = <0x051c>;
374         };
375
376         timer7_fck: timer7_fck@504 {
377                 #clock-cells = <0>;
378                 compatible = "ti,mux-clock";
379                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
380                 reg = <0x0504>;
381         };
382
383         usbotg_fck: usbotg_fck@47c {
384                 #clock-cells = <0>;
385                 compatible = "ti,gate-clock";
386                 clocks = <&dpll_per_ck>;
387                 ti,bit-shift = <8>;
388                 reg = <0x047c>;
389         };
390
391         dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
392                 #clock-cells = <0>;
393                 compatible = "fixed-factor-clock";
394                 clocks = <&dpll_core_m4_ck>;
395                 clock-mult = <1>;
396                 clock-div = <2>;
397         };
398
399         ieee5000_fck: ieee5000_fck@e4 {
400                 #clock-cells = <0>;
401                 compatible = "ti,gate-clock";
402                 clocks = <&dpll_core_m4_div2_ck>;
403                 ti,bit-shift = <1>;
404                 reg = <0x00e4>;
405         };
406
407         wdt1_fck: wdt1_fck@538 {
408                 #clock-cells = <0>;
409                 compatible = "ti,mux-clock";
410                 clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
411                 reg = <0x0538>;
412         };
413
414         l4_rtc_gclk: l4_rtc_gclk {
415                 #clock-cells = <0>;
416                 compatible = "fixed-factor-clock";
417                 clocks = <&dpll_core_m4_ck>;
418                 clock-mult = <1>;
419                 clock-div = <2>;
420         };
421
422         l4hs_gclk: l4hs_gclk {
423                 #clock-cells = <0>;
424                 compatible = "fixed-factor-clock";
425                 clocks = <&dpll_core_m4_ck>;
426                 clock-mult = <1>;
427                 clock-div = <1>;
428         };
429
430         l3s_gclk: l3s_gclk {
431                 #clock-cells = <0>;
432                 compatible = "fixed-factor-clock";
433                 clocks = <&dpll_core_m4_div2_ck>;
434                 clock-mult = <1>;
435                 clock-div = <1>;
436         };
437
438         l4fw_gclk: l4fw_gclk {
439                 #clock-cells = <0>;
440                 compatible = "fixed-factor-clock";
441                 clocks = <&dpll_core_m4_div2_ck>;
442                 clock-mult = <1>;
443                 clock-div = <1>;
444         };
445
446         l4ls_gclk: l4ls_gclk {
447                 #clock-cells = <0>;
448                 compatible = "fixed-factor-clock";
449                 clocks = <&dpll_core_m4_div2_ck>;
450                 clock-mult = <1>;
451                 clock-div = <1>;
452         };
453
454         sysclk_div_ck: sysclk_div_ck {
455                 #clock-cells = <0>;
456                 compatible = "fixed-factor-clock";
457                 clocks = <&dpll_core_m4_ck>;
458                 clock-mult = <1>;
459                 clock-div = <1>;
460         };
461
462         cpsw_125mhz_gclk: cpsw_125mhz_gclk {
463                 #clock-cells = <0>;
464                 compatible = "fixed-factor-clock";
465                 clocks = <&dpll_core_m5_ck>;
466                 clock-mult = <1>;
467                 clock-div = <2>;
468         };
469
470         cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
471                 #clock-cells = <0>;
472                 compatible = "ti,mux-clock";
473                 clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
474                 reg = <0x0520>;
475         };
476
477         gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
478                 #clock-cells = <0>;
479                 compatible = "ti,mux-clock";
480                 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
481                 reg = <0x053c>;
482         };
483
484         lcd_gclk: lcd_gclk@534 {
485                 #clock-cells = <0>;
486                 compatible = "ti,mux-clock";
487                 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
488                 reg = <0x0534>;
489                 ti,set-rate-parent;
490         };
491
492         mmc_clk: mmc_clk {
493                 #clock-cells = <0>;
494                 compatible = "fixed-factor-clock";
495                 clocks = <&dpll_per_m2_ck>;
496                 clock-mult = <1>;
497                 clock-div = <2>;
498         };
499
500         gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
501                 #clock-cells = <0>;
502                 compatible = "ti,mux-clock";
503                 clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
504                 ti,bit-shift = <1>;
505                 reg = <0x052c>;
506         };
507
508         gfx_fck_div_ck: gfx_fck_div_ck@52c {
509                 #clock-cells = <0>;
510                 compatible = "ti,divider-clock";
511                 clocks = <&gfx_fclk_clksel_ck>;
512                 reg = <0x052c>;
513                 ti,max-div = <2>;
514         };
515
516         sysclkout_pre_ck: sysclkout_pre_ck@700 {
517                 #clock-cells = <0>;
518                 compatible = "ti,mux-clock";
519                 clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
520                 reg = <0x0700>;
521         };
522
523         clkout2_div_ck: clkout2_div_ck@700 {
524                 #clock-cells = <0>;
525                 compatible = "ti,divider-clock";
526                 clocks = <&sysclkout_pre_ck>;
527                 ti,bit-shift = <3>;
528                 ti,max-div = <8>;
529                 reg = <0x0700>;
530         };
531
532         clkout2_ck: clkout2_ck@700 {
533                 #clock-cells = <0>;
534                 compatible = "ti,gate-clock";
535                 clocks = <&clkout2_div_ck>;
536                 ti,bit-shift = <7>;
537                 reg = <0x0700>;
538         };
539 };
540
541 &prcm {
542         l4_per_cm: l4_per_cm@0 {
543                 compatible = "ti,omap4-cm";
544                 reg = <0x0 0x200>;
545                 #address-cells = <1>;
546                 #size-cells = <1>;
547                 ranges = <0 0x0 0x200>;
548
549                 l4_per_clkctrl: clk@14 {
550                         compatible = "ti,clkctrl";
551                         reg = <0x14 0x13c>;
552                         #clock-cells = <2>;
553                 };
554         };
555
556         l4_wkup_cm: l4_wkup_cm@400 {
557                 compatible = "ti,omap4-cm";
558                 reg = <0x400 0x100>;
559                 #address-cells = <1>;
560                 #size-cells = <1>;
561                 ranges = <0 0x400 0x100>;
562
563                 l4_wkup_clkctrl: clk@4 {
564                         compatible = "ti,clkctrl";
565                         reg = <0x4 0xd4>;
566                         #clock-cells = <2>;
567                 };
568         };
569
570         mpu_cm: mpu_cm@600 {
571                 compatible = "ti,omap4-cm";
572                 reg = <0x600 0x100>;
573                 #address-cells = <1>;
574                 #size-cells = <1>;
575                 ranges = <0 0x600 0x100>;
576
577                 mpu_clkctrl: clk@4 {
578                         compatible = "ti,clkctrl";
579                         reg = <0x4 0x4>;
580                         #clock-cells = <2>;
581                 };
582         };
583
584         l4_rtc_cm: l4_rtc_cm@800 {
585                 compatible = "ti,omap4-cm";
586                 reg = <0x800 0x100>;
587                 #address-cells = <1>;
588                 #size-cells = <1>;
589                 ranges = <0 0x800 0x100>;
590
591                 l4_rtc_clkctrl: clk@0 {
592                         compatible = "ti,clkctrl";
593                         reg = <0x0 0x4>;
594                         #clock-cells = <2>;
595                 };
596         };
597
598         gfx_l3_cm: gfx_l3_cm@900 {
599                 compatible = "ti,omap4-cm";
600                 reg = <0x900 0x100>;
601                 #address-cells = <1>;
602                 #size-cells = <1>;
603                 ranges = <0 0x900 0x100>;
604
605                 gfx_l3_clkctrl: clk@4 {
606                         compatible = "ti,clkctrl";
607                         reg = <0x4 0x4>;
608                         #clock-cells = <2>;
609                 };
610         };
611
612         l4_cefuse_cm: l4_cefuse_cm@a00 {
613                 compatible = "ti,omap4-cm";
614                 reg = <0xa00 0x100>;
615                 #address-cells = <1>;
616                 #size-cells = <1>;
617                 ranges = <0 0xa00 0x100>;
618
619                 l4_cefuse_clkctrl: clk@20 {
620                         compatible = "ti,clkctrl";
621                         reg = <0x20 0x4>;
622                         #clock-cells = <2>;
623                 };
624         };
625 };