GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / am43xx-clocks.dtsi
1 /*
2  * Device Tree Source for AM43xx clock data
3  *
4  * Copyright (C) 2013 Texas Instruments, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 &scm_clocks {
11         sys_clkin_ck: sys_clkin_ck@40 {
12                 #clock-cells = <0>;
13                 compatible = "ti,mux-clock";
14                 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
15                 ti,bit-shift = <31>;
16                 reg = <0x0040>;
17         };
18
19         crystal_freq_sel_ck: crystal_freq_sel_ck@40 {
20                 #clock-cells = <0>;
21                 compatible = "ti,mux-clock";
22                 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
23                 ti,bit-shift = <29>;
24                 reg = <0x0040>;
25         };
26
27         sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
28                 #clock-cells = <0>;
29                 compatible = "ti,mux-clock";
30                 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
31                 ti,bit-shift = <22>;
32                 reg = <0x0040>;
33         };
34
35         adc_tsc_fck: adc_tsc_fck {
36                 #clock-cells = <0>;
37                 compatible = "fixed-factor-clock";
38                 clocks = <&sys_clkin_ck>;
39                 clock-mult = <1>;
40                 clock-div = <1>;
41         };
42
43         dcan0_fck: dcan0_fck {
44                 #clock-cells = <0>;
45                 compatible = "fixed-factor-clock";
46                 clocks = <&sys_clkin_ck>;
47                 clock-mult = <1>;
48                 clock-div = <1>;
49         };
50
51         dcan1_fck: dcan1_fck {
52                 #clock-cells = <0>;
53                 compatible = "fixed-factor-clock";
54                 clocks = <&sys_clkin_ck>;
55                 clock-mult = <1>;
56                 clock-div = <1>;
57         };
58
59         mcasp0_fck: mcasp0_fck {
60                 #clock-cells = <0>;
61                 compatible = "fixed-factor-clock";
62                 clocks = <&sys_clkin_ck>;
63                 clock-mult = <1>;
64                 clock-div = <1>;
65         };
66
67         mcasp1_fck: mcasp1_fck {
68                 #clock-cells = <0>;
69                 compatible = "fixed-factor-clock";
70                 clocks = <&sys_clkin_ck>;
71                 clock-mult = <1>;
72                 clock-div = <1>;
73         };
74
75         smartreflex0_fck: smartreflex0_fck {
76                 #clock-cells = <0>;
77                 compatible = "fixed-factor-clock";
78                 clocks = <&sys_clkin_ck>;
79                 clock-mult = <1>;
80                 clock-div = <1>;
81         };
82
83         smartreflex1_fck: smartreflex1_fck {
84                 #clock-cells = <0>;
85                 compatible = "fixed-factor-clock";
86                 clocks = <&sys_clkin_ck>;
87                 clock-mult = <1>;
88                 clock-div = <1>;
89         };
90
91         sha0_fck: sha0_fck {
92                 #clock-cells = <0>;
93                 compatible = "fixed-factor-clock";
94                 clocks = <&sys_clkin_ck>;
95                 clock-mult = <1>;
96                 clock-div = <1>;
97         };
98
99         aes0_fck: aes0_fck {
100                 #clock-cells = <0>;
101                 compatible = "fixed-factor-clock";
102                 clocks = <&sys_clkin_ck>;
103                 clock-mult = <1>;
104                 clock-div = <1>;
105         };
106
107         rng_fck: rng_fck {
108                 #clock-cells = <0>;
109                 compatible = "fixed-factor-clock";
110                 clocks = <&sys_clkin_ck>;
111                 clock-mult = <1>;
112                 clock-div = <1>;
113         };
114
115         ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
116                 #clock-cells = <0>;
117                 compatible = "ti,gate-clock";
118                 clocks = <&l4ls_gclk>;
119                 ti,bit-shift = <0>;
120                 reg = <0x0664>;
121         };
122
123         ehrpwm1_tbclk: ehrpwm1_tbclk@664 {
124                 #clock-cells = <0>;
125                 compatible = "ti,gate-clock";
126                 clocks = <&l4ls_gclk>;
127                 ti,bit-shift = <1>;
128                 reg = <0x0664>;
129         };
130
131         ehrpwm2_tbclk: ehrpwm2_tbclk@664 {
132                 #clock-cells = <0>;
133                 compatible = "ti,gate-clock";
134                 clocks = <&l4ls_gclk>;
135                 ti,bit-shift = <2>;
136                 reg = <0x0664>;
137         };
138
139         ehrpwm3_tbclk: ehrpwm3_tbclk@664 {
140                 #clock-cells = <0>;
141                 compatible = "ti,gate-clock";
142                 clocks = <&l4ls_gclk>;
143                 ti,bit-shift = <4>;
144                 reg = <0x0664>;
145         };
146
147         ehrpwm4_tbclk: ehrpwm4_tbclk@664 {
148                 #clock-cells = <0>;
149                 compatible = "ti,gate-clock";
150                 clocks = <&l4ls_gclk>;
151                 ti,bit-shift = <5>;
152                 reg = <0x0664>;
153         };
154
155         ehrpwm5_tbclk: ehrpwm5_tbclk@664 {
156                 #clock-cells = <0>;
157                 compatible = "ti,gate-clock";
158                 clocks = <&l4ls_gclk>;
159                 ti,bit-shift = <6>;
160                 reg = <0x0664>;
161         };
162 };
163 &prcm_clocks {
164         clk_32768_ck: clk_32768_ck {
165                 #clock-cells = <0>;
166                 compatible = "fixed-clock";
167                 clock-frequency = <32768>;
168         };
169
170         clk_rc32k_ck: clk_rc32k_ck {
171                 #clock-cells = <0>;
172                 compatible = "fixed-clock";
173                 clock-frequency = <32768>;
174         };
175
176         virt_19200000_ck: virt_19200000_ck {
177                 #clock-cells = <0>;
178                 compatible = "fixed-clock";
179                 clock-frequency = <19200000>;
180         };
181
182         virt_24000000_ck: virt_24000000_ck {
183                 #clock-cells = <0>;
184                 compatible = "fixed-clock";
185                 clock-frequency = <24000000>;
186         };
187
188         virt_25000000_ck: virt_25000000_ck {
189                 #clock-cells = <0>;
190                 compatible = "fixed-clock";
191                 clock-frequency = <25000000>;
192         };
193
194         virt_26000000_ck: virt_26000000_ck {
195                 #clock-cells = <0>;
196                 compatible = "fixed-clock";
197                 clock-frequency = <26000000>;
198         };
199
200         tclkin_ck: tclkin_ck {
201                 #clock-cells = <0>;
202                 compatible = "fixed-clock";
203                 clock-frequency = <26000000>;
204         };
205
206         dpll_core_ck: dpll_core_ck@2d20 {
207                 #clock-cells = <0>;
208                 compatible = "ti,am3-dpll-core-clock";
209                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
210                 reg = <0x2d20>, <0x2d24>, <0x2d2c>;
211         };
212
213         dpll_core_x2_ck: dpll_core_x2_ck {
214                 #clock-cells = <0>;
215                 compatible = "ti,am3-dpll-x2-clock";
216                 clocks = <&dpll_core_ck>;
217         };
218
219         dpll_core_m4_ck: dpll_core_m4_ck@2d38 {
220                 #clock-cells = <0>;
221                 compatible = "ti,divider-clock";
222                 clocks = <&dpll_core_x2_ck>;
223                 ti,max-div = <31>;
224                 ti,autoidle-shift = <8>;
225                 reg = <0x2d38>;
226                 ti,index-starts-at-one;
227                 ti,invert-autoidle-bit;
228         };
229
230         dpll_core_m5_ck: dpll_core_m5_ck@2d3c {
231                 #clock-cells = <0>;
232                 compatible = "ti,divider-clock";
233                 clocks = <&dpll_core_x2_ck>;
234                 ti,max-div = <31>;
235                 ti,autoidle-shift = <8>;
236                 reg = <0x2d3c>;
237                 ti,index-starts-at-one;
238                 ti,invert-autoidle-bit;
239         };
240
241         dpll_core_m6_ck: dpll_core_m6_ck@2d40 {
242                 #clock-cells = <0>;
243                 compatible = "ti,divider-clock";
244                 clocks = <&dpll_core_x2_ck>;
245                 ti,max-div = <31>;
246                 ti,autoidle-shift = <8>;
247                 reg = <0x2d40>;
248                 ti,index-starts-at-one;
249                 ti,invert-autoidle-bit;
250         };
251
252         dpll_mpu_ck: dpll_mpu_ck@2d60 {
253                 #clock-cells = <0>;
254                 compatible = "ti,am3-dpll-clock";
255                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
256                 reg = <0x2d60>, <0x2d64>, <0x2d6c>;
257         };
258
259         dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
260                 #clock-cells = <0>;
261                 compatible = "ti,divider-clock";
262                 clocks = <&dpll_mpu_ck>;
263                 ti,max-div = <31>;
264                 ti,autoidle-shift = <8>;
265                 reg = <0x2d70>;
266                 ti,index-starts-at-one;
267                 ti,invert-autoidle-bit;
268         };
269
270         mpu_periphclk: mpu_periphclk {
271                 #clock-cells = <0>;
272                 compatible = "fixed-factor-clock";
273                 clocks = <&dpll_mpu_m2_ck>;
274                 clock-mult = <1>;
275                 clock-div = <2>;
276         };
277
278         dpll_ddr_ck: dpll_ddr_ck@2da0 {
279                 #clock-cells = <0>;
280                 compatible = "ti,am3-dpll-clock";
281                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
282                 reg = <0x2da0>, <0x2da4>, <0x2dac>;
283         };
284
285         dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
286                 #clock-cells = <0>;
287                 compatible = "ti,divider-clock";
288                 clocks = <&dpll_ddr_ck>;
289                 ti,max-div = <31>;
290                 ti,autoidle-shift = <8>;
291                 reg = <0x2db0>;
292                 ti,index-starts-at-one;
293                 ti,invert-autoidle-bit;
294         };
295
296         dpll_disp_ck: dpll_disp_ck@2e20 {
297                 #clock-cells = <0>;
298                 compatible = "ti,am3-dpll-clock";
299                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
300                 reg = <0x2e20>, <0x2e24>, <0x2e2c>;
301         };
302
303         dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
304                 #clock-cells = <0>;
305                 compatible = "ti,divider-clock";
306                 clocks = <&dpll_disp_ck>;
307                 ti,max-div = <31>;
308                 ti,autoidle-shift = <8>;
309                 reg = <0x2e30>;
310                 ti,index-starts-at-one;
311                 ti,invert-autoidle-bit;
312                 ti,set-rate-parent;
313         };
314
315         dpll_per_ck: dpll_per_ck@2de0 {
316                 #clock-cells = <0>;
317                 compatible = "ti,am3-dpll-j-type-clock";
318                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
319                 reg = <0x2de0>, <0x2de4>, <0x2dec>;
320         };
321
322         dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
323                 #clock-cells = <0>;
324                 compatible = "ti,divider-clock";
325                 clocks = <&dpll_per_ck>;
326                 ti,max-div = <127>;
327                 ti,autoidle-shift = <8>;
328                 reg = <0x2df0>;
329                 ti,index-starts-at-one;
330                 ti,invert-autoidle-bit;
331         };
332
333         dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
334                 #clock-cells = <0>;
335                 compatible = "fixed-factor-clock";
336                 clocks = <&dpll_per_m2_ck>;
337                 clock-mult = <1>;
338                 clock-div = <4>;
339         };
340
341         dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
342                 #clock-cells = <0>;
343                 compatible = "fixed-factor-clock";
344                 clocks = <&dpll_per_m2_ck>;
345                 clock-mult = <1>;
346                 clock-div = <4>;
347         };
348
349         clk_24mhz: clk_24mhz {
350                 #clock-cells = <0>;
351                 compatible = "fixed-factor-clock";
352                 clocks = <&dpll_per_m2_ck>;
353                 clock-mult = <1>;
354                 clock-div = <8>;
355         };
356
357         clkdiv32k_ck: clkdiv32k_ck {
358                 #clock-cells = <0>;
359                 compatible = "fixed-factor-clock";
360                 clocks = <&clk_24mhz>;
361                 clock-mult = <1>;
362                 clock-div = <732>;
363         };
364
365         clkdiv32k_ick: clkdiv32k_ick@2a38 {
366                 #clock-cells = <0>;
367                 compatible = "ti,gate-clock";
368                 clocks = <&clkdiv32k_ck>;
369                 ti,bit-shift = <8>;
370                 reg = <0x2a38>;
371         };
372
373         sysclk_div: sysclk_div {
374                 #clock-cells = <0>;
375                 compatible = "fixed-factor-clock";
376                 clocks = <&dpll_core_m4_ck>;
377                 clock-mult = <1>;
378                 clock-div = <1>;
379         };
380
381         pruss_ocp_gclk: pruss_ocp_gclk@4248 {
382                 #clock-cells = <0>;
383                 compatible = "ti,mux-clock";
384                 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
385                 reg = <0x4248>;
386         };
387
388         clk_32k_tpm_ck: clk_32k_tpm_ck {
389                 #clock-cells = <0>;
390                 compatible = "fixed-clock";
391                 clock-frequency = <32768>;
392         };
393
394         timer1_fck: timer1_fck@4200 {
395                 #clock-cells = <0>;
396                 compatible = "ti,mux-clock";
397                 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
398                 reg = <0x4200>;
399         };
400
401         timer2_fck: timer2_fck@4204 {
402                 #clock-cells = <0>;
403                 compatible = "ti,mux-clock";
404                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
405                 reg = <0x4204>;
406         };
407
408         timer3_fck: timer3_fck@4208 {
409                 #clock-cells = <0>;
410                 compatible = "ti,mux-clock";
411                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
412                 reg = <0x4208>;
413         };
414
415         timer4_fck: timer4_fck@420c {
416                 #clock-cells = <0>;
417                 compatible = "ti,mux-clock";
418                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
419                 reg = <0x420c>;
420         };
421
422         timer5_fck: timer5_fck@4210 {
423                 #clock-cells = <0>;
424                 compatible = "ti,mux-clock";
425                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
426                 reg = <0x4210>;
427         };
428
429         timer6_fck: timer6_fck@4214 {
430                 #clock-cells = <0>;
431                 compatible = "ti,mux-clock";
432                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
433                 reg = <0x4214>;
434         };
435
436         timer7_fck: timer7_fck@4218 {
437                 #clock-cells = <0>;
438                 compatible = "ti,mux-clock";
439                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
440                 reg = <0x4218>;
441         };
442
443         wdt1_fck: wdt1_fck@422c {
444                 #clock-cells = <0>;
445                 compatible = "ti,mux-clock";
446                 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
447                 reg = <0x422c>;
448         };
449
450         l3_gclk: l3_gclk {
451                 #clock-cells = <0>;
452                 compatible = "fixed-factor-clock";
453                 clocks = <&dpll_core_m4_ck>;
454                 clock-mult = <1>;
455                 clock-div = <1>;
456         };
457
458         dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
459                 #clock-cells = <0>;
460                 compatible = "fixed-factor-clock";
461                 clocks = <&sysclk_div>;
462                 clock-mult = <1>;
463                 clock-div = <2>;
464         };
465
466         l4hs_gclk: l4hs_gclk {
467                 #clock-cells = <0>;
468                 compatible = "fixed-factor-clock";
469                 clocks = <&dpll_core_m4_ck>;
470                 clock-mult = <1>;
471                 clock-div = <1>;
472         };
473
474         l3s_gclk: l3s_gclk {
475                 #clock-cells = <0>;
476                 compatible = "fixed-factor-clock";
477                 clocks = <&dpll_core_m4_div2_ck>;
478                 clock-mult = <1>;
479                 clock-div = <1>;
480         };
481
482         l4ls_gclk: l4ls_gclk {
483                 #clock-cells = <0>;
484                 compatible = "fixed-factor-clock";
485                 clocks = <&dpll_core_m4_div2_ck>;
486                 clock-mult = <1>;
487                 clock-div = <1>;
488         };
489
490         cpsw_125mhz_gclk: cpsw_125mhz_gclk {
491                 #clock-cells = <0>;
492                 compatible = "fixed-factor-clock";
493                 clocks = <&dpll_core_m5_ck>;
494                 clock-mult = <1>;
495                 clock-div = <2>;
496         };
497
498         cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 {
499                 #clock-cells = <0>;
500                 compatible = "ti,mux-clock";
501                 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
502                 reg = <0x4238>;
503         };
504
505         dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 {
506                 #clock-cells = <0>;
507                 compatible = "ti,divider-clock";
508                 clocks = <&dpll_core_m5_ck>;
509                 reg = <0x4234>;
510                 ti,bit-shift = <2>;
511                 ti,dividers = <2>, <5>;
512         };
513
514         clk_32k_mosc_ck: clk_32k_mosc_ck {
515                 #clock-cells = <0>;
516                 compatible = "fixed-clock";
517                 clock-frequency = <32768>;
518         };
519
520         gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 {
521                 #clock-cells = <0>;
522                 compatible = "ti,mux-clock";
523                 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
524                 reg = <0x4240>;
525         };
526
527         mmc_clk: mmc_clk {
528                 #clock-cells = <0>;
529                 compatible = "fixed-factor-clock";
530                 clocks = <&dpll_per_m2_ck>;
531                 clock-mult = <1>;
532                 clock-div = <2>;
533         };
534
535         gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c {
536                 #clock-cells = <0>;
537                 compatible = "ti,mux-clock";
538                 clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
539                 ti,bit-shift = <1>;
540                 reg = <0x423c>;
541         };
542
543         gfx_fck_div_ck: gfx_fck_div_ck@423c {
544                 #clock-cells = <0>;
545                 compatible = "ti,divider-clock";
546                 clocks = <&gfx_fclk_clksel_ck>;
547                 reg = <0x423c>;
548                 ti,max-div = <2>;
549         };
550
551         disp_clk: disp_clk@4244 {
552                 #clock-cells = <0>;
553                 compatible = "ti,mux-clock";
554                 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
555                 reg = <0x4244>;
556                 ti,set-rate-parent;
557         };
558
559         dpll_extdev_ck: dpll_extdev_ck@2e60 {
560                 #clock-cells = <0>;
561                 compatible = "ti,am3-dpll-clock";
562                 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
563                 reg = <0x2e60>, <0x2e64>, <0x2e6c>;
564         };
565
566         dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {
567                 #clock-cells = <0>;
568                 compatible = "ti,divider-clock";
569                 clocks = <&dpll_extdev_ck>;
570                 ti,max-div = <127>;
571                 ti,autoidle-shift = <8>;
572                 reg = <0x2e70>;
573                 ti,index-starts-at-one;
574                 ti,invert-autoidle-bit;
575         };
576
577         mux_synctimer32k_ck: mux_synctimer32k_ck@4230 {
578                 #clock-cells = <0>;
579                 compatible = "ti,mux-clock";
580                 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
581                 reg = <0x4230>;
582         };
583
584         timer8_fck: timer8_fck@421c {
585                 #clock-cells = <0>;
586                 compatible = "ti,mux-clock";
587                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
588                 reg = <0x421c>;
589         };
590
591         timer9_fck: timer9_fck@4220 {
592                 #clock-cells = <0>;
593                 compatible = "ti,mux-clock";
594                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
595                 reg = <0x4220>;
596         };
597
598         timer10_fck: timer10_fck@4224 {
599                 #clock-cells = <0>;
600                 compatible = "ti,mux-clock";
601                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
602                 reg = <0x4224>;
603         };
604
605         timer11_fck: timer11_fck@4228 {
606                 #clock-cells = <0>;
607                 compatible = "ti,mux-clock";
608                 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
609                 reg = <0x4228>;
610         };
611
612         cpsw_50m_clkdiv: cpsw_50m_clkdiv {
613                 #clock-cells = <0>;
614                 compatible = "fixed-factor-clock";
615                 clocks = <&dpll_core_m5_ck>;
616                 clock-mult = <1>;
617                 clock-div = <1>;
618         };
619
620         cpsw_5m_clkdiv: cpsw_5m_clkdiv {
621                 #clock-cells = <0>;
622                 compatible = "fixed-factor-clock";
623                 clocks = <&cpsw_50m_clkdiv>;
624                 clock-mult = <1>;
625                 clock-div = <10>;
626         };
627
628         dpll_ddr_x2_ck: dpll_ddr_x2_ck {
629                 #clock-cells = <0>;
630                 compatible = "ti,am3-dpll-x2-clock";
631                 clocks = <&dpll_ddr_ck>;
632         };
633
634         dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 {
635                 #clock-cells = <0>;
636                 compatible = "ti,divider-clock";
637                 clocks = <&dpll_ddr_x2_ck>;
638                 ti,max-div = <31>;
639                 ti,autoidle-shift = <8>;
640                 reg = <0x2db8>;
641                 ti,index-starts-at-one;
642                 ti,invert-autoidle-bit;
643         };
644
645         dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 {
646                 #clock-cells = <0>;
647                 compatible = "ti,fixed-factor-clock";
648                 clocks = <&dpll_per_ck>;
649                 ti,clock-mult = <1>;
650                 ti,clock-div = <1>;
651                 ti,autoidle-shift = <8>;
652                 reg = <0x2e14>;
653                 ti,invert-autoidle-bit;
654         };
655
656         dll_aging_clk_div: dll_aging_clk_div@4250 {
657                 #clock-cells = <0>;
658                 compatible = "ti,divider-clock";
659                 clocks = <&sys_clkin_ck>;
660                 reg = <0x4250>;
661                 ti,dividers = <8>, <16>, <32>;
662         };
663
664         div_core_25m_ck: div_core_25m_ck {
665                 #clock-cells = <0>;
666                 compatible = "fixed-factor-clock";
667                 clocks = <&sysclk_div>;
668                 clock-mult = <1>;
669                 clock-div = <8>;
670         };
671
672         func_12m_clk: func_12m_clk {
673                 #clock-cells = <0>;
674                 compatible = "fixed-factor-clock";
675                 clocks = <&dpll_per_m2_ck>;
676                 clock-mult = <1>;
677                 clock-div = <16>;
678         };
679
680         vtp_clk_div: vtp_clk_div {
681                 #clock-cells = <0>;
682                 compatible = "fixed-factor-clock";
683                 clocks = <&sys_clkin_ck>;
684                 clock-mult = <1>;
685                 clock-div = <2>;
686         };
687
688         usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 {
689                 #clock-cells = <0>;
690                 compatible = "ti,mux-clock";
691                 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
692                 reg = <0x4260>;
693         };
694
695         usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
696                 #clock-cells = <0>;
697                 compatible = "ti,gate-clock";
698                 clocks = <&usbphy_32khz_clkmux>;
699                 ti,bit-shift = <8>;
700                 reg = <0x2a40>;
701         };
702
703         usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
704                 #clock-cells = <0>;
705                 compatible = "ti,gate-clock";
706                 clocks = <&usbphy_32khz_clkmux>;
707                 ti,bit-shift = <8>;
708                 reg = <0x2a48>;
709         };
710
711         clkout1_osc_div_ck: clkout1-osc-div-ck {
712                 #clock-cells = <0>;
713                 compatible = "ti,divider-clock";
714                 clocks = <&sys_clkin_ck>;
715                 ti,bit-shift = <20>;
716                 ti,max-div = <4>;
717                 reg = <0x4100>;
718         };
719
720         clkout1_src2_mux_ck: clkout1-src2-mux-ck {
721                 #clock-cells = <0>;
722                 compatible = "ti,mux-clock";
723                 clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
724                          <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
725                          <&dpll_mpu_m2_ck>;
726                 reg = <0x4100>;
727         };
728
729         clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck {
730                 #clock-cells = <0>;
731                 compatible = "ti,divider-clock";
732                 clocks = <&clkout1_src2_mux_ck>;
733                 ti,bit-shift = <4>;
734                 ti,max-div = <8>;
735                 reg = <0x4100>;
736         };
737
738         clkout1_src2_post_div_ck: clkout1-src2-post-div-ck {
739                 #clock-cells = <0>;
740                 compatible = "ti,divider-clock";
741                 clocks = <&clkout1_src2_pre_div_ck>;
742                 ti,bit-shift = <8>;
743                 ti,max-div = <32>;
744                 ti,index-power-of-two;
745                 reg = <0x4100>;
746         };
747
748         clkout1_mux_ck: clkout1-mux-ck {
749                 #clock-cells = <0>;
750                 compatible = "ti,mux-clock";
751                 clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
752                          <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
753                 ti,bit-shift = <16>;
754                 reg = <0x4100>;
755         };
756
757         clkout1_ck: clkout1-ck {
758                 #clock-cells = <0>;
759                 compatible = "ti,gate-clock";
760                 clocks = <&clkout1_mux_ck>;
761                 ti,bit-shift = <23>;
762                 reg = <0x4100>;
763         };
764 };
765
766 &prcm {
767         l4_wkup_cm: l4_wkup_cm@2800 {
768                 compatible = "ti,omap4-cm";
769                 reg = <0x2800 0x400>;
770                 #address-cells = <1>;
771                 #size-cells = <1>;
772                 ranges = <0 0x2800 0x400>;
773
774                 l4_wkup_clkctrl: clk@20 {
775                         compatible = "ti,clkctrl";
776                         reg = <0x20 0x34c>;
777                         #clock-cells = <2>;
778                 };
779         };
780
781         mpu_cm: mpu_cm@8300 {
782                 compatible = "ti,omap4-cm";
783                 reg = <0x8300 0x100>;
784                 #address-cells = <1>;
785                 #size-cells = <1>;
786                 ranges = <0 0x8300 0x100>;
787
788                 mpu_clkctrl: clk@20 {
789                         compatible = "ti,clkctrl";
790                         reg = <0x20 0x4>;
791                         #clock-cells = <2>;
792                 };
793         };
794
795         gfx_l3_cm: gfx_l3_cm@8400 {
796                 compatible = "ti,omap4-cm";
797                 reg = <0x8400 0x100>;
798                 #address-cells = <1>;
799                 #size-cells = <1>;
800                 ranges = <0 0x8400 0x100>;
801
802                 gfx_l3_clkctrl: clk@20 {
803                         compatible = "ti,clkctrl";
804                         reg = <0x20 0x4>;
805                         #clock-cells = <2>;
806                 };
807         };
808
809         l4_rtc_cm: l4_rtc_cm@8500 {
810                 compatible = "ti,omap4-cm";
811                 reg = <0x8500 0x100>;
812                 #address-cells = <1>;
813                 #size-cells = <1>;
814                 ranges = <0 0x8500 0x100>;
815
816                 l4_rtc_clkctrl: clk@20 {
817                         compatible = "ti,clkctrl";
818                         reg = <0x20 0x4>;
819                         #clock-cells = <2>;
820                 };
821         };
822
823         l4_per_cm: l4_per_cm@8800 {
824                 compatible = "ti,omap4-cm";
825                 reg = <0x8800 0xc00>;
826                 #address-cells = <1>;
827                 #size-cells = <1>;
828                 ranges = <0 0x8800 0xc00>;
829
830                 l4_per_clkctrl: clk@20 {
831                         compatible = "ti,clkctrl";
832                         reg = <0x20 0xb04>;
833                         #clock-cells = <2>;
834                 };
835         };
836 };