GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / arm-realview-pb1176.dts
1 /*
2  * Copyright 2014 Linaro Ltd
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a copy
5  * of this software and associated documentation files (the "Software"), to deal
6  * in the Software without restriction, including without limitation the rights
7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8  * copies of the Software, and to permit persons to whom the Software is
9  * furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20  * THE SOFTWARE.
21  */
22
23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include "skeleton.dtsi"
27
28 / {
29         model = "ARM RealView PB1176";
30         compatible = "arm,realview-pb1176";
31
32         chosen { };
33
34         aliases {
35                 serial0 = &pb1176_serial0;
36                 serial1 = &pb1176_serial1;
37                 serial2 = &pb1176_serial2;
38                 serial3 = &pb1176_serial3;
39                 serial4 = &fpga_serial;
40         };
41
42         memory {
43                 /* 128 MiB memory @ 0x0 */
44                 reg = <0x00000000 0x08000000>;
45         };
46
47         /* The voltage to the MMC card is hardwired at 3.3V */
48         vmmc: regulator-vmmc {
49                 compatible = "regulator-fixed";
50                 regulator-name = "vmmc";
51                 regulator-min-microvolt = <3300000>;
52                 regulator-max-microvolt = <3300000>;
53                 regulator-boot-on;
54         };
55
56         veth: regulator-veth {
57                 compatible = "regulator-fixed";
58                 regulator-name = "veth";
59                 regulator-min-microvolt = <3300000>;
60                 regulator-max-microvolt = <3300000>;
61                 regulator-boot-on;
62         };
63
64         xtal24mhz: xtal24mhz@24M {
65                 #clock-cells = <0>;
66                 compatible = "fixed-clock";
67                 clock-frequency = <24000000>;
68         };
69
70         timclk: timclk@1M {
71                 #clock-cells = <0>;
72                 compatible = "fixed-factor-clock";
73                 clock-div = <24>;
74                 clock-mult = <1>;
75                 clocks = <&xtal24mhz>;
76         };
77
78         mclk: mclk@24M {
79                 #clock-cells = <0>;
80                 compatible = "fixed-factor-clock";
81                 clock-div = <1>;
82                 clock-mult = <1>;
83                 clocks = <&xtal24mhz>;
84         };
85
86         kmiclk: kmiclk@24M {
87                 #clock-cells = <0>;
88                 compatible = "fixed-factor-clock";
89                 clock-div = <1>;
90                 clock-mult = <1>;
91                 clocks = <&xtal24mhz>;
92         };
93
94         sspclk: sspclk@24M {
95                 #clock-cells = <0>;
96                 compatible = "fixed-factor-clock";
97                 clock-div = <1>;
98                 clock-mult = <1>;
99                 clocks = <&xtal24mhz>;
100         };
101
102         uartclk: uartclk@24M {
103                 #clock-cells = <0>;
104                 compatible = "fixed-factor-clock";
105                 clock-div = <1>;
106                 clock-mult = <1>;
107                 clocks = <&xtal24mhz>;
108         };
109
110         /* FIXME: this actually hangs off the PLL clocks */
111         pclk: pclk@0 {
112                 #clock-cells = <0>;
113                 compatible = "fixed-clock";
114                 clock-frequency = <0>;
115         };
116
117         flash@30000000 {
118                 compatible = "arm,versatile-flash", "cfi-flash";
119                 reg = <0x30000000 0x4000000>;
120                 bank-width = <4>;
121         };
122
123         fpga_flash@38000000 {
124                 compatible = "arm,versatile-flash", "cfi-flash";
125                 reg = <0x38000000 0x800000>;
126                 bank-width = <4>;
127         };
128
129         /*
130          * The "secure flash" contains things like the boot
131          * monitor so we don't want people to accidentally
132          * screw this up. Mark the device tree node disabled
133          * by default.
134          */
135         secflash@3c000000 {
136                 compatible = "arm,versatile-flash", "cfi-flash";
137                 reg = <0x3c000000 0x4000000>;
138                 bank-width = <4>;
139                 status = "disabled";
140         };
141
142         /* SMSC 9118 ethernet with PHY and EEPROM */
143         ethernet@3a000000 {
144                 compatible = "smsc,lan9118", "smsc,lan9115";
145                 reg = <0x3a000000 0x10000>;
146                 interrupt-parent = <&intc_fpga1176>;
147                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
148                 phy-mode = "mii";
149                 reg-io-width = <4>;
150                 smsc,irq-active-high;
151                 smsc,irq-push-pull;
152                 vdd33a-supply = <&veth>;
153                 vddvario-supply = <&veth>;
154         };
155
156         usb@3b000000 {
157                 compatible = "nxp,usb-isp1761";
158                 reg = <0x3b000000 0x20000>;
159                 interrupt-parent = <&intc_fpga1176>;
160                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
161                 port1-otg;
162         };
163
164         bridge {
165                 compatible = "ti,ths8134a", "ti,ths8134";
166                 #address-cells = <1>;
167                 #size-cells = <0>;
168
169                 ports {
170                         #address-cells = <1>;
171                         #size-cells = <0>;
172
173                         port@0 {
174                                 reg = <0>;
175
176                                 vga_bridge_in: endpoint {
177                                         remote-endpoint = <&clcd_pads>;
178                                 };
179                         };
180
181                         port@1 {
182                                 reg = <1>;
183
184                                 vga_bridge_out: endpoint {
185                                         remote-endpoint = <&vga_con_in>;
186                                 };
187                         };
188                 };
189         };
190
191         vga {
192                 compatible = "vga-connector";
193
194                 port {
195                         vga_con_in: endpoint {
196                                 remote-endpoint = <&vga_bridge_out>;
197                         };
198                 };
199         };
200
201         soc {
202                 #address-cells = <1>;
203                 #size-cells = <1>;
204                 compatible = "arm,realview-pb1176-soc", "simple-bus";
205                 regmap = <&syscon>;
206                 ranges;
207
208                 syscon: syscon@10000000 {
209                         compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
210                         reg = <0x10000000 0x1000>;
211
212                         led@08.0 {
213                                 compatible = "register-bit-led";
214                                 offset = <0x08>;
215                                 mask = <0x01>;
216                                 label = "versatile:0";
217                                 linux,default-trigger = "heartbeat";
218                                 default-state = "on";
219                         };
220                         led@08.1 {
221                                 compatible = "register-bit-led";
222                                 offset = <0x08>;
223                                 mask = <0x02>;
224                                 label = "versatile:1";
225                                 linux,default-trigger = "mmc0";
226                                 default-state = "off";
227                         };
228                         led@08.2 {
229                                 compatible = "register-bit-led";
230                                 offset = <0x08>;
231                                 mask = <0x04>;
232                                 label = "versatile:2";
233                                 linux,default-trigger = "cpu0";
234                                 default-state = "off";
235                         };
236                         led@08.3 {
237                                 compatible = "register-bit-led";
238                                 offset = <0x08>;
239                                 mask = <0x08>;
240                                 label = "versatile:3";
241                                 default-state = "off";
242                         };
243                         led@08.4 {
244                                 compatible = "register-bit-led";
245                                 offset = <0x08>;
246                                 mask = <0x10>;
247                                 label = "versatile:4";
248                                 default-state = "off";
249                         };
250                         led@08.5 {
251                                 compatible = "register-bit-led";
252                                 offset = <0x08>;
253                                 mask = <0x20>;
254                                 label = "versatile:5";
255                                 default-state = "off";
256                         };
257                         led@08.6 {
258                                 compatible = "register-bit-led";
259                                 offset = <0x08>;
260                                 mask = <0x40>;
261                                 label = "versatile:6";
262                                 default-state = "off";
263                         };
264                         led@08.7 {
265                                 compatible = "register-bit-led";
266                                 offset = <0x08>;
267                                 mask = <0x80>;
268                                 label = "versatile:7";
269                                 default-state = "off";
270                         };
271                         oscclk0: osc0@0c {
272                                 compatible = "arm,syscon-icst307";
273                                 #clock-cells = <0>;
274                                 lock-offset = <0x20>;
275                                 vco-offset = <0x0C>;
276                                 clocks = <&xtal24mhz>;
277                         };
278                         oscclk1: osc1@10 {
279                                 compatible = "arm,syscon-icst307";
280                                 #clock-cells = <0>;
281                                 lock-offset = <0x20>;
282                                 vco-offset = <0x10>;
283                                 clocks = <&xtal24mhz>;
284                         };
285                         oscclk2: osc2@14 {
286                                 compatible = "arm,syscon-icst307";
287                                 #clock-cells = <0>;
288                                 lock-offset = <0x20>;
289                                 vco-offset = <0x14>;
290                                 clocks = <&xtal24mhz>;
291                         };
292                         oscclk3: osc3@18 {
293                                 compatible = "arm,syscon-icst307";
294                                 #clock-cells = <0>;
295                                 lock-offset = <0x20>;
296                                 vco-offset = <0x18>;
297                                 clocks = <&xtal24mhz>;
298                         };
299                         oscclk4: osc4@1c {
300                                 compatible = "arm,syscon-icst307";
301                                 #clock-cells = <0>;
302                                 lock-offset = <0x20>;
303                                 vco-offset = <0x1c>;
304                                 clocks = <&xtal24mhz>;
305                         };
306                 };
307
308                 /* Primary DevChip GIC synthesized with the CPU */
309                 intc_dc1176: interrupt-controller@10120000 {
310                         compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
311                         #interrupt-cells = <3>;
312                         #address-cells = <1>;
313                         interrupt-controller;
314                         reg = <0x10121000 0x1000>,
315                               <0x10120000 0x100>;
316                 };
317
318                 L2: l2-cache {
319                         compatible = "arm,l220-cache";
320                         reg = <0x10110000 0x1000>;
321                         interrupt-parent = <&intc_dc1176>;
322                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
323                         cache-unified;
324                         cache-level = <2>;
325                         /*
326                          * Override default cache size, sets and
327                          * associativity as these may be erroneously set
328                          * up by boot loader(s).
329                          */
330                         arm,override-auxreg;
331                         cache-size = <131072>; // 128kB
332                         cache-sets = <512>;
333                         cache-line-size = <32>;
334                 };
335
336                 pmu {
337                         compatible = "arm,arm1176-pmu";
338                         interrupt-parent = <&intc_dc1176>;
339                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
340                 };
341
342                 timer01: timer@10104000 {
343                         compatible = "arm,sp804", "arm,primecell";
344                         reg = <0x10104000 0x1000>;
345                         interrupt-parent = <&intc_dc1176>;
346                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
347                         clocks = <&timclk>, <&timclk>, <&pclk>;
348                         clock-names = "timer1", "timer2", "apb_pclk";
349                 };
350
351                 timer23: timer@10105000 {
352                         compatible = "arm,sp804", "arm,primecell";
353                         reg = <0x10105000 0x1000>;
354                         interrupt-parent = <&intc_dc1176>;
355                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
356                         arm,sp804-has-irq = <1>;
357                         clocks = <&timclk>, <&timclk>, <&pclk>;
358                         clock-names = "timer1", "timer2", "apb_pclk";
359                 };
360
361                 pb1176_rtc: rtc@10108000 {
362                         compatible = "arm,pl031", "arm,primecell";
363                         reg = <0x10108000 0x1000>;
364                         interrupt-parent = <&intc_dc1176>;
365                         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
366                         clocks = <&pclk>;
367                         clock-names = "apb_pclk";
368                 };
369
370                 pb1176_gpio0: gpio@1010a000 {
371                         compatible = "arm,pl061", "arm,primecell";
372                         reg = <0x1010a000 0x1000>;
373                         gpio-controller;
374                         interrupt-parent = <&intc_dc1176>;
375                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
376                         #gpio-cells = <2>;
377                         interrupt-controller;
378                         #interrupt-cells = <2>;
379                         clocks = <&pclk>;
380                         clock-names = "apb_pclk";
381                 };
382
383                 pb1176_ssp: spi@1010b000 {
384                         compatible = "arm,pl022", "arm,primecell";
385                         reg = <0x1010b000 0x1000>;
386                         interrupt-parent = <&intc_dc1176>;
387                         interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
388                         clocks = <&sspclk>, <&pclk>;
389                         clock-names = "SSPCLK", "apb_pclk";
390                 };
391
392                 pb1176_serial0: serial@1010c000 {
393                         compatible = "arm,pl011", "arm,primecell";
394                         reg = <0x1010c000 0x1000>;
395                         interrupt-parent = <&intc_dc1176>;
396                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
397                         clocks = <&uartclk>, <&pclk>;
398                         clock-names = "uartclk", "apb_pclk";
399                 };
400
401                 pb1176_serial1: serial@1010d000 {
402                         compatible = "arm,pl011", "arm,primecell";
403                         reg = <0x1010d000 0x1000>;
404                         interrupt-parent = <&intc_dc1176>;
405                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
406                         clocks = <&uartclk>, <&pclk>;
407                         clock-names = "uartclk", "apb_pclk";
408                 };
409
410                 pb1176_serial2: serial@1010e000 {
411                         compatible = "arm,pl011", "arm,primecell";
412                         reg = <0x1010e000 0x1000>;
413                         interrupt-parent = <&intc_dc1176>;
414                         interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
415                         clocks = <&uartclk>, <&pclk>;
416                         clock-names = "uartclk", "apb_pclk";
417                 };
418
419                 pb1176_serial3: serial@1010f000 {
420                         compatible = "arm,pl011", "arm,primecell";
421                         reg = <0x1010f000 0x1000>;
422                         interrupt-parent = <&intc_dc1176>;
423                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
424                         clocks = <&uartclk>, <&pclk>;
425                         clock-names = "uartclk", "apb_pclk";
426                 };
427
428                 /* Direct-mapped development chip ROM */
429                 pb1176_rom@10200000 {
430                         compatible = "direct-mapped";
431                         reg = <0x10200000 0x4000>;
432                         bank-width = <1>;
433                 };
434
435                 clcd@10112000 {
436                         compatible = "arm,pl111", "arm,primecell";
437                         reg = <0x10112000 0x1000>;
438                         interrupt-parent = <&intc_dc1176>;
439                         interrupt-names = "combined";
440                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
441                         clocks = <&oscclk0>, <&pclk>;
442                         clock-names = "clcdclk", "apb_pclk";
443                         /* 1024x768 16bpp @65MHz works fine */
444                         max-memory-bandwidth = <95000000>;
445
446                         port {
447                                 clcd_pads: endpoint {
448                                         remote-endpoint = <&vga_bridge_in>;
449                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
450                                 };
451                         };
452                 };
453         };
454
455         /* These peripherals are inside the FPGA rather than the DevChip */
456         fpga {
457                 #address-cells = <1>;
458                 #size-cells = <1>;
459                 compatible = "simple-bus";
460                 ranges;
461
462                 i2c0: i2c@10002000 {
463                         #address-cells = <1>;
464                         #size-cells = <0>;
465                         compatible = "arm,versatile-i2c";
466                         reg = <0x10002000 0x1000>;
467
468                         rtc@68 {
469                                 compatible = "dallas,ds1338";
470                                 reg = <0x68>;
471                         };
472                 };
473
474                 fpga_aaci: aaci@10004000 {
475                         compatible = "arm,pl041", "arm,primecell";
476                         reg = <0x10004000 0x1000>;
477                         interrupt-parent = <&intc_fpga1176>;
478                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
479                         clocks = <&pclk>;
480                         clock-names = "apb_pclk";
481                 };
482
483                 fpga_mci: mmcsd@10005000 {
484                         compatible = "arm,pl18x", "arm,primecell";
485                         reg = <0x10005000 0x1000>;
486                         interrupt-parent = <&intc_fpga1176>;
487                         interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
488                                         <0 2 IRQ_TYPE_LEVEL_HIGH>;
489                         /* Due to frequent FIFO overruns, use just 500 kHz */
490                         max-frequency = <500000>;
491                         bus-width = <4>;
492                         cap-sd-highspeed;
493                         cap-mmc-highspeed;
494                         clocks = <&mclk>, <&pclk>;
495                         clock-names = "mclk", "apb_pclk";
496                         vmmc-supply = <&vmmc>;
497                         cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
498                         wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
499                 };
500
501                 fpga_kmi0: kmi@10006000 {
502                         compatible = "arm,pl050", "arm,primecell";
503                         reg = <0x10006000 0x1000>;
504                         interrupt-parent = <&intc_fpga1176>;
505                         interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
506                         clocks = <&kmiclk>, <&pclk>;
507                         clock-names = "KMIREFCLK", "apb_pclk";
508                 };
509
510                 fpga_kmi1: kmi@10007000 {
511                         compatible = "arm,pl050", "arm,primecell";
512                         reg = <0x10007000 0x1000>;
513                         interrupt-parent = <&intc_fpga1176>;
514                         interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
515                         clocks = <&kmiclk>, <&pclk>;
516                         clock-names = "KMIREFCLK", "apb_pclk";
517                 };
518
519                 fpga_charlcd: charlcd@10008000 {
520                         compatible = "arm,versatile-lcd";
521                         reg = <0x10008000 0x1000>;
522                         interrupt-parent = <&intc_fpga1176>;
523                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
524                         clocks = <&pclk>;
525                         clock-names = "apb_pclk";
526                 };
527
528                 fpga_serial: serial@10009000 {
529                         compatible = "arm,pl011", "arm,primecell";
530                         reg = <0x10009000 0x1000>;
531                         interrupt-parent = <&intc_fpga1176>;
532                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
533                         clocks = <&uartclk>, <&pclk>;
534                         clock-names = "uartclk", "apb_pclk";
535                 };
536
537                 /* This GIC on the board is cascaded off the DevChip GIC */
538                 intc_fpga1176: interrupt-controller@10040000 {
539                         compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
540                         #interrupt-cells = <3>;
541                         #address-cells = <1>;
542                         interrupt-controller;
543                         reg = <0x10041000 0x1000>,
544                               <0x10040000 0x100>;
545                         interrupt-parent = <&intc_dc1176>;
546                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
547                 };
548
549                 fpga_gpio0: gpio@10014000 {
550                         compatible = "arm,pl061", "arm,primecell";
551                         reg = <0x10014000 0x1000>;
552                         gpio-controller;
553                         interrupt-parent = <&intc_fpga1176>;
554                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
555                         #gpio-cells = <2>;
556                         interrupt-controller;
557                         #interrupt-cells = <2>;
558                         clocks = <&pclk>;
559                         clock-names = "apb_pclk";
560                 };
561
562                 fpga_gpio1: gpio@10015000 {
563                         compatible = "arm,pl061", "arm,primecell";
564                         reg = <0x10015000 0x1000>;
565                         gpio-controller;
566                         interrupt-parent = <&intc_fpga1176>;
567                         interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
568                         #gpio-cells = <2>;
569                         interrupt-controller;
570                         #interrupt-cells = <2>;
571                         clocks = <&pclk>;
572                         clock-names = "apb_pclk";
573                 };
574
575                 fpga_rtc: rtc@10017000 {
576                         compatible = "arm,pl031", "arm,primecell";
577                         reg = <0x10017000 0x1000>;
578                         interrupt-parent = <&intc_fpga1176>;
579                         interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
580                         clocks = <&pclk>;
581                         clock-names = "apb_pclk";
582                 };
583         };
584 };