GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / at91-sama5d27_som1.dtsi
1 /*
2  * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board
3  *
4  *  Copyright (c) 2017, Microchip Technology Inc.
5  *                2017 Cristian Birsan <cristian.birsan@microchip.com>
6  *                2017 Claudiu Beznea <claudiu.beznea@microchip.com>
7  *
8  * This file is dual-licensed: you can use it either under the terms
9  * of the GPL or the X11 license, at your option. Note that this dual
10  * licensing only applies to this file, and not this project as a
11  * whole.
12  *
13  *  a) This file is free software; you can redistribute it and/or
14  *     modify it under the terms of the GNU General Public License as
15  *     published by the Free Software Foundation; either version 2 of the
16  *     License, or (at your option) any later version.
17  *
18  *     This file is distributed in the hope that it will be useful,
19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21  *     GNU General Public License for more details.
22  *
23  * Or, alternatively,
24  *
25  *  b) Permission is hereby granted, free of charge, to any person
26  *     obtaining a copy of this software and associated documentation
27  *     files (the "Software"), to deal in the Software without
28  *     restriction, including without limitation the rights to use,
29  *     copy, modify, merge, publish, distribute, sublicense, and/or
30  *     sell copies of the Software, and to permit persons to whom the
31  *     Software is furnished to do so, subject to the following
32  *     conditions:
33  *
34  *     The above copyright notice and this permission notice shall be
35  *     included in all copies or substantial portions of the Software.
36  *
37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44  *     OTHER DEALINGS IN THE SOFTWARE.
45  */
46 #include "sama5d2.dtsi"
47 #include "sama5d2-pinfunc.h"
48
49 / {
50         model = "Atmel SAMA5D27 SoM1";
51         compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
52
53         clocks {
54                 slow_xtal {
55                         clock-frequency = <32768>;
56                 };
57
58                 main_xtal {
59                         clock-frequency = <24000000>;
60                 };
61         };
62
63         ahb {
64                 apb {
65                         macb0: ethernet@f8008000 {
66                                 pinctrl-names = "default";
67                                 pinctrl-0 = <&pinctrl_macb0_default>;
68                                 phy-mode = "rmii";
69
70                                 ethernet-phy@7 {
71                                         reg = <0x7>;
72                                         interrupt-parent = <&pioA>;
73                                         interrupts = <PIN_PD31 IRQ_TYPE_LEVEL_LOW>;
74                                         pinctrl-names = "default";
75                                         pinctrl-0 = <&pinctrl_macb0_phy_irq>;
76                                 };
77                         };
78
79                         pinctrl@fc038000 {
80
81                                 pinctrl_macb0_default: macb0_default {
82                                         pinmux = <PIN_PD9__GTXCK>,
83                                                  <PIN_PD10__GTXEN>,
84                                                  <PIN_PD11__GRXDV>,
85                                                  <PIN_PD12__GRXER>,
86                                                  <PIN_PD13__GRX0>,
87                                                  <PIN_PD14__GRX1>,
88                                                  <PIN_PD15__GTX0>,
89                                                  <PIN_PD16__GTX1>,
90                                                  <PIN_PD17__GMDC>,
91                                                  <PIN_PD18__GMDIO>;
92                                         bias-disable;
93                                 };
94
95                                 pinctrl_macb0_phy_irq: macb0_phy_irq {
96                                         pinmux = <PIN_PD31__GPIO>;
97                                         bias-disable;
98                                 };
99                         };
100                 };
101         };
102 };