arch/arm/boot/dts/bcm2837.dtsi

   1 #include "bcm283x.dtsi"
   2
   3 / {
   4         compatible = "brcm,bcm2837";
   5
   6         soc {
   7                 ranges = <0x7e000000 0x3f000000 0x1000000>,
   8                          <0x40000000 0x40000000 0x00001000>;
   9                 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
  10
  11                 local_intc: local_intc@40000000 {
  12                         compatible = "brcm,bcm2836-l1-intc";
  13                         reg = <0x40000000 0x100>;
  14                         interrupt-controller;
  15                         #interrupt-cells = <2>;
  16                         interrupt-parent = <&local_intc>;
  17                 };
  18         };
  19
  20         arm-pmu {
  21                 compatible = "arm,cortex-a53-pmu";
  22                 interrupt-parent = <&local_intc>;
  23                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
  24         };
  25
  26         timer {
  27                 compatible = "arm,armv7-timer";
  28                 interrupt-parent = <&local_intc>;
  29                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
  30                              <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
  31                              <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
  32                              <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
  33                 always-on;
  34         };
  35
  36         cpus: cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39                 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
  40
  41                 /* Source for d/i-cache-line-size and d/i-cache-sets
  42                  * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
  43                  * /about-the-l1-memory-system?lang=en
  44                  *
  45                  * Source for d/i-cache-size
  46                  * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
  47                  */
  48                 cpu0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53";
  51                         reg = <0>;
  52                         enable-method = "spin-table";
  53                         cpu-release-addr = <0x0 0x000000d8>;
  54                         d-cache-size = <0x8000>;
  55                         d-cache-line-size = <64>;
  56                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
  57                         i-cache-size = <0x8000>;
  58                         i-cache-line-size = <64>;
  59                         i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
  60                         next-level-cache = <&l2>;
  61                 };
  62
  63                 cpu1: cpu@1 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a53";
  66                         reg = <1>;
  67                         enable-method = "spin-table";
  68                         cpu-release-addr = <0x0 0x000000e0>;
  69                         d-cache-size = <0x8000>;
  70                         d-cache-line-size = <64>;
  71                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
  72                         i-cache-size = <0x8000>;
  73                         i-cache-line-size = <64>;
  74                         i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
  75                         next-level-cache = <&l2>;
  76                 };
  77
  78                 cpu2: cpu@2 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53";
  81                         reg = <2>;
  82                         enable-method = "spin-table";
  83                         cpu-release-addr = <0x0 0x000000e8>;
  84                         d-cache-size = <0x8000>;
  85                         d-cache-line-size = <64>;
  86                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
  87                         i-cache-size = <0x8000>;
  88                         i-cache-line-size = <64>;
  89                         i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
  90                         next-level-cache = <&l2>;
  91                 };
  92
  93                 cpu3: cpu@3 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53";
  96                         reg = <3>;
  97                         enable-method = "spin-table";
  98                         cpu-release-addr = <0x0 0x000000f0>;
  99                         d-cache-size = <0x8000>;
 100                         d-cache-line-size = <64>;
 101                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
 102                         i-cache-size = <0x8000>;
 103                         i-cache-line-size = <64>;
 104                         i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
 105                         next-level-cache = <&l2>;
 106                 };
 107
 108                 /* Source for cache-line-size + cache-sets
 109                  * https://developer.arm.com/documentation/ddi0500
 110                  * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
 111                  * Source for cache-size
 112                  * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
 113                  */
 114                 l2: l2-cache0 {
 115                         compatible = "cache";
 116                         cache-size = <0x80000>;
 117                         cache-line-size = <64>;
 118                         cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
 119                         cache-level = <2>;
 120                 };
 121         };
 122 };
 123
 124 /* Make the BCM2835-style global interrupt controller be a child of the
 125  * CPU-local interrupt controller.
 126  */
 127 &intc {
 128         compatible = "brcm,bcm2836-armctrl-ic";
 129         reg = <0x7e00b200 0x200>;
 130         interrupt-parent = <&local_intc>;
 131         interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 132 };
 133
 134 &cpu_thermal {
 135         coefficients = <(-538)  412000>;
 136 };
 137
 138 /* enable thermal sensor with the correct compatible property set */
 139 &thermal {
 140         compatible = "brcm,bcm2837-thermal";
 141         status = "okay";
 142 };