arch/arm/boot/dts/bcm63138.dtsi

   1 /*
   2  * Broadcom BCM63138 DSL SoCs Device Tree
   3  */
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7
   8 #include "skeleton.dtsi"
   9
  10 / {
  11         compatible = "brcm,bcm63138";
  12         model = "Broadcom BCM63138 DSL SoC";
  13         interrupt-parent = <&gic>;
  14
  15         aliases {
  16                 uart0 = &serial0;
  17                 uart1 = &serial1;
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a9";
  27                         next-level-cache = <&L2>;
  28                         reg = <0>;
  29                         enable-method = "brcm,bcm63138";
  30                 };
  31
  32                 cpu@1 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a9";
  35                         next-level-cache = <&L2>;
  36                         reg = <1>;
  37                         enable-method = "brcm,bcm63138";
  38                         resets = <&pmb0 4 1>;
  39                 };
  40         };
  41
  42         clocks {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 /* UBUS peripheral clock */
  47                 periph_clk: periph_clk {
  48                         #clock-cells = <0>;
  49                         compatible = "fixed-clock";
  50                         clock-frequency = <50000000>;
  51                         clock-output-names = "periph";
  52                 };
  53
  54                 /* peripheral clock for system timer */
  55                 axi_clk: axi_clk {
  56                         #clock-cells = <0>;
  57                         compatible = "fixed-factor-clock";
  58                         clocks = <&armpll>;
  59                         clock-div = <2>;
  60                         clock-mult = <1>;
  61                 };
  62
  63                 /* APB bus clock */
  64                 apb_clk: apb_clk {
  65                         #clock-cells = <0>;
  66                         compatible = "fixed-factor-clock";
  67                         clocks = <&armpll>;
  68                         clock-div = <4>;
  69                         clock-mult = <1>;
  70                 };
  71         };
  72
  73         /* ARM bus */
  74         axi@80000000 {
  75                 compatible = "simple-bus";
  76                 ranges = <0 0x80000000 0x784000>;
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79
  80                 L2: cache-controller@1d000 {
  81                         compatible = "arm,pl310-cache";
  82                         reg = <0x1d000 0x1000>;
  83                         cache-unified;
  84                         cache-level = <2>;
  85                         cache-size = <524288>;
  86                         cache-sets = <1024>;
  87                         cache-line-size = <32>;
  88                         interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
  89                 };
  90
  91                 scu: scu@1e000 {
  92                         compatible = "arm,cortex-a9-scu";
  93                         reg = <0x1e000 0x100>;
  94                 };
  95
  96                 gic: interrupt-controller@1e100 {
  97                         compatible = "arm,cortex-a9-gic";
  98                         reg = <0x1f000 0x1000
  99                                 0x1e100 0x100>;
 100                         #interrupt-cells = <3>;
 101                         #address-cells = <0>;
 102                         interrupt-controller;
 103                 };
 104
 105                 global_timer: timer@1e200 {
 106                         compatible = "arm,cortex-a9-global-timer";
 107                         reg = <0x1e200 0x20>;
 108                         interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
 109                         clocks = <&axi_clk>;
 110                 };
 111
 112                 local_timer: local-timer@1e600 {
 113                         compatible = "arm,cortex-a9-twd-timer";
 114                         reg = <0x1e600 0x20>;
 115                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 116                                                   IRQ_TYPE_EDGE_RISING)>;
 117                         clocks = <&axi_clk>;
 118                 };
 119
 120                 twd_watchdog: watchdog@1e620 {
 121                         compatible = "arm,cortex-a9-twd-wdt";
 122                         reg = <0x1e620 0x20>;
 123                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 124                                                   IRQ_TYPE_LEVEL_HIGH)>;
 125                 };
 126
 127                 armpll: armpll {
 128                         #clock-cells = <0>;
 129                         compatible = "brcm,bcm63138-armpll";
 130                         clocks = <&periph_clk>;
 131                         reg = <0x20000 0xf00>;
 132                 };
 133
 134                 pmb0: reset-controller@4800c0 {
 135                         compatible = "brcm,bcm63138-pmb";
 136                         reg = <0x4800c0 0x10>;
 137                         #reset-cells = <2>;
 138                 };
 139
 140                 pmb1: reset-controller@4800e0 {
 141                         compatible = "brcm,bcm63138-pmb";
 142                         reg = <0x4800e0 0x10>;
 143                         #reset-cells = <2>;
 144                 };
 145         };
 146
 147         /* Legacy UBUS base */
 148         ubus@fffe8000 {
 149                 compatible = "simple-bus";
 150                 #address-cells = <1>;
 151                 #size-cells = <1>;
 152                 ranges = <0 0xfffe8000 0x8100>;
 153
 154                 timer: timer@80 {
 155                         compatible = "brcm,bcm6328-timer", "syscon";
 156                         reg = <0x80 0x3c>;
 157                 };
 158
 159                 serial0: serial@600 {
 160                         compatible = "brcm,bcm6345-uart";
 161                         reg = <0x600 0x1b>;
 162                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 163                         clocks = <&periph_clk>;
 164                         clock-names = "periph";
 165                         status = "disabled";
 166                 };
 167
 168                 serial1: serial@620 {
 169                         compatible = "brcm,bcm6345-uart";
 170                         reg = <0x620 0x1b>;
 171                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 172                         clocks = <&periph_clk>;
 173                         clock-names = "periph";
 174                         status = "disabled";
 175                 };
 176
 177                 nand_controller: nand-controller@2000 {
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                         compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
 181                         reg = <0x2000 0x600>, <0xf0 0x10>;
 182                         reg-names = "nand", "nand-int-base";
 183                         status = "disabled";
 184                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 185                         interrupt-names = "nand";
 186                 };
 187
 188                 bootlut: bootlut@8000 {
 189                         compatible = "brcm,bcm63138-bootlut";
 190                         reg = <0x8000 0x50>;
 191                 };
 192
 193                 reboot {
 194                         compatible = "syscon-reboot";
 195                         regmap = <&timer>;
 196                         offset = <0x34>;
 197                         mask = <1>;
 198                 };
 199         };
 200 };