arch/arm/boot/dts/exynos3250.dtsi

   1 /*
   2  * Samsung's Exynos3250 SoC device tree source
   3  *
   4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include "exynos4-cpu-thermal.dtsi"
  21 #include "exynos-syscon-restart.dtsi"
  22 #include <dt-bindings/clock/exynos3250.h>
  23
  24 / {
  25         compatible = "samsung,exynos3250";
  26         interrupt-parent = <&gic>;
  27         #address-cells = <1>;
  28         #size-cells = <1>;
  29
  30         aliases {
  31                 pinctrl0 = &pinctrl_0;
  32                 pinctrl1 = &pinctrl_1;
  33                 mshc0 = &mshc_0;
  34                 mshc1 = &mshc_1;
  35                 mshc2 = &mshc_2;
  36                 spi0 = &spi_0;
  37                 spi1 = &spi_1;
  38                 i2c0 = &i2c_0;
  39                 i2c1 = &i2c_1;
  40                 i2c2 = &i2c_2;
  41                 i2c3 = &i2c_3;
  42                 i2c4 = &i2c_4;
  43                 i2c5 = &i2c_5;
  44                 i2c6 = &i2c_6;
  45                 i2c7 = &i2c_7;
  46                 serial0 = &serial_0;
  47                 serial1 = &serial_1;
  48                 serial2 = &serial_2;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu0: cpu@0 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a7";
  58                         reg = <0>;
  59                         clock-frequency = <1000000000>;
  60                         clocks = <&cmu CLK_ARM_CLK>;
  61                         clock-names = "cpu";
  62                         #cooling-cells = <2>;
  63
  64                         operating-points = <
  65                                 1000000 1150000
  66                                 900000  1112500
  67                                 800000  1075000
  68                                 700000  1037500
  69                                 600000  1000000
  70                                 500000  962500
  71                                 400000  925000
  72                                 300000  887500
  73                                 200000  850000
  74                                 100000  850000
  75                         >;
  76                 };
  77
  78                 cpu1: cpu@1 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a7";
  81                         reg = <1>;
  82                         clock-frequency = <1000000000>;
  83                         clocks = <&cmu CLK_ARM_CLK>;
  84                         clock-names = "cpu";
  85                         #cooling-cells = <2>;
  86
  87                         operating-points = <
  88                                 1000000 1150000
  89                                 900000  1112500
  90                                 800000  1075000
  91                                 700000  1037500
  92                                 600000  1000000
  93                                 500000  962500
  94                                 400000  925000
  95                                 300000  887500
  96                                 200000  850000
  97                                 100000  850000
  98                         >;
  99                 };
 100         };
 101
 102         soc: soc {
 103                 compatible = "simple-bus";
 104                 #address-cells = <1>;
 105                 #size-cells = <1>;
 106                 ranges;
 107
 108                 fixed-rate-clocks {
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111
 112                         xusbxti: clock@0 {
 113                                 compatible = "fixed-clock";
 114                                 #address-cells = <1>;
 115                                 #size-cells = <0>;
 116                                 reg = <0>;
 117                                 clock-frequency = <0>;
 118                                 #clock-cells = <0>;
 119                                 clock-output-names = "xusbxti";
 120                         };
 121
 122                         xxti: clock@1 {
 123                                 compatible = "fixed-clock";
 124                                 reg = <1>;
 125                                 clock-frequency = <0>;
 126                                 #clock-cells = <0>;
 127                                 clock-output-names = "xxti";
 128                         };
 129
 130                         xtcxo: clock@2 {
 131                                 compatible = "fixed-clock";
 132                                 reg = <2>;
 133                                 clock-frequency = <0>;
 134                                 #clock-cells = <0>;
 135                                 clock-output-names = "xtcxo";
 136                         };
 137                 };
 138
 139                 sysram@02020000 {
 140                         compatible = "mmio-sram";
 141                         reg = <0x02020000 0x40000>;
 142                         #address-cells = <1>;
 143                         #size-cells = <1>;
 144                         ranges = <0 0x02020000 0x40000>;
 145
 146                         smp-sysram@0 {
 147                                 compatible = "samsung,exynos4210-sysram";
 148                                 reg = <0x0 0x1000>;
 149                         };
 150
 151                         smp-sysram@3f000 {
 152                                 compatible = "samsung,exynos4210-sysram-ns";
 153                                 reg = <0x3f000 0x1000>;
 154                         };
 155                 };
 156
 157                 chipid@10000000 {
 158                         compatible = "samsung,exynos4210-chipid";
 159                         reg = <0x10000000 0x100>;
 160                 };
 161
 162                 sys_reg: syscon@10010000 {
 163                         compatible = "samsung,exynos3-sysreg", "syscon";
 164                         reg = <0x10010000 0x400>;
 165                 };
 166
 167                 pmu_system_controller: system-controller@10020000 {
 168                         compatible = "samsung,exynos3250-pmu", "syscon";
 169                         reg = <0x10020000 0x4000>;
 170                         interrupt-controller;
 171                         #interrupt-cells = <3>;
 172                         interrupt-parent = <&gic>;
 173                         clock-names = "clkout8";
 174                         clocks = <&cmu CLK_FIN_PLL>;
 175                         #clock-cells = <1>;
 176                 };
 177
 178                 mipi_phy: video-phy {
 179                         compatible = "samsung,s5pv210-mipi-video-phy";
 180                         #phy-cells = <1>;
 181                         syscon = <&pmu_system_controller>;
 182                 };
 183
 184                 pd_cam: cam-power-domain@10023C00 {
 185                         compatible = "samsung,exynos4210-pd";
 186                         reg = <0x10023C00 0x20>;
 187                         #power-domain-cells = <0>;
 188                 };
 189
 190                 pd_mfc: mfc-power-domain@10023C40 {
 191                         compatible = "samsung,exynos4210-pd";
 192                         reg = <0x10023C40 0x20>;
 193                         #power-domain-cells = <0>;
 194                 };
 195
 196                 pd_g3d: g3d-power-domain@10023C60 {
 197                         compatible = "samsung,exynos4210-pd";
 198                         reg = <0x10023C60 0x20>;
 199                         #power-domain-cells = <0>;
 200                 };
 201
 202                 pd_lcd0: lcd0-power-domain@10023C80 {
 203                         compatible = "samsung,exynos4210-pd";
 204                         reg = <0x10023C80 0x20>;
 205                         #power-domain-cells = <0>;
 206                 };
 207
 208                 pd_isp: isp-power-domain@10023CA0 {
 209                         compatible = "samsung,exynos4210-pd";
 210                         reg = <0x10023CA0 0x20>;
 211                         #power-domain-cells = <0>;
 212                 };
 213
 214                 cmu: clock-controller@10030000 {
 215                         compatible = "samsung,exynos3250-cmu";
 216                         reg = <0x10030000 0x20000>;
 217                         #clock-cells = <1>;
 218                         assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
 219                                           <&cmu CLK_MOUT_ACLK_266_SUB>;
 220                         assigned-clock-parents = <&cmu CLK_FIN_PLL>,
 221                                                  <&cmu CLK_FIN_PLL>;
 222                 };
 223
 224                 cmu_dmc: clock-controller@105C0000 {
 225                         compatible = "samsung,exynos3250-cmu-dmc";
 226                         reg = <0x105C0000 0x2000>;
 227                         #clock-cells = <1>;
 228                 };
 229
 230                 rtc: rtc@10070000 {
 231                         compatible = "samsung,s3c6410-rtc";
 232                         reg = <0x10070000 0x100>;
 233                         interrupts = <0 73 0>, <0 74 0>;
 234                         interrupt-parent = <&pmu_system_controller>;
 235                         status = "disabled";
 236                 };
 237
 238                 tmu: tmu@100C0000 {
 239                         compatible = "samsung,exynos3250-tmu";
 240                         reg = <0x100C0000 0x100>;
 241                         interrupts = <0 216 0>;
 242                         clocks = <&cmu CLK_TMU_APBIF>;
 243                         clock-names = "tmu_apbif";
 244                         #include "exynos4412-tmu-sensor-conf.dtsi"
 245                         status = "disabled";
 246                 };
 247
 248                 gic: interrupt-controller@10481000 {
 249                         compatible = "arm,cortex-a15-gic";
 250                         #interrupt-cells = <3>;
 251                         interrupt-controller;
 252                         reg = <0x10481000 0x1000>,
 253                               <0x10482000 0x1000>,
 254                               <0x10484000 0x2000>,
 255                               <0x10486000 0x2000>;
 256                         interrupts = <1 9 0xf04>;
 257                 };
 258
 259                 mct@10050000 {
 260                         compatible = "samsung,exynos4210-mct";
 261                         reg = <0x10050000 0x800>;
 262                         interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
 263                                      <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
 264                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 265                         clock-names = "fin_pll", "mct";
 266                 };
 267
 268                 pinctrl_1: pinctrl@11000000 {
 269                         compatible = "samsung,exynos3250-pinctrl";
 270                         reg = <0x11000000 0x1000>;
 271                         interrupts = <0 225 0>;
 272
 273                         wakeup-interrupt-controller {
 274                                 compatible = "samsung,exynos4210-wakeup-eint";
 275                                 interrupts = <0 48 0>;
 276                         };
 277                 };
 278
 279                 pinctrl_0: pinctrl@11400000 {
 280                         compatible = "samsung,exynos3250-pinctrl";
 281                         reg = <0x11400000 0x1000>;
 282                         interrupts = <0 240 0>;
 283                 };
 284
 285                 jpeg: codec@11830000 {
 286                         compatible = "samsung,exynos3250-jpeg";
 287                         reg = <0x11830000 0x1000>;
 288                         interrupts = <0 171 0>;
 289                         clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
 290                         clock-names = "jpeg", "sclk";
 291                         power-domains = <&pd_cam>;
 292                         assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
 293                         assigned-clock-rates = <0>, <150000000>;
 294                         assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
 295                         iommus = <&sysmmu_jpeg>;
 296                         status = "disabled";
 297                 };
 298
 299                 sysmmu_jpeg: sysmmu@11A60000 {
 300                         compatible = "samsung,exynos-sysmmu";
 301                         reg = <0x11a60000 0x1000>;
 302                         interrupts = <0 156 0>, <0 161 0>;
 303                         clock-names = "sysmmu", "master";
 304                         clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
 305                         power-domains = <&pd_cam>;
 306                         #iommu-cells = <0>;
 307                 };
 308
 309                 fimd: fimd@11c00000 {
 310                         compatible = "samsung,exynos3250-fimd";
 311                         reg = <0x11c00000 0x30000>;
 312                         interrupt-names = "fifo", "vsync", "lcd_sys";
 313                         interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
 314                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
 315                         clock-names = "sclk_fimd", "fimd";
 316                         power-domains = <&pd_lcd0>;
 317                         iommus = <&sysmmu_fimd0>;
 318                         samsung,sysreg = <&sys_reg>;
 319                         status = "disabled";
 320                 };
 321
 322                 dsi_0: dsi@11C80000 {
 323                         compatible = "samsung,exynos3250-mipi-dsi";
 324                         reg = <0x11C80000 0x10000>;
 325                         interrupts = <0 83 0>;
 326                         samsung,phy-type = <0>;
 327                         power-domains = <&pd_lcd0>;
 328                         phys = <&mipi_phy 1>;
 329                         phy-names = "dsim";
 330                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
 331                         clock-names = "bus_clk", "pll_clk";
 332                         #address-cells = <1>;
 333                         #size-cells = <0>;
 334                         status = "disabled";
 335                 };
 336
 337                 sysmmu_fimd0: sysmmu@11E20000 {
 338                         compatible = "samsung,exynos-sysmmu";
 339                         reg = <0x11e20000 0x1000>;
 340                         interrupts = <0 80 0>, <0 81 0>;
 341                         clock-names = "sysmmu", "master";
 342                         clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
 343                         power-domains = <&pd_lcd0>;
 344                         #iommu-cells = <0>;
 345                 };
 346
 347                 hsotg: hsotg@12480000 {
 348                         compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
 349                         reg = <0x12480000 0x20000>;
 350                         interrupts = <0 141 0>;
 351                         clocks = <&cmu CLK_USBOTG>;
 352                         clock-names = "otg";
 353                         phys = <&exynos_usbphy 0>;
 354                         phy-names = "usb2-phy";
 355                         status = "disabled";
 356                 };
 357
 358                 mshc_0: mshc@12510000 {
 359                         compatible = "samsung,exynos5420-dw-mshc";
 360                         reg = <0x12510000 0x1000>;
 361                         interrupts = <0 142 0>;
 362                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 363                         clock-names = "biu", "ciu";
 364                         fifo-depth = <0x80>;
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                         status = "disabled";
 368                 };
 369
 370                 mshc_1: mshc@12520000 {
 371                         compatible = "samsung,exynos5420-dw-mshc";
 372                         reg = <0x12520000 0x1000>;
 373                         interrupts = <0 143 0>;
 374                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 375                         clock-names = "biu", "ciu";
 376                         fifo-depth = <0x80>;
 377                         #address-cells = <1>;
 378                         #size-cells = <0>;
 379                         status = "disabled";
 380                 };
 381
 382                 mshc_2: mshc@12530000 {
 383                         compatible = "samsung,exynos5250-dw-mshc";
 384                         reg = <0x12530000 0x1000>;
 385                         interrupts = <0 144 0>;
 386                         clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
 387                         clock-names = "biu", "ciu";
 388                         fifo-depth = <0x80>;
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         status = "disabled";
 392                 };
 393
 394                 exynos_usbphy: exynos-usbphy@125B0000 {
 395                         compatible = "samsung,exynos3250-usb2-phy";
 396                         reg = <0x125B0000 0x100>;
 397                         samsung,pmureg-phandle = <&pmu_system_controller>;
 398                         clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
 399                         clock-names = "phy", "ref";
 400                         #phy-cells = <1>;
 401                         status = "disabled";
 402                 };
 403
 404                 amba {
 405                         compatible = "simple-bus";
 406                         #address-cells = <1>;
 407                         #size-cells = <1>;
 408                         ranges;
 409
 410                         pdma0: pdma@12680000 {
 411                                 compatible = "arm,pl330", "arm,primecell";
 412                                 reg = <0x12680000 0x1000>;
 413                                 interrupts = <0 138 0>;
 414                                 clocks = <&cmu CLK_PDMA0>;
 415                                 clock-names = "apb_pclk";
 416                                 #dma-cells = <1>;
 417                                 #dma-channels = <8>;
 418                                 #dma-requests = <32>;
 419                         };
 420
 421                         pdma1: pdma@12690000 {
 422                                 compatible = "arm,pl330", "arm,primecell";
 423                                 reg = <0x12690000 0x1000>;
 424                                 interrupts = <0 139 0>;
 425                                 clocks = <&cmu CLK_PDMA1>;
 426                                 clock-names = "apb_pclk";
 427                                 #dma-cells = <1>;
 428                                 #dma-channels = <8>;
 429                                 #dma-requests = <32>;
 430                         };
 431                 };
 432
 433                 adc: adc@126C0000 {
 434                         compatible = "samsung,exynos3250-adc",
 435                                      "samsung,exynos-adc-v2";
 436                         reg = <0x126C0000 0x100>;
 437                         interrupts = <0 137 0>;
 438                         clock-names = "adc", "sclk";
 439                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 440                         #io-channel-cells = <1>;
 441                         io-channel-ranges;
 442                         samsung,syscon-phandle = <&pmu_system_controller>;
 443                         status = "disabled";
 444                 };
 445
 446                 mfc: codec@13400000 {
 447                         compatible = "samsung,mfc-v7";
 448                         reg = <0x13400000 0x10000>;
 449                         interrupts = <0 102 0>;
 450                         clock-names = "mfc", "sclk_mfc";
 451                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
 452                         power-domains = <&pd_mfc>;
 453                         iommus = <&sysmmu_mfc>;
 454                 };
 455
 456                 sysmmu_mfc: sysmmu@13620000 {
 457                         compatible = "samsung,exynos-sysmmu";
 458                         reg = <0x13620000 0x1000>;
 459                         interrupts = <0 96 0>, <0 98 0>;
 460                         clock-names = "sysmmu", "master";
 461                         clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
 462                         power-domains = <&pd_mfc>;
 463                         #iommu-cells = <0>;
 464                 };
 465
 466                 serial_0: serial@13800000 {
 467                         compatible = "samsung,exynos4210-uart";
 468                         reg = <0x13800000 0x100>;
 469                         interrupts = <0 109 0>;
 470                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 471                         clock-names = "uart", "clk_uart_baud0";
 472                         pinctrl-names = "default";
 473                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 474                         status = "disabled";
 475                 };
 476
 477                 serial_1: serial@13810000 {
 478                         compatible = "samsung,exynos4210-uart";
 479                         reg = <0x13810000 0x100>;
 480                         interrupts = <0 110 0>;
 481                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 482                         clock-names = "uart", "clk_uart_baud0";
 483                         pinctrl-names = "default";
 484                         pinctrl-0 = <&uart1_data>;
 485                         status = "disabled";
 486                 };
 487
 488                 serial_2: serial@13820000 {
 489                         compatible = "samsung,exynos4210-uart";
 490                         reg = <0x13820000 0x100>;
 491                         interrupts = <0 111 0>;
 492                         clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
 493                         clock-names = "uart", "clk_uart_baud0";
 494                         pinctrl-names = "default";
 495                         pinctrl-0 = <&uart2_data>;
 496                         status = "disabled";
 497                 };
 498
 499                 i2c_0: i2c@13860000 {
 500                         #address-cells = <1>;
 501                         #size-cells = <0>;
 502                         compatible = "samsung,s3c2440-i2c";
 503                         reg = <0x13860000 0x100>;
 504                         interrupts = <0 113 0>;
 505                         clocks = <&cmu CLK_I2C0>;
 506                         clock-names = "i2c";
 507                         pinctrl-names = "default";
 508                         pinctrl-0 = <&i2c0_bus>;
 509                         status = "disabled";
 510                 };
 511
 512                 i2c_1: i2c@13870000 {
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         compatible = "samsung,s3c2440-i2c";
 516                         reg = <0x13870000 0x100>;
 517                         interrupts = <0 114 0>;
 518                         clocks = <&cmu CLK_I2C1>;
 519                         clock-names = "i2c";
 520                         pinctrl-names = "default";
 521                         pinctrl-0 = <&i2c1_bus>;
 522                         status = "disabled";
 523                 };
 524
 525                 i2c_2: i2c@13880000 {
 526                         #address-cells = <1>;
 527                         #size-cells = <0>;
 528                         compatible = "samsung,s3c2440-i2c";
 529                         reg = <0x13880000 0x100>;
 530                         interrupts = <0 115 0>;
 531                         clocks = <&cmu CLK_I2C2>;
 532                         clock-names = "i2c";
 533                         pinctrl-names = "default";
 534                         pinctrl-0 = <&i2c2_bus>;
 535                         status = "disabled";
 536                 };
 537
 538                 i2c_3: i2c@13890000 {
 539                         #address-cells = <1>;
 540                         #size-cells = <0>;
 541                         compatible = "samsung,s3c2440-i2c";
 542                         reg = <0x13890000 0x100>;
 543                         interrupts = <0 116 0>;
 544                         clocks = <&cmu CLK_I2C3>;
 545                         clock-names = "i2c";
 546                         pinctrl-names = "default";
 547                         pinctrl-0 = <&i2c3_bus>;
 548                         status = "disabled";
 549                 };
 550
 551                 i2c_4: i2c@138A0000 {
 552                         #address-cells = <1>;
 553                         #size-cells = <0>;
 554                         compatible = "samsung,s3c2440-i2c";
 555                         reg = <0x138A0000 0x100>;
 556                         interrupts = <0 117 0>;
 557                         clocks = <&cmu CLK_I2C4>;
 558                         clock-names = "i2c";
 559                         pinctrl-names = "default";
 560                         pinctrl-0 = <&i2c4_bus>;
 561                         status = "disabled";
 562                 };
 563
 564                 i2c_5: i2c@138B0000 {
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567                         compatible = "samsung,s3c2440-i2c";
 568                         reg = <0x138B0000 0x100>;
 569                         interrupts = <0 118 0>;
 570                         clocks = <&cmu CLK_I2C5>;
 571                         clock-names = "i2c";
 572                         pinctrl-names = "default";
 573                         pinctrl-0 = <&i2c5_bus>;
 574                         status = "disabled";
 575                 };
 576
 577                 i2c_6: i2c@138C0000 {
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                         compatible = "samsung,s3c2440-i2c";
 581                         reg = <0x138C0000 0x100>;
 582                         interrupts = <0 119 0>;
 583                         clocks = <&cmu CLK_I2C6>;
 584                         clock-names = "i2c";
 585                         pinctrl-names = "default";
 586                         pinctrl-0 = <&i2c6_bus>;
 587                         status = "disabled";
 588                 };
 589
 590                 i2c_7: i2c@138D0000 {
 591                         #address-cells = <1>;
 592                         #size-cells = <0>;
 593                         compatible = "samsung,s3c2440-i2c";
 594                         reg = <0x138D0000 0x100>;
 595                         interrupts = <0 120 0>;
 596                         clocks = <&cmu CLK_I2C7>;
 597                         clock-names = "i2c";
 598                         pinctrl-names = "default";
 599                         pinctrl-0 = <&i2c7_bus>;
 600                         status = "disabled";
 601                 };
 602
 603                 spi_0: spi@13920000 {
 604                         compatible = "samsung,exynos4210-spi";
 605                         reg = <0x13920000 0x100>;
 606                         interrupts = <0 121 0>;
 607                         dmas = <&pdma0 7>, <&pdma0 6>;
 608                         dma-names = "tx", "rx";
 609                         #address-cells = <1>;
 610                         #size-cells = <0>;
 611                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 612                         clock-names = "spi", "spi_busclk0";
 613                         samsung,spi-src-clk = <0>;
 614                         pinctrl-names = "default";
 615                         pinctrl-0 = <&spi0_bus>;
 616                         status = "disabled";
 617                 };
 618
 619                 spi_1: spi@13930000 {
 620                         compatible = "samsung,exynos4210-spi";
 621                         reg = <0x13930000 0x100>;
 622                         interrupts = <0 122 0>;
 623                         dmas = <&pdma1 7>, <&pdma1 6>;
 624                         dma-names = "tx", "rx";
 625                         #address-cells = <1>;
 626                         #size-cells = <0>;
 627                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 628                         clock-names = "spi", "spi_busclk0";
 629                         samsung,spi-src-clk = <0>;
 630                         pinctrl-names = "default";
 631                         pinctrl-0 = <&spi1_bus>;
 632                         status = "disabled";
 633                 };
 634
 635                 i2s2: i2s@13970000 {
 636                         compatible = "samsung,s3c6410-i2s";
 637                         reg = <0x13970000 0x100>;
 638                         interrupts = <0 126 0>;
 639                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 640                         clock-names = "iis", "i2s_opclk0";
 641                         dmas = <&pdma0 14>, <&pdma0 13>;
 642                         dma-names = "tx", "rx";
 643                         pinctrl-0 = <&i2s2_bus>;
 644                         pinctrl-names = "default";
 645                         status = "disabled";
 646                 };
 647
 648                 pwm: pwm@139D0000 {
 649                         compatible = "samsung,exynos4210-pwm";
 650                         reg = <0x139D0000 0x1000>;
 651                         interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
 652                                      <0 107 0>, <0 108 0>;
 653                         #pwm-cells = <3>;
 654                         status = "disabled";
 655                 };
 656
 657                 pmu {
 658                         compatible = "arm,cortex-a7-pmu";
 659                         interrupts = <0 18 0>, <0 19 0>;
 660                 };
 661
 662                 ppmu_dmc0: ppmu_dmc0@106a0000 {
 663                         compatible = "samsung,exynos-ppmu";
 664                         reg = <0x106a0000 0x2000>;
 665                         status = "disabled";
 666                 };
 667
 668                 ppmu_dmc1: ppmu_dmc1@106b0000 {
 669                         compatible = "samsung,exynos-ppmu";
 670                         reg = <0x106b0000 0x2000>;
 671                         status = "disabled";
 672                 };
 673
 674                 ppmu_cpu: ppmu_cpu@106c0000 {
 675                         compatible = "samsung,exynos-ppmu";
 676                         reg = <0x106c0000 0x2000>;
 677                         status = "disabled";
 678                 };
 679
 680                 ppmu_rightbus: ppmu_rightbus@112a0000 {
 681                         compatible = "samsung,exynos-ppmu";
 682                         reg = <0x112a0000 0x2000>;
 683                         clocks = <&cmu CLK_PPMURIGHT>;
 684                         clock-names = "ppmu";
 685                         status = "disabled";
 686                 };
 687
 688                 ppmu_leftbus: ppmu_leftbus0@116a0000 {
 689                         compatible = "samsung,exynos-ppmu";
 690                         reg = <0x116a0000 0x2000>;
 691                         clocks = <&cmu CLK_PPMULEFT>;
 692                         clock-names = "ppmu";
 693                         status = "disabled";
 694                 };
 695
 696                 ppmu_camif: ppmu_camif@11ac0000 {
 697                         compatible = "samsung,exynos-ppmu";
 698                         reg = <0x11ac0000 0x2000>;
 699                         clocks = <&cmu CLK_PPMUCAMIF>;
 700                         clock-names = "ppmu";
 701                         status = "disabled";
 702                 };
 703
 704                 ppmu_lcd0: ppmu_lcd0@11e40000 {
 705                         compatible = "samsung,exynos-ppmu";
 706                         reg = <0x11e40000 0x2000>;
 707                         clocks = <&cmu CLK_PPMULCD0>;
 708                         clock-names = "ppmu";
 709                         status = "disabled";
 710                 };
 711
 712                 ppmu_fsys: ppmu_fsys@12630000 {
 713                         compatible = "samsung,exynos-ppmu";
 714                         reg = <0x12630000 0x2000>;
 715                         clocks = <&cmu CLK_PPMUFILE>;
 716                         clock-names = "ppmu";
 717                         status = "disabled";
 718                 };
 719
 720                 ppmu_g3d: ppmu_g3d@13220000 {
 721                         compatible = "samsung,exynos-ppmu";
 722                         reg = <0x13220000 0x2000>;
 723                         clocks = <&cmu CLK_PPMUG3D>;
 724                         clock-names = "ppmu";
 725                         status = "disabled";
 726                 };
 727
 728                 ppmu_mfc: ppmu_mfc@13660000 {
 729                         compatible = "samsung,exynos-ppmu";
 730                         reg = <0x13660000 0x2000>;
 731                         clocks = <&cmu CLK_PPMUMFC_L>;
 732                         clock-names = "ppmu";
 733                         status = "disabled";
 734                 };
 735
 736                 bus_dmc: bus_dmc {
 737                         compatible = "samsung,exynos-bus";
 738                         clocks = <&cmu_dmc CLK_DIV_DMC>;
 739                         clock-names = "bus";
 740                         operating-points-v2 = <&bus_dmc_opp_table>;
 741                         status = "disabled";
 742                 };
 743
 744                 bus_dmc_opp_table: opp_table1 {
 745                         compatible = "operating-points-v2";
 746                         opp-shared;
 747
 748                         opp@50000000 {
 749                                 opp-hz = /bits/ 64 <50000000>;
 750                                 opp-microvolt = <800000>;
 751                         };
 752                         opp@100000000 {
 753                                 opp-hz = /bits/ 64 <100000000>;
 754                                 opp-microvolt = <800000>;
 755                         };
 756                         opp@134000000 {
 757                                 opp-hz = /bits/ 64 <134000000>;
 758                                 opp-microvolt = <800000>;
 759                         };
 760                         opp@200000000 {
 761                                 opp-hz = /bits/ 64 <200000000>;
 762                                 opp-microvolt = <825000>;
 763                         };
 764                         opp@400000000 {
 765                                 opp-hz = /bits/ 64 <400000000>;
 766                                 opp-microvolt = <875000>;
 767                         };
 768                 };
 769
 770                 bus_leftbus: bus_leftbus {
 771                         compatible = "samsung,exynos-bus";
 772                         clocks = <&cmu CLK_DIV_GDL>;
 773                         clock-names = "bus";
 774                         operating-points-v2 = <&bus_leftbus_opp_table>;
 775                         status = "disabled";
 776                 };
 777
 778                 bus_rightbus: bus_rightbus {
 779                         compatible = "samsung,exynos-bus";
 780                         clocks = <&cmu CLK_DIV_GDR>;
 781                         clock-names = "bus";
 782                         operating-points-v2 = <&bus_leftbus_opp_table>;
 783                         status = "disabled";
 784                 };
 785
 786                 bus_lcd0: bus_lcd0 {
 787                         compatible = "samsung,exynos-bus";
 788                         clocks = <&cmu CLK_DIV_ACLK_160>;
 789                         clock-names = "bus";
 790                         operating-points-v2 = <&bus_leftbus_opp_table>;
 791                         status = "disabled";
 792                 };
 793
 794                 bus_fsys: bus_fsys {
 795                         compatible = "samsung,exynos-bus";
 796                         clocks = <&cmu CLK_DIV_ACLK_200>;
 797                         clock-names = "bus";
 798                         operating-points-v2 = <&bus_leftbus_opp_table>;
 799                         status = "disabled";
 800                 };
 801
 802                 bus_mcuisp: bus_mcuisp {
 803                         compatible = "samsung,exynos-bus";
 804                         clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
 805                         clock-names = "bus";
 806                         operating-points-v2 = <&bus_mcuisp_opp_table>;
 807                         status = "disabled";
 808                 };
 809
 810                 bus_isp: bus_isp {
 811                         compatible = "samsung,exynos-bus";
 812                         clocks = <&cmu CLK_DIV_ACLK_266>;
 813                         clock-names = "bus";
 814                         operating-points-v2 = <&bus_isp_opp_table>;
 815                         status = "disabled";
 816                 };
 817
 818                 bus_peril: bus_peril {
 819                         compatible = "samsung,exynos-bus";
 820                         clocks = <&cmu CLK_DIV_ACLK_100>;
 821                         clock-names = "bus";
 822                         operating-points-v2 = <&bus_peril_opp_table>;
 823                         status = "disabled";
 824                 };
 825
 826                 bus_mfc: bus_mfc {
 827                         compatible = "samsung,exynos-bus";
 828                         clocks = <&cmu CLK_SCLK_MFC>;
 829                         clock-names = "bus";
 830                         operating-points-v2 = <&bus_leftbus_opp_table>;
 831                         status = "disabled";
 832                 };
 833
 834                 bus_leftbus_opp_table: opp_table2 {
 835                         compatible = "operating-points-v2";
 836                         opp-shared;
 837
 838                         opp@50000000 {
 839                                 opp-hz = /bits/ 64 <50000000>;
 840                                 opp-microvolt = <900000>;
 841                         };
 842                         opp@80000000 {
 843                                 opp-hz = /bits/ 64 <80000000>;
 844                                 opp-microvolt = <900000>;
 845                         };
 846                         opp@100000000 {
 847                                 opp-hz = /bits/ 64 <100000000>;
 848                                 opp-microvolt = <1000000>;
 849                         };
 850                         opp@134000000 {
 851                                 opp-hz = /bits/ 64 <134000000>;
 852                                 opp-microvolt = <1000000>;
 853                         };
 854                         opp@200000000 {
 855                                 opp-hz = /bits/ 64 <200000000>;
 856                                 opp-microvolt = <1000000>;
 857                         };
 858                 };
 859
 860                 bus_mcuisp_opp_table: opp_table3 {
 861                         compatible = "operating-points-v2";
 862                         opp-shared;
 863
 864                         opp@50000000 {
 865                                 opp-hz = /bits/ 64 <50000000>;
 866                         };
 867                         opp@80000000 {
 868                                 opp-hz = /bits/ 64 <80000000>;
 869                         };
 870                         opp@100000000 {
 871                                 opp-hz = /bits/ 64 <100000000>;
 872                         };
 873                         opp@200000000 {
 874                                 opp-hz = /bits/ 64 <200000000>;
 875                         };
 876                         opp@400000000 {
 877                                 opp-hz = /bits/ 64 <400000000>;
 878                         };
 879                 };
 880
 881                 bus_isp_opp_table: opp_table4 {
 882                         compatible = "operating-points-v2";
 883                         opp-shared;
 884
 885                         opp@50000000 {
 886                                 opp-hz = /bits/ 64 <50000000>;
 887                         };
 888                         opp@80000000 {
 889                                 opp-hz = /bits/ 64 <80000000>;
 890                         };
 891                         opp@100000000 {
 892                                 opp-hz = /bits/ 64 <100000000>;
 893                         };
 894                         opp@200000000 {
 895                                 opp-hz = /bits/ 64 <200000000>;
 896                         };
 897                         opp@300000000 {
 898                                 opp-hz = /bits/ 64 <300000000>;
 899                         };
 900                 };
 901
 902                 bus_peril_opp_table: opp_table5 {
 903                         compatible = "operating-points-v2";
 904                         opp-shared;
 905
 906                         opp@50000000 {
 907                                 opp-hz = /bits/ 64 <50000000>;
 908                         };
 909                         opp@80000000 {
 910                                 opp-hz = /bits/ 64 <80000000>;
 911                         };
 912                         opp@100000000 {
 913                                 opp-hz = /bits/ 64 <100000000>;
 914                         };
 915                 };
 916         };
 917 };
 918
 919 #include "exynos3250-pinctrl.dtsi"