arch/arm/boot/dts/exynos5420-cpus.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC cpu device tree source
   3  *
   4  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This file provides desired ordering for Exynos5420 and Exynos5800
   8  * boards: CPU[0123] being the A15.
   9  *
  10  * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
  11  * but particular boards choose different booting order.
  12  *
  13  * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
  14  * booting cluster (big or LITTLE) is chosen by IROM code by reading
  15  * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
  16  * from the LITTLE: Cortex-A7.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 / {
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu0: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a15";
  31                         reg = <0x0>;
  32                         clocks = <&clock CLK_ARM_CLK>;
  33                         clock-frequency = <1800000000>;
  34                         cci-control-port = <&cci_control1>;
  35                         operating-points-v2 = <&cluster_a15_opp_table>;
  36                         #cooling-cells = <2>; /* min followed by max */
  37                 };
  38
  39                 cpu1: cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a15";
  42                         reg = <0x1>;
  43                         clock-frequency = <1800000000>;
  44                         cci-control-port = <&cci_control1>;
  45                         operating-points-v2 = <&cluster_a15_opp_table>;
  46                         #cooling-cells = <2>; /* min followed by max */
  47                 };
  48
  49                 cpu2: cpu@2 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a15";
  52                         reg = <0x2>;
  53                         clock-frequency = <1800000000>;
  54                         cci-control-port = <&cci_control1>;
  55                         operating-points-v2 = <&cluster_a15_opp_table>;
  56                         #cooling-cells = <2>; /* min followed by max */
  57                 };
  58
  59                 cpu3: cpu@3 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a15";
  62                         reg = <0x3>;
  63                         clock-frequency = <1800000000>;
  64                         cci-control-port = <&cci_control1>;
  65                         operating-points-v2 = <&cluster_a15_opp_table>;
  66                         #cooling-cells = <2>; /* min followed by max */
  67                 };
  68
  69                 cpu4: cpu@100 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a7";
  72                         reg = <0x100>;
  73                         clocks = <&clock CLK_KFC_CLK>;
  74                         clock-frequency = <1000000000>;
  75                         cci-control-port = <&cci_control0>;
  76                         operating-points-v2 = <&cluster_a7_opp_table>;
  77                         #cooling-cells = <2>; /* min followed by max */
  78                 };
  79
  80                 cpu5: cpu@101 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a7";
  83                         reg = <0x101>;
  84                         clock-frequency = <1000000000>;
  85                         cci-control-port = <&cci_control0>;
  86                         operating-points-v2 = <&cluster_a7_opp_table>;
  87                         #cooling-cells = <2>; /* min followed by max */
  88                 };
  89
  90                 cpu6: cpu@102 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0x102>;
  94                         clock-frequency = <1000000000>;
  95                         cci-control-port = <&cci_control0>;
  96                         operating-points-v2 = <&cluster_a7_opp_table>;
  97                         #cooling-cells = <2>; /* min followed by max */
  98                 };
  99
 100                 cpu7: cpu@103 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a7";
 103                         reg = <0x103>;
 104                         clock-frequency = <1000000000>;
 105                         cci-control-port = <&cci_control0>;
 106                         operating-points-v2 = <&cluster_a7_opp_table>;
 107                         #cooling-cells = <2>; /* min followed by max */
 108                 };
 109         };
 110 };