arch/arm/boot/dts/imx6qdl.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2011 Freescale Semiconductor, Inc.
   4 // Copyright 2011 Linaro Ltd.
   5
   6 #include <dt-bindings/clock/imx6qdl-clock.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         /*
  13          * The decompressor and also some bootloaders rely on a
  14          * pre-existing /chosen node to be available to insert the
  15          * command line and merge other ATAGS info.
  16          * Also for U-Boot there must be a pre-existing /memory node.
  17          */
  18         chosen {};
  19         memory { device_type = "memory"; };
  20
  21         aliases {
  22                 ethernet0 = &fec;
  23                 can0 = &can1;
  24                 can1 = &can2;
  25                 gpio0 = &gpio1;
  26                 gpio1 = &gpio2;
  27                 gpio2 = &gpio3;
  28                 gpio3 = &gpio4;
  29                 gpio4 = &gpio5;
  30                 gpio5 = &gpio6;
  31                 gpio6 = &gpio7;
  32                 i2c0 = &i2c1;
  33                 i2c1 = &i2c2;
  34                 i2c2 = &i2c3;
  35                 ipu0 = &ipu1;
  36                 mmc0 = &usdhc1;
  37                 mmc1 = &usdhc2;
  38                 mmc2 = &usdhc3;
  39                 mmc3 = &usdhc4;
  40                 serial0 = &uart1;
  41                 serial1 = &uart2;
  42                 serial2 = &uart3;
  43                 serial3 = &uart4;
  44                 serial4 = &uart5;
  45                 spi0 = &ecspi1;
  46                 spi1 = &ecspi2;
  47                 spi2 = &ecspi3;
  48                 spi3 = &ecspi4;
  49                 usbphy0 = &usbphy1;
  50                 usbphy1 = &usbphy2;
  51         };
  52
  53         clocks {
  54                 ckil {
  55                         compatible = "fsl,imx-ckil", "fixed-clock";
  56                         #clock-cells = <0>;
  57                         clock-frequency = <32768>;
  58                 };
  59
  60                 ckih1 {
  61                         compatible = "fsl,imx-ckih1", "fixed-clock";
  62                         #clock-cells = <0>;
  63                         clock-frequency = <0>;
  64                 };
  65
  66                 osc {
  67                         compatible = "fsl,imx-osc", "fixed-clock";
  68                         #clock-cells = <0>;
  69                         clock-frequency = <24000000>;
  70                 };
  71         };
  72
  73         tempmon: tempmon {
  74                 compatible = "fsl,imx6q-tempmon";
  75                 interrupt-parent = <&gpc>;
  76                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
  77                 fsl,tempmon = <&anatop>;
  78                 fsl,tempmon-data = <&ocotp>;
  79                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  80         };
  81
  82         ldb: ldb {
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
  86                 gpr = <&gpr>;
  87                 status = "disabled";
  88
  89                 lvds-channel@0 {
  90                         #address-cells = <1>;
  91                         #size-cells = <0>;
  92                         reg = <0>;
  93                         status = "disabled";
  94
  95                         port@0 {
  96                                 reg = <0>;
  97
  98                                 lvds0_mux_0: endpoint {
  99                                         remote-endpoint = <&ipu1_di0_lvds0>;
 100                                 };
 101                         };
 102
 103                         port@1 {
 104                                 reg = <1>;
 105
 106                                 lvds0_mux_1: endpoint {
 107                                         remote-endpoint = <&ipu1_di1_lvds0>;
 108                                 };
 109                         };
 110                 };
 111
 112                 lvds-channel@1 {
 113                         #address-cells = <1>;
 114                         #size-cells = <0>;
 115                         reg = <1>;
 116                         status = "disabled";
 117
 118                         port@0 {
 119                                 reg = <0>;
 120
 121                                 lvds1_mux_0: endpoint {
 122                                         remote-endpoint = <&ipu1_di0_lvds1>;
 123                                 };
 124                         };
 125
 126                         port@1 {
 127                                 reg = <1>;
 128
 129                                 lvds1_mux_1: endpoint {
 130                                         remote-endpoint = <&ipu1_di1_lvds1>;
 131                                 };
 132                         };
 133                 };
 134         };
 135
 136         pmu: pmu {
 137                 compatible = "arm,cortex-a9-pmu";
 138                 interrupt-parent = <&gpc>;
 139                 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 140         };
 141
 142         soc {
 143                 #address-cells = <1>;
 144                 #size-cells = <1>;
 145                 compatible = "simple-bus";
 146                 interrupt-parent = <&gpc>;
 147                 ranges;
 148
 149                 dma_apbh: dma-apbh@110000 {
 150                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 151                         reg = <0x00110000 0x2000>;
 152                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 153                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 154                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 155                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 156                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 157                         #dma-cells = <1>;
 158                         dma-channels = <4>;
 159                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
 160                 };
 161
 162                 gpmi: gpmi-nand@112000 {
 163                         compatible = "fsl,imx6q-gpmi-nand";
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 167                         reg-names = "gpmi-nand", "bch";
 168                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 169                         interrupt-names = "bch";
 170                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 171                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 172                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 173                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 174                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 175                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 176                                       "gpmi_bch_apb", "per1_bch";
 177                         dmas = <&dma_apbh 0>;
 178                         dma-names = "rx-tx";
 179                         status = "disabled";
 180                 };
 181
 182                 hdmi: hdmi@120000 {
 183                         #address-cells = <1>;
 184                         #size-cells = <0>;
 185                         reg = <0x00120000 0x9000>;
 186                         interrupts = <0 115 0x04>;
 187                         gpr = <&gpr>;
 188                         clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
 189                                  <&clks IMX6QDL_CLK_HDMI_ISFR>;
 190                         clock-names = "iahb", "isfr";
 191                         status = "disabled";
 192
 193                         port@0 {
 194                                 reg = <0>;
 195
 196                                 hdmi_mux_0: endpoint {
 197                                         remote-endpoint = <&ipu1_di0_hdmi>;
 198                                 };
 199                         };
 200
 201                         port@1 {
 202                                 reg = <1>;
 203
 204                                 hdmi_mux_1: endpoint {
 205                                         remote-endpoint = <&ipu1_di1_hdmi>;
 206                                 };
 207                         };
 208                 };
 209
 210                 gpu_3d: gpu@130000 {
 211                         compatible = "vivante,gc";
 212                         reg = <0x00130000 0x4000>;
 213                         interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 214                         clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
 215                                  <&clks IMX6QDL_CLK_GPU3D_CORE>,
 216                                  <&clks IMX6QDL_CLK_GPU3D_SHADER>;
 217                         clock-names = "bus", "core", "shader";
 218                         power-domains = <&pd_pu>;
 219                 };
 220
 221                 gpu_2d: gpu@134000 {
 222                         compatible = "vivante,gc";
 223                         reg = <0x00134000 0x4000>;
 224                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 225                         clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
 226                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 227                         clock-names = "bus", "core";
 228                         power-domains = <&pd_pu>;
 229                 };
 230
 231                 timer@a00600 {
 232                         compatible = "arm,cortex-a9-twd-timer";
 233                         reg = <0x00a00600 0x20>;
 234                         interrupts = <1 13 0xf01>;
 235                         interrupt-parent = <&intc>;
 236                         clocks = <&clks IMX6QDL_CLK_TWD>;
 237                 };
 238
 239                 intc: interrupt-controller@a01000 {
 240                         compatible = "arm,cortex-a9-gic";
 241                         #interrupt-cells = <3>;
 242                         interrupt-controller;
 243                         reg = <0x00a01000 0x1000>,
 244                               <0x00a00100 0x100>;
 245                         interrupt-parent = <&intc>;
 246                 };
 247
 248                 L2: l2-cache@a02000 {
 249                         compatible = "arm,pl310-cache";
 250                         reg = <0x00a02000 0x1000>;
 251                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 252                         cache-unified;
 253                         cache-level = <2>;
 254                         arm,tag-latency = <4 2 3>;
 255                         arm,data-latency = <4 2 3>;
 256                         arm,shared-override;
 257                 };
 258
 259                 pcie: pcie@1ffc000 {
 260                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 261                         reg = <0x01ffc000 0x04000>,
 262                               <0x01f00000 0x80000>;
 263                         reg-names = "dbi", "config";
 264                         #address-cells = <3>;
 265                         #size-cells = <2>;
 266                         device_type = "pci";
 267                         bus-range = <0x00 0xff>;
 268                         ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 269                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 270                         num-lanes = <1>;
 271                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 272                         interrupt-names = "msi";
 273                         #interrupt-cells = <1>;
 274                         interrupt-map-mask = <0 0 0 0x7>;
 275                         interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 276                                         <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 277                                         <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 278                                         <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
 280                                  <&clks IMX6QDL_CLK_LVDS1_GATE>,
 281                                  <&clks IMX6QDL_CLK_PCIE_REF_125M>;
 282                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 283                         status = "disabled";
 284                 };
 285
 286                 aips-bus@2000000 { /* AIPS1 */
 287                         compatible = "fsl,aips-bus", "simple-bus";
 288                         #address-cells = <1>;
 289                         #size-cells = <1>;
 290                         reg = <0x02000000 0x100000>;
 291                         ranges;
 292
 293                         spba-bus@2000000 {
 294                                 compatible = "fsl,spba-bus", "simple-bus";
 295                                 #address-cells = <1>;
 296                                 #size-cells = <1>;
 297                                 reg = <0x02000000 0x40000>;
 298                                 ranges;
 299
 300                                 spdif: spdif@2004000 {
 301                                         compatible = "fsl,imx35-spdif";
 302                                         reg = <0x02004000 0x4000>;
 303                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 304                                         dmas = <&sdma 14 18 0>,
 305                                                <&sdma 15 18 0>;
 306                                         dma-names = "rx", "tx";
 307                                         clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
 308                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
 309                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
 310                                                  <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
 311                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
 312                                         clock-names = "core",  "rxtx0",
 313                                                       "rxtx1", "rxtx2",
 314                                                       "rxtx3", "rxtx4",
 315                                                       "rxtx5", "rxtx6",
 316                                                       "rxtx7", "spba";
 317                                         status = "disabled";
 318                                 };
 319
 320                                 ecspi1: ecspi@2008000 {
 321                                         #address-cells = <1>;
 322                                         #size-cells = <0>;
 323                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 324                                         reg = <0x02008000 0x4000>;
 325                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 326                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 327                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 328                                         clock-names = "ipg", "per";
 329                                         dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
 330                                         dma-names = "rx", "tx";
 331                                         status = "disabled";
 332                                 };
 333
 334                                 ecspi2: ecspi@200c000 {
 335                                         #address-cells = <1>;
 336                                         #size-cells = <0>;
 337                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 338                                         reg = <0x0200c000 0x4000>;
 339                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 340                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 341                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 342                                         clock-names = "ipg", "per";
 343                                         dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
 344                                         dma-names = "rx", "tx";
 345                                         status = "disabled";
 346                                 };
 347
 348                                 ecspi3: ecspi@2010000 {
 349                                         #address-cells = <1>;
 350                                         #size-cells = <0>;
 351                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 352                                         reg = <0x02010000 0x4000>;
 353                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 354                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 355                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 356                                         clock-names = "ipg", "per";
 357                                         dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
 358                                         dma-names = "rx", "tx";
 359                                         status = "disabled";
 360                                 };
 361
 362                                 ecspi4: ecspi@2014000 {
 363                                         #address-cells = <1>;
 364                                         #size-cells = <0>;
 365                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 366                                         reg = <0x02014000 0x4000>;
 367                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 368                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 369                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 370                                         clock-names = "ipg", "per";
 371                                         dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
 372                                         dma-names = "rx", "tx";
 373                                         status = "disabled";
 374                                 };
 375
 376                                 uart1: serial@2020000 {
 377                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 378                                         reg = <0x02020000 0x4000>;
 379                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 380                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 381                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 382                                         clock-names = "ipg", "per";
 383                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 384                                         dma-names = "rx", "tx";
 385                                         status = "disabled";
 386                                 };
 387
 388                                 esai: esai@2024000 {
 389                                         #sound-dai-cells = <0>;
 390                                         compatible = "fsl,imx35-esai";
 391                                         reg = <0x02024000 0x4000>;
 392                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 393                                         clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
 394                                                  <&clks IMX6QDL_CLK_ESAI_MEM>,
 395                                                  <&clks IMX6QDL_CLK_ESAI_EXTAL>,
 396                                                  <&clks IMX6QDL_CLK_ESAI_IPG>,
 397                                                  <&clks IMX6QDL_CLK_SPBA>;
 398                                         clock-names = "core", "mem", "extal", "fsys", "spba";
 399                                         dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
 400                                         dma-names = "rx", "tx";
 401                                         status = "disabled";
 402                                 };
 403
 404                                 ssi1: ssi@2028000 {
 405                                         #sound-dai-cells = <0>;
 406                                         compatible = "fsl,imx6q-ssi",
 407                                                         "fsl,imx51-ssi";
 408                                         reg = <0x02028000 0x4000>;
 409                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 410                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
 411                                                  <&clks IMX6QDL_CLK_SSI1>;
 412                                         clock-names = "ipg", "baud";
 413                                         dmas = <&sdma 37 1 0>,
 414                                                <&sdma 38 1 0>;
 415                                         dma-names = "rx", "tx";
 416                                         fsl,fifo-depth = <15>;
 417                                         status = "disabled";
 418                                 };
 419
 420                                 ssi2: ssi@202c000 {
 421                                         #sound-dai-cells = <0>;
 422                                         compatible = "fsl,imx6q-ssi",
 423                                                         "fsl,imx51-ssi";
 424                                         reg = <0x0202c000 0x4000>;
 425                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 426                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
 427                                                  <&clks IMX6QDL_CLK_SSI2>;
 428                                         clock-names = "ipg", "baud";
 429                                         dmas = <&sdma 41 1 0>,
 430                                                <&sdma 42 1 0>;
 431                                         dma-names = "rx", "tx";
 432                                         fsl,fifo-depth = <15>;
 433                                         status = "disabled";
 434                                 };
 435
 436                                 ssi3: ssi@2030000 {
 437                                         #sound-dai-cells = <0>;
 438                                         compatible = "fsl,imx6q-ssi",
 439                                                         "fsl,imx51-ssi";
 440                                         reg = <0x02030000 0x4000>;
 441                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 442                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
 443                                                  <&clks IMX6QDL_CLK_SSI3>;
 444                                         clock-names = "ipg", "baud";
 445                                         dmas = <&sdma 45 1 0>,
 446                                                <&sdma 46 1 0>;
 447                                         dma-names = "rx", "tx";
 448                                         fsl,fifo-depth = <15>;
 449                                         status = "disabled";
 450                                 };
 451
 452                                 asrc: asrc@2034000 {
 453                                         compatible = "fsl,imx53-asrc";
 454                                         reg = <0x02034000 0x4000>;
 455                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 456                                         clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
 457                                                 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
 458                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 459                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 460                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 461                                                 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
 462                                                 <&clks IMX6QDL_CLK_SPBA>;
 463                                         clock-names = "mem", "ipg", "asrck_0",
 464                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 465                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 466                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 467                                                 "asrck_d", "asrck_e", "asrck_f", "spba";
 468                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 469                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 470                                         dma-names = "rxa", "rxb", "rxc",
 471                                                         "txa", "txb", "txc";
 472                                         fsl,asrc-rate  = <48000>;
 473                                         fsl,asrc-width = <16>;
 474                                         status = "okay";
 475                                 };
 476
 477                                 spba@203c000 {
 478                                         reg = <0x0203c000 0x4000>;
 479                                 };
 480                         };
 481
 482                         vpu: vpu@2040000 {
 483                                 compatible = "cnm,coda960";
 484                                 reg = <0x02040000 0x3c000>;
 485                                 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
 486                                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 487                                 interrupt-names = "bit", "jpeg";
 488                                 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
 489                                          <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
 490                                 clock-names = "per", "ahb";
 491                                 power-domains = <&pd_pu>;
 492                                 resets = <&src 1>;
 493                                 iram = <&ocram>;
 494                         };
 495
 496                         aipstz@207c000 { /* AIPSTZ1 */
 497                                 reg = <0x0207c000 0x4000>;
 498                         };
 499
 500                         pwm1: pwm@2080000 {
 501                                 #pwm-cells = <2>;
 502                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 503                                 reg = <0x02080000 0x4000>;
 504                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 505                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 506                                          <&clks IMX6QDL_CLK_PWM1>;
 507                                 clock-names = "ipg", "per";
 508                                 status = "disabled";
 509                         };
 510
 511                         pwm2: pwm@2084000 {
 512                                 #pwm-cells = <2>;
 513                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 514                                 reg = <0x02084000 0x4000>;
 515                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 516                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 517                                          <&clks IMX6QDL_CLK_PWM2>;
 518                                 clock-names = "ipg", "per";
 519                                 status = "disabled";
 520                         };
 521
 522                         pwm3: pwm@2088000 {
 523                                 #pwm-cells = <2>;
 524                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 525                                 reg = <0x02088000 0x4000>;
 526                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 527                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 528                                          <&clks IMX6QDL_CLK_PWM3>;
 529                                 clock-names = "ipg", "per";
 530                                 status = "disabled";
 531                         };
 532
 533                         pwm4: pwm@208c000 {
 534                                 #pwm-cells = <2>;
 535                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 536                                 reg = <0x0208c000 0x4000>;
 537                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 538                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 539                                          <&clks IMX6QDL_CLK_PWM4>;
 540                                 clock-names = "ipg", "per";
 541                                 status = "disabled";
 542                         };
 543
 544                         can1: flexcan@2090000 {
 545                                 compatible = "fsl,imx6q-flexcan";
 546                                 reg = <0x02090000 0x4000>;
 547                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 548                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 549                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 550                                 clock-names = "ipg", "per";
 551                                 status = "disabled";
 552                         };
 553
 554                         can2: flexcan@2094000 {
 555                                 compatible = "fsl,imx6q-flexcan";
 556                                 reg = <0x02094000 0x4000>;
 557                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 558                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 559                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 560                                 clock-names = "ipg", "per";
 561                                 status = "disabled";
 562                         };
 563
 564                         gpt: gpt@2098000 {
 565                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 566                                 reg = <0x02098000 0x4000>;
 567                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 568                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 569                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>,
 570                                          <&clks IMX6QDL_CLK_GPT_3M>;
 571                                 clock-names = "ipg", "per", "osc_per";
 572                         };
 573
 574                         gpio1: gpio@209c000 {
 575                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 576                                 reg = <0x0209c000 0x4000>;
 577                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 578                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 579                                 gpio-controller;
 580                                 #gpio-cells = <2>;
 581                                 interrupt-controller;
 582                                 #interrupt-cells = <2>;
 583                         };
 584
 585                         gpio2: gpio@20a0000 {
 586                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 587                                 reg = <0x020a0000 0x4000>;
 588                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 589                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 590                                 gpio-controller;
 591                                 #gpio-cells = <2>;
 592                                 interrupt-controller;
 593                                 #interrupt-cells = <2>;
 594                         };
 595
 596                         gpio3: gpio@20a4000 {
 597                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 598                                 reg = <0x020a4000 0x4000>;
 599                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 600                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 601                                 gpio-controller;
 602                                 #gpio-cells = <2>;
 603                                 interrupt-controller;
 604                                 #interrupt-cells = <2>;
 605                         };
 606
 607                         gpio4: gpio@20a8000 {
 608                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 609                                 reg = <0x020a8000 0x4000>;
 610                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 611                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 612                                 gpio-controller;
 613                                 #gpio-cells = <2>;
 614                                 interrupt-controller;
 615                                 #interrupt-cells = <2>;
 616                         };
 617
 618                         gpio5: gpio@20ac000 {
 619                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 620                                 reg = <0x020ac000 0x4000>;
 621                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 622                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 623                                 gpio-controller;
 624                                 #gpio-cells = <2>;
 625                                 interrupt-controller;
 626                                 #interrupt-cells = <2>;
 627                         };
 628
 629                         gpio6: gpio@20b0000 {
 630                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 631                                 reg = <0x020b0000 0x4000>;
 632                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 633                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 634                                 gpio-controller;
 635                                 #gpio-cells = <2>;
 636                                 interrupt-controller;
 637                                 #interrupt-cells = <2>;
 638                         };
 639
 640                         gpio7: gpio@20b4000 {
 641                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 642                                 reg = <0x020b4000 0x4000>;
 643                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 644                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 645                                 gpio-controller;
 646                                 #gpio-cells = <2>;
 647                                 interrupt-controller;
 648                                 #interrupt-cells = <2>;
 649                         };
 650
 651                         kpp: kpp@20b8000 {
 652                                 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 653                                 reg = <0x020b8000 0x4000>;
 654                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 655                                 clocks = <&clks IMX6QDL_CLK_IPG>;
 656                                 status = "disabled";
 657                         };
 658
 659                         wdog1: wdog@20bc000 {
 660                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 661                                 reg = <0x020bc000 0x4000>;
 662                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 663                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 664                         };
 665
 666                         wdog2: wdog@20c0000 {
 667                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 668                                 reg = <0x020c0000 0x4000>;
 669                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 670                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 671                                 status = "disabled";
 672                         };
 673
 674                         clks: ccm@20c4000 {
 675                                 compatible = "fsl,imx6q-ccm";
 676                                 reg = <0x020c4000 0x4000>;
 677                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 678                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 679                                 #clock-cells = <1>;
 680                         };
 681
 682                         anatop: anatop@20c8000 {
 683                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 684                                 reg = <0x020c8000 0x1000>;
 685                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 686                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 687                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 688
 689                                 reg_vdd1p1: regulator-1p1 {
 690                                         compatible = "fsl,anatop-regulator";
 691                                         regulator-name = "vdd1p1";
 692                                         regulator-min-microvolt = <1000000>;
 693                                         regulator-max-microvolt = <1200000>;
 694                                         regulator-always-on;
 695                                         anatop-reg-offset = <0x110>;
 696                                         anatop-vol-bit-shift = <8>;
 697                                         anatop-vol-bit-width = <5>;
 698                                         anatop-min-bit-val = <4>;
 699                                         anatop-min-voltage = <800000>;
 700                                         anatop-max-voltage = <1375000>;
 701                                         anatop-enable-bit = <0>;
 702                                 };
 703
 704                                 reg_vdd3p0: regulator-3p0 {
 705                                         compatible = "fsl,anatop-regulator";
 706                                         regulator-name = "vdd3p0";
 707                                         regulator-min-microvolt = <2800000>;
 708                                         regulator-max-microvolt = <3150000>;
 709                                         regulator-always-on;
 710                                         anatop-reg-offset = <0x120>;
 711                                         anatop-vol-bit-shift = <8>;
 712                                         anatop-vol-bit-width = <5>;
 713                                         anatop-min-bit-val = <0>;
 714                                         anatop-min-voltage = <2625000>;
 715                                         anatop-max-voltage = <3400000>;
 716                                         anatop-enable-bit = <0>;
 717                                 };
 718
 719                                 reg_vdd2p5: regulator-2p5 {
 720                                         compatible = "fsl,anatop-regulator";
 721                                         regulator-name = "vdd2p5";
 722                                         regulator-min-microvolt = <2250000>;
 723                                         regulator-max-microvolt = <2750000>;
 724                                         regulator-always-on;
 725                                         anatop-reg-offset = <0x130>;
 726                                         anatop-vol-bit-shift = <8>;
 727                                         anatop-vol-bit-width = <5>;
 728                                         anatop-min-bit-val = <0>;
 729                                         anatop-min-voltage = <2100000>;
 730                                         anatop-max-voltage = <2875000>;
 731                                         anatop-enable-bit = <0>;
 732                                 };
 733
 734                                 reg_arm: regulator-vddcore {
 735                                         compatible = "fsl,anatop-regulator";
 736                                         regulator-name = "vddarm";
 737                                         regulator-min-microvolt = <725000>;
 738                                         regulator-max-microvolt = <1450000>;
 739                                         regulator-always-on;
 740                                         anatop-reg-offset = <0x140>;
 741                                         anatop-vol-bit-shift = <0>;
 742                                         anatop-vol-bit-width = <5>;
 743                                         anatop-delay-reg-offset = <0x170>;
 744                                         anatop-delay-bit-shift = <24>;
 745                                         anatop-delay-bit-width = <2>;
 746                                         anatop-min-bit-val = <1>;
 747                                         anatop-min-voltage = <725000>;
 748                                         anatop-max-voltage = <1450000>;
 749                                 };
 750
 751                                 reg_pu: regulator-vddpu {
 752                                         compatible = "fsl,anatop-regulator";
 753                                         regulator-name = "vddpu";
 754                                         regulator-min-microvolt = <725000>;
 755                                         regulator-max-microvolt = <1450000>;
 756                                         regulator-enable-ramp-delay = <380>;
 757                                         anatop-reg-offset = <0x140>;
 758                                         anatop-vol-bit-shift = <9>;
 759                                         anatop-vol-bit-width = <5>;
 760                                         anatop-delay-reg-offset = <0x170>;
 761                                         anatop-delay-bit-shift = <26>;
 762                                         anatop-delay-bit-width = <2>;
 763                                         anatop-min-bit-val = <1>;
 764                                         anatop-min-voltage = <725000>;
 765                                         anatop-max-voltage = <1450000>;
 766                                 };
 767
 768                                 reg_soc: regulator-vddsoc {
 769                                         compatible = "fsl,anatop-regulator";
 770                                         regulator-name = "vddsoc";
 771                                         regulator-min-microvolt = <725000>;
 772                                         regulator-max-microvolt = <1450000>;
 773                                         regulator-always-on;
 774                                         anatop-reg-offset = <0x140>;
 775                                         anatop-vol-bit-shift = <18>;
 776                                         anatop-vol-bit-width = <5>;
 777                                         anatop-delay-reg-offset = <0x170>;
 778                                         anatop-delay-bit-shift = <28>;
 779                                         anatop-delay-bit-width = <2>;
 780                                         anatop-min-bit-val = <1>;
 781                                         anatop-min-voltage = <725000>;
 782                                         anatop-max-voltage = <1450000>;
 783                                 };
 784                         };
 785
 786                         usbphy1: usbphy@20c9000 {
 787                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 788                                 reg = <0x020c9000 0x1000>;
 789                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 790                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 791                                 fsl,anatop = <&anatop>;
 792                         };
 793
 794                         usbphy2: usbphy@20ca000 {
 795                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 796                                 reg = <0x020ca000 0x1000>;
 797                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 798                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 799                                 fsl,anatop = <&anatop>;
 800                         };
 801
 802                         snvs: snvs@20cc000 {
 803                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 804                                 reg = <0x020cc000 0x4000>;
 805
 806                                 snvs_rtc: snvs-rtc-lp {
 807                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 808                                         regmap = <&snvs>;
 809                                         offset = <0x34>;
 810                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 811                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 812                                 };
 813
 814                                 snvs_poweroff: snvs-poweroff {
 815                                         compatible = "syscon-poweroff";
 816                                         regmap = <&snvs>;
 817                                         offset = <0x38>;
 818                                         value = <0x60>;
 819                                         mask = <0x60>;
 820                                         status = "disabled";
 821                                 };
 822
 823                                 snvs_lpgpr: snvs-lpgpr {
 824                                         compatible = "fsl,imx6q-snvs-lpgpr";
 825                                 };
 826                         };
 827
 828                         epit1: epit@20d0000 { /* EPIT1 */
 829                                 reg = <0x020d0000 0x4000>;
 830                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 831                         };
 832
 833                         epit2: epit@20d4000 { /* EPIT2 */
 834                                 reg = <0x020d4000 0x4000>;
 835                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 836                         };
 837
 838                         src: src@20d8000 {
 839                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 840                                 reg = <0x020d8000 0x4000>;
 841                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 842                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 843                                 #reset-cells = <1>;
 844                         };
 845
 846                         gpc: gpc@20dc000 {
 847                                 compatible = "fsl,imx6q-gpc";
 848                                 reg = <0x020dc000 0x4000>;
 849                                 interrupt-controller;
 850                                 #interrupt-cells = <3>;
 851                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 852                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 853                                 interrupt-parent = <&intc>;
 854                                 clocks = <&clks IMX6QDL_CLK_IPG>;
 855                                 clock-names = "ipg";
 856
 857                                 pgc {
 858                                         #address-cells = <1>;
 859                                         #size-cells = <0>;
 860
 861                                         power-domain@0 {
 862                                                 reg = <0>;
 863                                                 #power-domain-cells = <0>;
 864                                         };
 865                                         pd_pu: power-domain@1 {
 866                                                 reg = <1>;
 867                                                 #power-domain-cells = <0>;
 868                                                 power-supply = <&reg_pu>;
 869                                                 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
 870                                                          <&clks IMX6QDL_CLK_GPU3D_SHADER>,
 871                                                          <&clks IMX6QDL_CLK_GPU2D_CORE>,
 872                                                          <&clks IMX6QDL_CLK_GPU2D_AXI>,
 873                                                          <&clks IMX6QDL_CLK_OPENVG_AXI>,
 874                                                          <&clks IMX6QDL_CLK_VPU_AXI>;
 875                                         };
 876                                 };
 877                         };
 878
 879                         gpr: iomuxc-gpr@20e0000 {
 880                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
 881                                 reg = <0x20e0000 0x38>;
 882
 883                                 mux: mux-controller {
 884                                         compatible = "mmio-mux";
 885                                         #mux-control-cells = <1>;
 886                                 };
 887                         };
 888
 889                         iomuxc: iomuxc@20e0000 {
 890                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 891                                 reg = <0x20e0000 0x4000>;
 892                         };
 893
 894                         dcic1: dcic@20e4000 {
 895                                 reg = <0x020e4000 0x4000>;
 896                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 897                         };
 898
 899                         dcic2: dcic@20e8000 {
 900                                 reg = <0x020e8000 0x4000>;
 901                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 902                         };
 903
 904                         sdma: sdma@20ec000 {
 905                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 906                                 reg = <0x020ec000 0x4000>;
 907                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 908                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 909                                          <&clks IMX6QDL_CLK_SDMA>;
 910                                 clock-names = "ipg", "ahb";
 911                                 #dma-cells = <3>;
 912                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 913                         };
 914                 };
 915
 916                 aips-bus@2100000 { /* AIPS2 */
 917                         compatible = "fsl,aips-bus", "simple-bus";
 918                         #address-cells = <1>;
 919                         #size-cells = <1>;
 920                         reg = <0x02100000 0x100000>;
 921                         ranges;
 922
 923                         crypto: caam@2100000 {
 924                                 compatible = "fsl,sec-v4.0";
 925                                 #address-cells = <1>;
 926                                 #size-cells = <1>;
 927                                 reg = <0x2100000 0x10000>;
 928                                 ranges = <0 0x2100000 0x10000>;
 929                                 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
 930                                          <&clks IMX6QDL_CLK_CAAM_ACLK>,
 931                                          <&clks IMX6QDL_CLK_CAAM_IPG>,
 932                                          <&clks IMX6QDL_CLK_EIM_SLOW>;
 933                                 clock-names = "mem", "aclk", "ipg", "emi_slow";
 934
 935                                 sec_jr0: jr0@1000 {
 936                                         compatible = "fsl,sec-v4.0-job-ring";
 937                                         reg = <0x1000 0x1000>;
 938                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 939                                 };
 940
 941                                 sec_jr1: jr1@2000 {
 942                                         compatible = "fsl,sec-v4.0-job-ring";
 943                                         reg = <0x2000 0x1000>;
 944                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 945                                 };
 946                         };
 947
 948                         aipstz@217c000 { /* AIPSTZ2 */
 949                                 reg = <0x0217c000 0x4000>;
 950                         };
 951
 952                         usbotg: usb@2184000 {
 953                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 954                                 reg = <0x02184000 0x200>;
 955                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 956                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 957                                 fsl,usbphy = <&usbphy1>;
 958                                 fsl,usbmisc = <&usbmisc 0>;
 959                                 ahb-burst-config = <0x0>;
 960                                 tx-burst-size-dword = <0x10>;
 961                                 rx-burst-size-dword = <0x10>;
 962                                 status = "disabled";
 963                         };
 964
 965                         usbh1: usb@2184200 {
 966                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 967                                 reg = <0x02184200 0x200>;
 968                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 969                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 970                                 fsl,usbphy = <&usbphy2>;
 971                                 fsl,usbmisc = <&usbmisc 1>;
 972                                 dr_mode = "host";
 973                                 ahb-burst-config = <0x0>;
 974                                 tx-burst-size-dword = <0x10>;
 975                                 rx-burst-size-dword = <0x10>;
 976                                 status = "disabled";
 977                         };
 978
 979                         usbh2: usb@2184400 {
 980                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 981                                 reg = <0x02184400 0x200>;
 982                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 983                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 984                                 fsl,usbmisc = <&usbmisc 2>;
 985                                 dr_mode = "host";
 986                                 ahb-burst-config = <0x0>;
 987                                 tx-burst-size-dword = <0x10>;
 988                                 rx-burst-size-dword = <0x10>;
 989                                 status = "disabled";
 990                         };
 991
 992                         usbh3: usb@2184600 {
 993                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 994                                 reg = <0x02184600 0x200>;
 995                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 996                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 997                                 fsl,usbmisc = <&usbmisc 3>;
 998                                 dr_mode = "host";
 999                                 ahb-burst-config = <0x0>;
1000                                 tx-burst-size-dword = <0x10>;
1001                                 rx-burst-size-dword = <0x10>;
1002                                 status = "disabled";
1003                         };
1004
1005                         usbmisc: usbmisc@2184800 {
1006                                 #index-cells = <1>;
1007                                 compatible = "fsl,imx6q-usbmisc";
1008                                 reg = <0x02184800 0x200>;
1009                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1010                         };
1011
1012                         fec: ethernet@2188000 {
1013                                 compatible = "fsl,imx6q-fec";
1014                                 reg = <0x02188000 0x4000>;
1015                                 interrupt-names = "int0", "pps";
1016                                 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1017                                              <0 119 IRQ_TYPE_LEVEL_HIGH>;
1018                                 clocks = <&clks IMX6QDL_CLK_ENET>,
1019                                          <&clks IMX6QDL_CLK_ENET>,
1020                                          <&clks IMX6QDL_CLK_ENET_REF>;
1021                                 clock-names = "ipg", "ahb", "ptp";
1022                                 status = "disabled";
1023                         };
1024
1025                         mlb@218c000 {
1026                                 reg = <0x0218c000 0x4000>;
1027                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1028                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1029                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
1030                         };
1031
1032                         usdhc1: usdhc@2190000 {
1033                                 compatible = "fsl,imx6q-usdhc";
1034                                 reg = <0x02190000 0x4000>;
1035                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1036                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1037                                          <&clks IMX6QDL_CLK_USDHC1>,
1038                                          <&clks IMX6QDL_CLK_USDHC1>;
1039                                 clock-names = "ipg", "ahb", "per";
1040                                 bus-width = <4>;
1041                                 status = "disabled";
1042                         };
1043
1044                         usdhc2: usdhc@2194000 {
1045                                 compatible = "fsl,imx6q-usdhc";
1046                                 reg = <0x02194000 0x4000>;
1047                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1048                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1049                                          <&clks IMX6QDL_CLK_USDHC2>,
1050                                          <&clks IMX6QDL_CLK_USDHC2>;
1051                                 clock-names = "ipg", "ahb", "per";
1052                                 bus-width = <4>;
1053                                 status = "disabled";
1054                         };
1055
1056                         usdhc3: usdhc@2198000 {
1057                                 compatible = "fsl,imx6q-usdhc";
1058                                 reg = <0x02198000 0x4000>;
1059                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1060                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1061                                          <&clks IMX6QDL_CLK_USDHC3>,
1062                                          <&clks IMX6QDL_CLK_USDHC3>;
1063                                 clock-names = "ipg", "ahb", "per";
1064                                 bus-width = <4>;
1065                                 status = "disabled";
1066                         };
1067
1068                         usdhc4: usdhc@219c000 {
1069                                 compatible = "fsl,imx6q-usdhc";
1070                                 reg = <0x0219c000 0x4000>;
1071                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1072                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1073                                          <&clks IMX6QDL_CLK_USDHC4>,
1074                                          <&clks IMX6QDL_CLK_USDHC4>;
1075                                 clock-names = "ipg", "ahb", "per";
1076                                 bus-width = <4>;
1077                                 status = "disabled";
1078                         };
1079
1080                         i2c1: i2c@21a0000 {
1081                                 #address-cells = <1>;
1082                                 #size-cells = <0>;
1083                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1084                                 reg = <0x021a0000 0x4000>;
1085                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1086                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
1087                                 status = "disabled";
1088                         };
1089
1090                         i2c2: i2c@21a4000 {
1091                                 #address-cells = <1>;
1092                                 #size-cells = <0>;
1093                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1094                                 reg = <0x021a4000 0x4000>;
1095                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1096                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
1097                                 status = "disabled";
1098                         };
1099
1100                         i2c3: i2c@21a8000 {
1101                                 #address-cells = <1>;
1102                                 #size-cells = <0>;
1103                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1104                                 reg = <0x021a8000 0x4000>;
1105                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1106                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
1107                                 status = "disabled";
1108                         };
1109
1110                         romcp@21ac000 {
1111                                 reg = <0x021ac000 0x4000>;
1112                         };
1113
1114                         mmdc0: mmdc@21b0000 { /* MMDC0 */
1115                                 compatible = "fsl,imx6q-mmdc";
1116                                 reg = <0x021b0000 0x4000>;
1117                         };
1118
1119                         mmdc1: mmdc@21b4000 { /* MMDC1 */
1120                                 reg = <0x021b4000 0x4000>;
1121                         };
1122
1123                         weim: weim@21b8000 {
1124                                 #address-cells = <2>;
1125                                 #size-cells = <1>;
1126                                 compatible = "fsl,imx6q-weim";
1127                                 reg = <0x021b8000 0x4000>;
1128                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1129                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1130                                 fsl,weim-cs-gpr = <&gpr>;
1131                                 status = "disabled";
1132                         };
1133
1134                         ocotp: ocotp@21bc000 {
1135                                 compatible = "fsl,imx6q-ocotp", "syscon";
1136                                 reg = <0x021bc000 0x4000>;
1137                                 clocks = <&clks IMX6QDL_CLK_IIM>;
1138                         };
1139
1140                         tzasc@21d0000 { /* TZASC1 */
1141                                 reg = <0x021d0000 0x4000>;
1142                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1143                         };
1144
1145                         tzasc@21d4000 { /* TZASC2 */
1146                                 reg = <0x021d4000 0x4000>;
1147                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1148                         };
1149
1150                         audmux: audmux@21d8000 {
1151                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1152                                 reg = <0x021d8000 0x4000>;
1153                                 status = "disabled";
1154                         };
1155
1156                         mipi_csi: mipi@21dc000 {
1157                                 compatible = "fsl,imx6-mipi-csi2";
1158                                 reg = <0x021dc000 0x4000>;
1159                                 #address-cells = <1>;
1160                                 #size-cells = <0>;
1161                                 interrupts = <0 100 0x04>, <0 101 0x04>;
1162                                 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1163                                          <&clks IMX6QDL_CLK_VIDEO_27M>,
1164                                          <&clks IMX6QDL_CLK_EIM_PODF>;
1165                                 clock-names = "dphy", "ref", "pix";
1166                                 status = "disabled";
1167                         };
1168
1169                         mipi_dsi: mipi@21e0000 {
1170                                 reg = <0x021e0000 0x4000>;
1171                                 status = "disabled";
1172
1173                                 ports {
1174                                         #address-cells = <1>;
1175                                         #size-cells = <0>;
1176
1177                                         port@0 {
1178                                                 reg = <0>;
1179
1180                                                 mipi_mux_0: endpoint {
1181                                                         remote-endpoint = <&ipu1_di0_mipi>;
1182                                                 };
1183                                         };
1184
1185                                         port@1 {
1186                                                 reg = <1>;
1187
1188                                                 mipi_mux_1: endpoint {
1189                                                         remote-endpoint = <&ipu1_di1_mipi>;
1190                                                 };
1191                                         };
1192                                 };
1193                         };
1194
1195                         vdoa@21e4000 {
1196                                 compatible = "fsl,imx6q-vdoa";
1197                                 reg = <0x021e4000 0x4000>;
1198                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1199                                 clocks = <&clks IMX6QDL_CLK_VDOA>;
1200                         };
1201
1202                         uart2: serial@21e8000 {
1203                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1204                                 reg = <0x021e8000 0x4000>;
1205                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1206                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1207                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1208                                 clock-names = "ipg", "per";
1209                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1210                                 dma-names = "rx", "tx";
1211                                 status = "disabled";
1212                         };
1213
1214                         uart3: serial@21ec000 {
1215                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1216                                 reg = <0x021ec000 0x4000>;
1217                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1218                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1219                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1220                                 clock-names = "ipg", "per";
1221                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1222                                 dma-names = "rx", "tx";
1223                                 status = "disabled";
1224                         };
1225
1226                         uart4: serial@21f0000 {
1227                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1228                                 reg = <0x021f0000 0x4000>;
1229                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1230                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1231                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1232                                 clock-names = "ipg", "per";
1233                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1234                                 dma-names = "rx", "tx";
1235                                 status = "disabled";
1236                         };
1237
1238                         uart5: serial@21f4000 {
1239                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1240                                 reg = <0x021f4000 0x4000>;
1241                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1242                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1243                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1244                                 clock-names = "ipg", "per";
1245                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1246                                 dma-names = "rx", "tx";
1247                                 status = "disabled";
1248                         };
1249                 };
1250
1251                 ipu1: ipu@2400000 {
1252                         #address-cells = <1>;
1253                         #size-cells = <0>;
1254                         compatible = "fsl,imx6q-ipu";
1255                         reg = <0x02400000 0x400000>;
1256                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1257                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1258                         clocks = <&clks IMX6QDL_CLK_IPU1>,
1259                                  <&clks IMX6QDL_CLK_IPU1_DI0>,
1260                                  <&clks IMX6QDL_CLK_IPU1_DI1>;
1261                         clock-names = "bus", "di0", "di1";
1262                         resets = <&src 2>;
1263
1264                         ipu1_csi0: port@0 {
1265                                 reg = <0>;
1266
1267                                 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1268                                         remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1269                                 };
1270                         };
1271
1272                         ipu1_csi1: port@1 {
1273                                 reg = <1>;
1274                         };
1275
1276                         ipu1_di0: port@2 {
1277                                 #address-cells = <1>;
1278                                 #size-cells = <0>;
1279                                 reg = <2>;
1280
1281                                 ipu1_di0_disp0: endpoint@0 {
1282                                         reg = <0>;
1283                                 };
1284
1285                                 ipu1_di0_hdmi: endpoint@1 {
1286                                         reg = <1>;
1287                                         remote-endpoint = <&hdmi_mux_0>;
1288                                 };
1289
1290                                 ipu1_di0_mipi: endpoint@2 {
1291                                         reg = <2>;
1292                                         remote-endpoint = <&mipi_mux_0>;
1293                                 };
1294
1295                                 ipu1_di0_lvds0: endpoint@3 {
1296                                         reg = <3>;
1297                                         remote-endpoint = <&lvds0_mux_0>;
1298                                 };
1299
1300                                 ipu1_di0_lvds1: endpoint@4 {
1301                                         reg = <4>;
1302                                         remote-endpoint = <&lvds1_mux_0>;
1303                                 };
1304                         };
1305
1306                         ipu1_di1: port@3 {
1307                                 #address-cells = <1>;
1308                                 #size-cells = <0>;
1309                                 reg = <3>;
1310
1311                                 ipu1_di1_disp1: endpoint@0 {
1312                                         reg = <0>;
1313                                 };
1314
1315                                 ipu1_di1_hdmi: endpoint@1 {
1316                                         reg = <1>;
1317                                         remote-endpoint = <&hdmi_mux_1>;
1318                                 };
1319
1320                                 ipu1_di1_mipi: endpoint@2 {
1321                                         reg = <2>;
1322                                         remote-endpoint = <&mipi_mux_1>;
1323                                 };
1324
1325                                 ipu1_di1_lvds0: endpoint@3 {
1326                                         reg = <3>;
1327                                         remote-endpoint = <&lvds0_mux_1>;
1328                                 };
1329
1330                                 ipu1_di1_lvds1: endpoint@4 {
1331                                         reg = <4>;
1332                                         remote-endpoint = <&lvds1_mux_1>;
1333                                 };
1334                         };
1335                 };
1336         };
1337 };