arch/arm/boot/dts/imx6sl.dtsi

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include "skeleton.dtsi"
  12 #include "imx6sl-pinfunc.h"
  13 #include <dt-bindings/clock/imx6sl-clock.h>
  14
  15 / {
  16         aliases {
  17                 ethernet0 = &fec;
  18                 gpio0 = &gpio1;
  19                 gpio1 = &gpio2;
  20                 gpio2 = &gpio3;
  21                 gpio3 = &gpio4;
  22                 gpio4 = &gpio5;
  23                 serial0 = &uart1;
  24                 serial1 = &uart2;
  25                 serial2 = &uart3;
  26                 serial3 = &uart4;
  27                 serial4 = &uart5;
  28                 spi0 = &ecspi1;
  29                 spi1 = &ecspi2;
  30                 spi2 = &ecspi3;
  31                 spi3 = &ecspi4;
  32                 usbphy0 = &usbphy1;
  33                 usbphy1 = &usbphy2;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         compatible = "arm,cortex-a9";
  42                         device_type = "cpu";
  43                         reg = <0x0>;
  44                         next-level-cache = <&L2>;
  45                         operating-points = <
  46                                 /* kHz    uV */
  47                                 996000  1275000
  48                                 792000  1175000
  49                                 396000  975000
  50                         >;
  51                         fsl,soc-operating-points = <
  52                                 /* ARM kHz      SOC-PU uV */
  53                                 996000          1225000
  54                                 792000          1175000
  55                                 396000          1175000
  56                         >;
  57                         clock-latency = <61036>; /* two CLK32 periods */
  58                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  59                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  60                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  61                         clock-names = "arm", "pll2_pfd2_396m", "step",
  62                                       "pll1_sw", "pll1_sys";
  63                         arm-supply = <&reg_arm>;
  64                         pu-supply = <&reg_pu>;
  65                         soc-supply = <&reg_soc>;
  66                 };
  67         };
  68
  69         intc: interrupt-controller@00a01000 {
  70                 compatible = "arm,cortex-a9-gic";
  71                 #interrupt-cells = <3>;
  72                 interrupt-controller;
  73                 reg = <0x00a01000 0x1000>,
  74                       <0x00a00100 0x100>;
  75                 interrupt-parent = <&intc>;
  76         };
  77
  78         clocks {
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 ckil {
  83                         compatible = "fixed-clock";
  84                         #clock-cells = <0>;
  85                         clock-frequency = <32768>;
  86                 };
  87
  88                 osc {
  89                         compatible = "fixed-clock";
  90                         #clock-cells = <0>;
  91                         clock-frequency = <24000000>;
  92                 };
  93         };
  94
  95         soc {
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 compatible = "simple-bus";
  99                 interrupt-parent = <&gpc>;
 100                 ranges;
 101
 102                 ocram: sram@00900000 {
 103                         compatible = "mmio-sram";
 104                         reg = <0x00900000 0x20000>;
 105                         ranges = <0 0x00900000 0x20000>;
 106                         #address-cells = <1>;
 107                         #size-cells = <1>;
 108                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 109                 };
 110
 111                 L2: l2-cache@00a02000 {
 112                         compatible = "arm,pl310-cache";
 113                         reg = <0x00a02000 0x1000>;
 114                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 115                         cache-unified;
 116                         cache-level = <2>;
 117                         arm,tag-latency = <4 2 3>;
 118                         arm,data-latency = <4 2 3>;
 119                 };
 120
 121                 pmu {
 122                         compatible = "arm,cortex-a9-pmu";
 123                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 124                 };
 125
 126                 aips1: aips-bus@02000000 {
 127                         compatible = "fsl,aips-bus", "simple-bus";
 128                         #address-cells = <1>;
 129                         #size-cells = <1>;
 130                         reg = <0x02000000 0x100000>;
 131                         ranges;
 132
 133                         spba: spba-bus@02000000 {
 134                                 compatible = "fsl,spba-bus", "simple-bus";
 135                                 #address-cells = <1>;
 136                                 #size-cells = <1>;
 137                                 reg = <0x02000000 0x40000>;
 138                                 ranges;
 139
 140                                 spdif: spdif@02004000 {
 141                                         compatible = "fsl,imx6sl-spdif",
 142                                                 "fsl,imx35-spdif";
 143                                         reg = <0x02004000 0x4000>;
 144                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 145                                         dmas = <&sdma 14 18 0>,
 146                                                 <&sdma 15 18 0>;
 147                                         dma-names = "rx", "tx";
 148                                         clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
 149                                                  <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
 150                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
 151                                                  <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
 152                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
 153                                         clock-names = "core", "rxtx0",
 154                                                 "rxtx1", "rxtx2",
 155                                                 "rxtx3", "rxtx4",
 156                                                 "rxtx5", "rxtx6",
 157                                                 "rxtx7", "spba";
 158                                         status = "disabled";
 159                                 };
 160
 161                                 ecspi1: ecspi@02008000 {
 162                                         #address-cells = <1>;
 163                                         #size-cells = <0>;
 164                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 165                                         reg = <0x02008000 0x4000>;
 166                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 167                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 168                                                  <&clks IMX6SL_CLK_ECSPI1>;
 169                                         clock-names = "ipg", "per";
 170                                         status = "disabled";
 171                                 };
 172
 173                                 ecspi2: ecspi@0200c000 {
 174                                         #address-cells = <1>;
 175                                         #size-cells = <0>;
 176                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 177                                         reg = <0x0200c000 0x4000>;
 178                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 179                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 180                                                  <&clks IMX6SL_CLK_ECSPI2>;
 181                                         clock-names = "ipg", "per";
 182                                         status = "disabled";
 183                                 };
 184
 185                                 ecspi3: ecspi@02010000 {
 186                                         #address-cells = <1>;
 187                                         #size-cells = <0>;
 188                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 189                                         reg = <0x02010000 0x4000>;
 190                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 191                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 192                                                  <&clks IMX6SL_CLK_ECSPI3>;
 193                                         clock-names = "ipg", "per";
 194                                         status = "disabled";
 195                                 };
 196
 197                                 ecspi4: ecspi@02014000 {
 198                                         #address-cells = <1>;
 199                                         #size-cells = <0>;
 200                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 201                                         reg = <0x02014000 0x4000>;
 202                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 203                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 204                                                  <&clks IMX6SL_CLK_ECSPI4>;
 205                                         clock-names = "ipg", "per";
 206                                         status = "disabled";
 207                                 };
 208
 209                                 uart5: serial@02018000 {
 210                                         compatible = "fsl,imx6sl-uart",
 211                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 212                                         reg = <0x02018000 0x4000>;
 213                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 214                                         clocks = <&clks IMX6SL_CLK_UART>,
 215                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 216                                         clock-names = "ipg", "per";
 217                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 218                                         dma-names = "rx", "tx";
 219                                         status = "disabled";
 220                                 };
 221
 222                                 uart1: serial@02020000 {
 223                                         compatible = "fsl,imx6sl-uart",
 224                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 225                                         reg = <0x02020000 0x4000>;
 226                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 227                                         clocks = <&clks IMX6SL_CLK_UART>,
 228                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 229                                         clock-names = "ipg", "per";
 230                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 231                                         dma-names = "rx", "tx";
 232                                         status = "disabled";
 233                                 };
 234
 235                                 uart2: serial@02024000 {
 236                                         compatible = "fsl,imx6sl-uart",
 237                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 238                                         reg = <0x02024000 0x4000>;
 239                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 240                                         clocks = <&clks IMX6SL_CLK_UART>,
 241                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 242                                         clock-names = "ipg", "per";
 243                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 244                                         dma-names = "rx", "tx";
 245                                         status = "disabled";
 246                                 };
 247
 248                                 ssi1: ssi@02028000 {
 249                                         #sound-dai-cells = <0>;
 250                                         compatible = "fsl,imx6sl-ssi",
 251                                                         "fsl,imx51-ssi";
 252                                         reg = <0x02028000 0x4000>;
 253                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 254                                         clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
 255                                                  <&clks IMX6SL_CLK_SSI1>;
 256                                         clock-names = "ipg", "baud";
 257                                         dmas = <&sdma 37 1 0>,
 258                                                <&sdma 38 1 0>;
 259                                         dma-names = "rx", "tx";
 260                                         fsl,fifo-depth = <15>;
 261                                         status = "disabled";
 262                                 };
 263
 264                                 ssi2: ssi@0202c000 {
 265                                         #sound-dai-cells = <0>;
 266                                         compatible = "fsl,imx6sl-ssi",
 267                                                         "fsl,imx51-ssi";
 268                                         reg = <0x0202c000 0x4000>;
 269                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 270                                         clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
 271                                                  <&clks IMX6SL_CLK_SSI2>;
 272                                         clock-names = "ipg", "baud";
 273                                         dmas = <&sdma 41 1 0>,
 274                                                <&sdma 42 1 0>;
 275                                         dma-names = "rx", "tx";
 276                                         fsl,fifo-depth = <15>;
 277                                         status = "disabled";
 278                                 };
 279
 280                                 ssi3: ssi@02030000 {
 281                                         #sound-dai-cells = <0>;
 282                                         compatible = "fsl,imx6sl-ssi",
 283                                                         "fsl,imx51-ssi";
 284                                         reg = <0x02030000 0x4000>;
 285                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 286                                         clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
 287                                                  <&clks IMX6SL_CLK_SSI3>;
 288                                         clock-names = "ipg", "baud";
 289                                         dmas = <&sdma 45 1 0>,
 290                                                <&sdma 46 1 0>;
 291                                         dma-names = "rx", "tx";
 292                                         fsl,fifo-depth = <15>;
 293                                         status = "disabled";
 294                                 };
 295
 296                                 uart3: serial@02034000 {
 297                                         compatible = "fsl,imx6sl-uart",
 298                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 299                                         reg = <0x02034000 0x4000>;
 300                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 301                                         clocks = <&clks IMX6SL_CLK_UART>,
 302                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 303                                         clock-names = "ipg", "per";
 304                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 305                                         dma-names = "rx", "tx";
 306                                         status = "disabled";
 307                                 };
 308
 309                                 uart4: serial@02038000 {
 310                                         compatible = "fsl,imx6sl-uart",
 311                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 312                                         reg = <0x02038000 0x4000>;
 313                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 314                                         clocks = <&clks IMX6SL_CLK_UART>,
 315                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 316                                         clock-names = "ipg", "per";
 317                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 318                                         dma-names = "rx", "tx";
 319                                         status = "disabled";
 320                                 };
 321                         };
 322
 323                         pwm1: pwm@02080000 {
 324                                 #pwm-cells = <2>;
 325                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 326                                 reg = <0x02080000 0x4000>;
 327                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 328                                 clocks = <&clks IMX6SL_CLK_PWM1>,
 329                                          <&clks IMX6SL_CLK_PWM1>;
 330                                 clock-names = "ipg", "per";
 331                         };
 332
 333                         pwm2: pwm@02084000 {
 334                                 #pwm-cells = <2>;
 335                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 336                                 reg = <0x02084000 0x4000>;
 337                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 338                                 clocks = <&clks IMX6SL_CLK_PWM2>,
 339                                          <&clks IMX6SL_CLK_PWM2>;
 340                                 clock-names = "ipg", "per";
 341                         };
 342
 343                         pwm3: pwm@02088000 {
 344                                 #pwm-cells = <2>;
 345                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 346                                 reg = <0x02088000 0x4000>;
 347                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 348                                 clocks = <&clks IMX6SL_CLK_PWM3>,
 349                                          <&clks IMX6SL_CLK_PWM3>;
 350                                 clock-names = "ipg", "per";
 351                         };
 352
 353                         pwm4: pwm@0208c000 {
 354                                 #pwm-cells = <2>;
 355                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 356                                 reg = <0x0208c000 0x4000>;
 357                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 358                                 clocks = <&clks IMX6SL_CLK_PWM4>,
 359                                          <&clks IMX6SL_CLK_PWM4>;
 360                                 clock-names = "ipg", "per";
 361                         };
 362
 363                         gpt: gpt@02098000 {
 364                                 compatible = "fsl,imx6sl-gpt";
 365                                 reg = <0x02098000 0x4000>;
 366                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 367                                 clocks = <&clks IMX6SL_CLK_GPT>,
 368                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 369                                 clock-names = "ipg", "per";
 370                         };
 371
 372                         gpio1: gpio@0209c000 {
 373                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 374                                 reg = <0x0209c000 0x4000>;
 375                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 376                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 377                                 gpio-controller;
 378                                 #gpio-cells = <2>;
 379                                 interrupt-controller;
 380                                 #interrupt-cells = <2>;
 381                                 gpio-ranges = <&iomuxc  0 22 1>, <&iomuxc  1 20 2>,
 382                                               <&iomuxc  3 23 1>, <&iomuxc  4 25 1>,
 383                                               <&iomuxc  5 24 1>, <&iomuxc  6 19 1>,
 384                                               <&iomuxc  7 36 2>, <&iomuxc  9 44 8>,
 385                                               <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
 386                                               <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
 387                         };
 388
 389                         gpio2: gpio@020a0000 {
 390                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 391                                 reg = <0x020a0000 0x4000>;
 392                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 393                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 394                                 gpio-controller;
 395                                 #gpio-cells = <2>;
 396                                 interrupt-controller;
 397                                 #interrupt-cells = <2>;
 398                                 gpio-ranges = <&iomuxc  0  53 3>, <&iomuxc  3  72 2>,
 399                                               <&iomuxc  5  34 2>, <&iomuxc  7  57 4>,
 400                                               <&iomuxc 11  56 1>, <&iomuxc 12  61 3>,
 401                                               <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
 402                                               <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
 403                                               <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
 404                                               <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
 405                         };
 406
 407                         gpio3: gpio@020a4000 {
 408                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 409                                 reg = <0x020a4000 0x4000>;
 410                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 411                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 412                                 gpio-controller;
 413                                 #gpio-cells = <2>;
 414                                 interrupt-controller;
 415                                 #interrupt-cells = <2>;
 416                                 gpio-ranges = <&iomuxc  0 112 8>, <&iomuxc  8 121 4>,
 417                                               <&iomuxc 12  97 4>, <&iomuxc 16 166 3>,
 418                                               <&iomuxc 19  85 2>, <&iomuxc 21 137 2>,
 419                                               <&iomuxc 23 136 1>, <&iomuxc 24  91 1>,
 420                                               <&iomuxc 25  99 1>, <&iomuxc 26  92 1>,
 421                                               <&iomuxc 27 100 1>, <&iomuxc 28  93 1>,
 422                                               <&iomuxc 29 101 1>, <&iomuxc 30  94 1>,
 423                                               <&iomuxc 31 102 1>;
 424                         };
 425
 426                         gpio4: gpio@020a8000 {
 427                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 428                                 reg = <0x020a8000 0x4000>;
 429                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 430                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 431                                 gpio-controller;
 432                                 #gpio-cells = <2>;
 433                                 interrupt-controller;
 434                                 #interrupt-cells = <2>;
 435                                 gpio-ranges = <&iomuxc  0  95 1>, <&iomuxc  1 103 1>,
 436                                               <&iomuxc  2  96 1>, <&iomuxc  3 104 1>,
 437                                               <&iomuxc  4  97 1>, <&iomuxc  5 105 1>,
 438                                               <&iomuxc  6  98 1>, <&iomuxc  7 106 1>,
 439                                               <&iomuxc  8  28 1>, <&iomuxc  9  27 1>,
 440                                               <&iomuxc 10  26 1>, <&iomuxc 11  29 1>,
 441                                               <&iomuxc 12  32 1>, <&iomuxc 13  31 1>,
 442                                               <&iomuxc 14  30 1>, <&iomuxc 15  33 1>,
 443                                               <&iomuxc 16  84 1>, <&iomuxc 17  79 2>,
 444                                               <&iomuxc 19  78 1>, <&iomuxc 20  76 1>,
 445                                               <&iomuxc 21  81 2>, <&iomuxc 23  75 1>,
 446                                               <&iomuxc 24  83 1>, <&iomuxc 25  74 1>,
 447                                               <&iomuxc 26  77 1>, <&iomuxc 27 159 1>,
 448                                               <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
 449                                               <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
 450                         };
 451
 452                         gpio5: gpio@020ac000 {
 453                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 454                                 reg = <0x020ac000 0x4000>;
 455                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 456                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 457                                 gpio-controller;
 458                                 #gpio-cells = <2>;
 459                                 interrupt-controller;
 460                                 #interrupt-cells = <2>;
 461                                 gpio-ranges = <&iomuxc  0 158 1>, <&iomuxc  1 151 1>,
 462                                               <&iomuxc  2 155 1>, <&iomuxc  3 153 1>,
 463                                               <&iomuxc  4 150 1>, <&iomuxc  5 149 1>,
 464                                               <&iomuxc  6 144 1>, <&iomuxc  7 147 1>,
 465                                               <&iomuxc  8 142 1>, <&iomuxc  9 146 1>,
 466                                               <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
 467                                               <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
 468                                               <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
 469                                               <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
 470                                               <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
 471                                               <&iomuxc 21 161 1>;
 472                         };
 473
 474                         kpp: kpp@020b8000 {
 475                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 476                                 reg = <0x020b8000 0x4000>;
 477                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 478                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 479                                 status = "disabled";
 480                         };
 481
 482                         wdog1: wdog@020bc000 {
 483                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 484                                 reg = <0x020bc000 0x4000>;
 485                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 486                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 487                         };
 488
 489                         wdog2: wdog@020c0000 {
 490                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 491                                 reg = <0x020c0000 0x4000>;
 492                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 493                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 494                                 status = "disabled";
 495                         };
 496
 497                         clks: ccm@020c4000 {
 498                                 compatible = "fsl,imx6sl-ccm";
 499                                 reg = <0x020c4000 0x4000>;
 500                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 501                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 502                                 #clock-cells = <1>;
 503                         };
 504
 505                         anatop: anatop@020c8000 {
 506                                 compatible = "fsl,imx6sl-anatop",
 507                                              "fsl,imx6q-anatop",
 508                                              "syscon", "simple-bus";
 509                                 reg = <0x020c8000 0x1000>;
 510                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 511                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 512                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 513
 514                                 regulator-1p1 {
 515                                         compatible = "fsl,anatop-regulator";
 516                                         regulator-name = "vdd1p1";
 517                                         regulator-min-microvolt = <800000>;
 518                                         regulator-max-microvolt = <1375000>;
 519                                         regulator-always-on;
 520                                         anatop-reg-offset = <0x110>;
 521                                         anatop-vol-bit-shift = <8>;
 522                                         anatop-vol-bit-width = <5>;
 523                                         anatop-min-bit-val = <4>;
 524                                         anatop-min-voltage = <800000>;
 525                                         anatop-max-voltage = <1375000>;
 526                                 };
 527
 528                                 regulator-3p0 {
 529                                         compatible = "fsl,anatop-regulator";
 530                                         regulator-name = "vdd3p0";
 531                                         regulator-min-microvolt = <2800000>;
 532                                         regulator-max-microvolt = <3150000>;
 533                                         regulator-always-on;
 534                                         anatop-reg-offset = <0x120>;
 535                                         anatop-vol-bit-shift = <8>;
 536                                         anatop-vol-bit-width = <5>;
 537                                         anatop-min-bit-val = <0>;
 538                                         anatop-min-voltage = <2625000>;
 539                                         anatop-max-voltage = <3400000>;
 540                                 };
 541
 542                                 regulator-2p5 {
 543                                         compatible = "fsl,anatop-regulator";
 544                                         regulator-name = "vdd2p5";
 545                                         regulator-min-microvolt = <2100000>;
 546                                         regulator-max-microvolt = <2850000>;
 547                                         regulator-always-on;
 548                                         anatop-reg-offset = <0x130>;
 549                                         anatop-vol-bit-shift = <8>;
 550                                         anatop-vol-bit-width = <5>;
 551                                         anatop-min-bit-val = <0>;
 552                                         anatop-min-voltage = <2100000>;
 553                                         anatop-max-voltage = <2850000>;
 554                                 };
 555
 556                                 reg_arm: regulator-vddcore {
 557                                         compatible = "fsl,anatop-regulator";
 558                                         regulator-name = "vddarm";
 559                                         regulator-min-microvolt = <725000>;
 560                                         regulator-max-microvolt = <1450000>;
 561                                         regulator-always-on;
 562                                         anatop-reg-offset = <0x140>;
 563                                         anatop-vol-bit-shift = <0>;
 564                                         anatop-vol-bit-width = <5>;
 565                                         anatop-delay-reg-offset = <0x170>;
 566                                         anatop-delay-bit-shift = <24>;
 567                                         anatop-delay-bit-width = <2>;
 568                                         anatop-min-bit-val = <1>;
 569                                         anatop-min-voltage = <725000>;
 570                                         anatop-max-voltage = <1450000>;
 571                                 };
 572
 573                                 reg_pu: regulator-vddpu {
 574                                         compatible = "fsl,anatop-regulator";
 575                                         regulator-name = "vddpu";
 576                                         regulator-min-microvolt = <725000>;
 577                                         regulator-max-microvolt = <1450000>;
 578                                         regulator-always-on;
 579                                         anatop-reg-offset = <0x140>;
 580                                         anatop-vol-bit-shift = <9>;
 581                                         anatop-vol-bit-width = <5>;
 582                                         anatop-delay-reg-offset = <0x170>;
 583                                         anatop-delay-bit-shift = <26>;
 584                                         anatop-delay-bit-width = <2>;
 585                                         anatop-min-bit-val = <1>;
 586                                         anatop-min-voltage = <725000>;
 587                                         anatop-max-voltage = <1450000>;
 588                                 };
 589
 590                                 reg_soc: regulator-vddsoc {
 591                                         compatible = "fsl,anatop-regulator";
 592                                         regulator-name = "vddsoc";
 593                                         regulator-min-microvolt = <725000>;
 594                                         regulator-max-microvolt = <1450000>;
 595                                         regulator-always-on;
 596                                         anatop-reg-offset = <0x140>;
 597                                         anatop-vol-bit-shift = <18>;
 598                                         anatop-vol-bit-width = <5>;
 599                                         anatop-delay-reg-offset = <0x170>;
 600                                         anatop-delay-bit-shift = <28>;
 601                                         anatop-delay-bit-width = <2>;
 602                                         anatop-min-bit-val = <1>;
 603                                         anatop-min-voltage = <725000>;
 604                                         anatop-max-voltage = <1450000>;
 605                                 };
 606                         };
 607
 608                         tempmon: tempmon {
 609                                 compatible = "fsl,imx6q-tempmon";
 610                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 611                                 fsl,tempmon = <&anatop>;
 612                                 fsl,tempmon-data = <&ocotp>;
 613                                 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
 614                         };
 615
 616                         usbphy1: usbphy@020c9000 {
 617                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 618                                 reg = <0x020c9000 0x1000>;
 619                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 620                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 621                                 fsl,anatop = <&anatop>;
 622                         };
 623
 624                         usbphy2: usbphy@020ca000 {
 625                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 626                                 reg = <0x020ca000 0x1000>;
 627                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 628                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 629                                 fsl,anatop = <&anatop>;
 630                         };
 631
 632                         snvs: snvs@020cc000 {
 633                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 634                                 reg = <0x020cc000 0x4000>;
 635
 636                                 snvs_rtc: snvs-rtc-lp {
 637                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 638                                         regmap = <&snvs>;
 639                                         offset = <0x34>;
 640                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 641                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 642                                 };
 643
 644                                 snvs_poweroff: snvs-poweroff {
 645                                         compatible = "syscon-poweroff";
 646                                         regmap = <&snvs>;
 647                                         offset = <0x38>;
 648                                         mask = <0x60>;
 649                                         status = "disabled";
 650                                 };
 651                         };
 652
 653                         epit1: epit@020d0000 {
 654                                 reg = <0x020d0000 0x4000>;
 655                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 656                         };
 657
 658                         epit2: epit@020d4000 {
 659                                 reg = <0x020d4000 0x4000>;
 660                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 661                         };
 662
 663                         src: src@020d8000 {
 664                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 665                                 reg = <0x020d8000 0x4000>;
 666                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 667                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 668                                 #reset-cells = <1>;
 669                         };
 670
 671                         gpc: gpc@020dc000 {
 672                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 673                                 reg = <0x020dc000 0x4000>;
 674                                 interrupt-controller;
 675                                 #interrupt-cells = <3>;
 676                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 677                                 interrupt-parent = <&intc>;
 678                                 pu-supply = <&reg_pu>;
 679                                 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
 680                                          <&clks IMX6SL_CLK_GPU2D_PODF>;
 681                                 #power-domain-cells = <1>;
 682                         };
 683
 684                         gpr: iomuxc-gpr@020e0000 {
 685                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 686                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 687                                 reg = <0x020e0000 0x38>;
 688                         };
 689
 690                         iomuxc: iomuxc@020e0000 {
 691                                 compatible = "fsl,imx6sl-iomuxc";
 692                                 reg = <0x020e0000 0x4000>;
 693                         };
 694
 695                         csi: csi@020e4000 {
 696                                 reg = <0x020e4000 0x4000>;
 697                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 698                         };
 699
 700                         spdc: spdc@020e8000 {
 701                                 reg = <0x020e8000 0x4000>;
 702                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 703                         };
 704
 705                         sdma: sdma@020ec000 {
 706                                 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
 707                                 reg = <0x020ec000 0x4000>;
 708                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 709                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 710                                          <&clks IMX6SL_CLK_AHB>;
 711                                 clock-names = "ipg", "ahb";
 712                                 #dma-cells = <3>;
 713                                 /* imx6sl reuses imx6q sdma firmware */
 714                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 715                         };
 716
 717                         pxp: pxp@020f0000 {
 718                                 reg = <0x020f0000 0x4000>;
 719                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 720                         };
 721
 722                         epdc: epdc@020f4000 {
 723                                 reg = <0x020f4000 0x4000>;
 724                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 725                         };
 726
 727                         lcdif: lcdif@020f8000 {
 728                                 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
 729                                 reg = <0x020f8000 0x4000>;
 730                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 731                                 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
 732                                          <&clks IMX6SL_CLK_LCDIF_AXI>,
 733                                          <&clks IMX6SL_CLK_DUMMY>;
 734                                 clock-names = "pix", "axi", "disp_axi";
 735                                 status = "disabled";
 736                         };
 737
 738                         dcp: dcp@020fc000 {
 739                                 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
 740                                 reg = <0x020fc000 0x4000>;
 741                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
 742                                              <0 100 IRQ_TYPE_LEVEL_HIGH>,
 743                                              <0 101 IRQ_TYPE_LEVEL_HIGH>;
 744                         };
 745                 };
 746
 747                 aips2: aips-bus@02100000 {
 748                         compatible = "fsl,aips-bus", "simple-bus";
 749                         #address-cells = <1>;
 750                         #size-cells = <1>;
 751                         reg = <0x02100000 0x100000>;
 752                         ranges;
 753
 754                         usbotg1: usb@02184000 {
 755                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 756                                 reg = <0x02184000 0x200>;
 757                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 758                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 759                                 fsl,usbphy = <&usbphy1>;
 760                                 fsl,usbmisc = <&usbmisc 0>;
 761                                 ahb-burst-config = <0x0>;
 762                                 tx-burst-size-dword = <0x10>;
 763                                 rx-burst-size-dword = <0x10>;
 764                                 status = "disabled";
 765                         };
 766
 767                         usbotg2: usb@02184200 {
 768                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 769                                 reg = <0x02184200 0x200>;
 770                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 771                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 772                                 fsl,usbphy = <&usbphy2>;
 773                                 fsl,usbmisc = <&usbmisc 1>;
 774                                 ahb-burst-config = <0x0>;
 775                                 tx-burst-size-dword = <0x10>;
 776                                 rx-burst-size-dword = <0x10>;
 777                                 status = "disabled";
 778                         };
 779
 780                         usbh: usb@02184400 {
 781                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 782                                 reg = <0x02184400 0x200>;
 783                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 784                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 785                                 fsl,usbmisc = <&usbmisc 2>;
 786                                 dr_mode = "host";
 787                                 ahb-burst-config = <0x0>;
 788                                 tx-burst-size-dword = <0x10>;
 789                                 rx-burst-size-dword = <0x10>;
 790                                 status = "disabled";
 791                         };
 792
 793                         usbmisc: usbmisc@02184800 {
 794                                 #index-cells = <1>;
 795                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 796                                 reg = <0x02184800 0x200>;
 797                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 798                         };
 799
 800                         fec: ethernet@02188000 {
 801                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 802                                 reg = <0x02188000 0x4000>;
 803                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 804                                 clocks = <&clks IMX6SL_CLK_ENET>,
 805                                          <&clks IMX6SL_CLK_ENET_REF>;
 806                                 clock-names = "ipg", "ahb";
 807                                 status = "disabled";
 808                         };
 809
 810                         usdhc1: usdhc@02190000 {
 811                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 812                                 reg = <0x02190000 0x4000>;
 813                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 814                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 815                                          <&clks IMX6SL_CLK_USDHC1>,
 816                                          <&clks IMX6SL_CLK_USDHC1>;
 817                                 clock-names = "ipg", "ahb", "per";
 818                                 bus-width = <4>;
 819                                 status = "disabled";
 820                         };
 821
 822                         usdhc2: usdhc@02194000 {
 823                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 824                                 reg = <0x02194000 0x4000>;
 825                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 826                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 827                                          <&clks IMX6SL_CLK_USDHC2>,
 828                                          <&clks IMX6SL_CLK_USDHC2>;
 829                                 clock-names = "ipg", "ahb", "per";
 830                                 bus-width = <4>;
 831                                 status = "disabled";
 832                         };
 833
 834                         usdhc3: usdhc@02198000 {
 835                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 836                                 reg = <0x02198000 0x4000>;
 837                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 838                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 839                                          <&clks IMX6SL_CLK_USDHC3>,
 840                                          <&clks IMX6SL_CLK_USDHC3>;
 841                                 clock-names = "ipg", "ahb", "per";
 842                                 bus-width = <4>;
 843                                 status = "disabled";
 844                         };
 845
 846                         usdhc4: usdhc@0219c000 {
 847                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 848                                 reg = <0x0219c000 0x4000>;
 849                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 850                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 851                                          <&clks IMX6SL_CLK_USDHC4>,
 852                                          <&clks IMX6SL_CLK_USDHC4>;
 853                                 clock-names = "ipg", "ahb", "per";
 854                                 bus-width = <4>;
 855                                 status = "disabled";
 856                         };
 857
 858                         i2c1: i2c@021a0000 {
 859                                 #address-cells = <1>;
 860                                 #size-cells = <0>;
 861                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 862                                 reg = <0x021a0000 0x4000>;
 863                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 864                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 865                                 status = "disabled";
 866                         };
 867
 868                         i2c2: i2c@021a4000 {
 869                                 #address-cells = <1>;
 870                                 #size-cells = <0>;
 871                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 872                                 reg = <0x021a4000 0x4000>;
 873                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 874                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 875                                 status = "disabled";
 876                         };
 877
 878                         i2c3: i2c@021a8000 {
 879                                 #address-cells = <1>;
 880                                 #size-cells = <0>;
 881                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 882                                 reg = <0x021a8000 0x4000>;
 883                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 884                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 885                                 status = "disabled";
 886                         };
 887
 888                         mmdc: mmdc@021b0000 {
 889                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 890                                 reg = <0x021b0000 0x4000>;
 891                         };
 892
 893                         rngb: rngb@021b4000 {
 894                                 reg = <0x021b4000 0x4000>;
 895                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 896                         };
 897
 898                         weim: weim@021b8000 {
 899                                 reg = <0x021b8000 0x4000>;
 900                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 901                         };
 902
 903                         ocotp: ocotp@021bc000 {
 904                                 compatible = "fsl,imx6sl-ocotp", "syscon";
 905                                 reg = <0x021bc000 0x4000>;
 906                                 clocks = <&clks IMX6SL_CLK_OCOTP>;
 907                         };
 908
 909                         audmux: audmux@021d8000 {
 910                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 911                                 reg = <0x021d8000 0x4000>;
 912                                 status = "disabled";
 913                         };
 914                 };
 915         };
 916 };