GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / imx6sx.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2014 Freescale Semiconductor, Inc.
4
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
10
11 / {
12         #address-cells = <1>;
13         #size-cells = <1>;
14         /*
15          * The decompressor and also some bootloaders rely on a
16          * pre-existing /chosen node to be available to insert the
17          * command line and merge other ATAGS info.
18          */
19         chosen {};
20
21         aliases {
22                 can0 = &flexcan1;
23                 can1 = &flexcan2;
24                 ethernet0 = &fec1;
25                 ethernet1 = &fec2;
26                 gpio0 = &gpio1;
27                 gpio1 = &gpio2;
28                 gpio2 = &gpio3;
29                 gpio3 = &gpio4;
30                 gpio4 = &gpio5;
31                 gpio5 = &gpio6;
32                 gpio6 = &gpio7;
33                 i2c0 = &i2c1;
34                 i2c1 = &i2c2;
35                 i2c2 = &i2c3;
36                 i2c3 = &i2c4;
37                 mmc0 = &usdhc1;
38                 mmc1 = &usdhc2;
39                 mmc2 = &usdhc3;
40                 mmc3 = &usdhc4;
41                 serial0 = &uart1;
42                 serial1 = &uart2;
43                 serial2 = &uart3;
44                 serial3 = &uart4;
45                 serial4 = &uart5;
46                 serial5 = &uart6;
47                 spi0 = &ecspi1;
48                 spi1 = &ecspi2;
49                 spi2 = &ecspi3;
50                 spi3 = &ecspi4;
51                 spi4 = &ecspi5;
52                 usbphy0 = &usbphy1;
53                 usbphy1 = &usbphy2;
54         };
55
56         cpus {
57                 #address-cells = <1>;
58                 #size-cells = <0>;
59
60                 cpu0: cpu@0 {
61                         compatible = "arm,cortex-a9";
62                         device_type = "cpu";
63                         reg = <0>;
64                         next-level-cache = <&L2>;
65                         operating-points = <
66                                 /* kHz    uV */
67                                 996000  1250000
68                                 792000  1175000
69                                 396000  1075000
70                                 198000  975000
71                         >;
72                         fsl,soc-operating-points = <
73                                 /* ARM kHz  SOC uV */
74                                 996000      1175000
75                                 792000      1175000
76                                 396000      1175000
77                                 198000      1175000
78                         >;
79                         clock-latency = <61036>; /* two CLK32 periods */
80                         #cooling-cells = <2>;
81                         clocks = <&clks IMX6SX_CLK_ARM>,
82                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
83                                  <&clks IMX6SX_CLK_STEP>,
84                                  <&clks IMX6SX_CLK_PLL1_SW>,
85                                  <&clks IMX6SX_CLK_PLL1_SYS>;
86                         clock-names = "arm", "pll2_pfd2_396m", "step",
87                                       "pll1_sw", "pll1_sys";
88                         arm-supply = <&reg_arm>;
89                         soc-supply = <&reg_soc>;
90                 };
91         };
92
93         intc: interrupt-controller@a01000 {
94                 compatible = "arm,cortex-a9-gic";
95                 #interrupt-cells = <3>;
96                 interrupt-controller;
97                 reg = <0x00a01000 0x1000>,
98                       <0x00a00100 0x100>;
99                 interrupt-parent = <&intc>;
100         };
101
102         ckil: clock-ckil {
103                 compatible = "fixed-clock";
104                 #clock-cells = <0>;
105                 clock-frequency = <32768>;
106                 clock-output-names = "ckil";
107         };
108
109         osc: clock-osc {
110                 compatible = "fixed-clock";
111                 #clock-cells = <0>;
112                 clock-frequency = <24000000>;
113                 clock-output-names = "osc";
114         };
115
116         ipp_di0: clock-ipp-di0 {
117                 compatible = "fixed-clock";
118                 #clock-cells = <0>;
119                 clock-frequency = <0>;
120                 clock-output-names = "ipp_di0";
121         };
122
123         ipp_di1: clock-ipp-di1 {
124                 compatible = "fixed-clock";
125                 #clock-cells = <0>;
126                 clock-frequency = <0>;
127                 clock-output-names = "ipp_di1";
128         };
129
130         anaclk1: clock-anaclk1 {
131                 compatible = "fixed-clock";
132                 #clock-cells = <0>;
133                 clock-frequency = <0>;
134                 clock-output-names = "anaclk1";
135         };
136
137         anaclk2: clock-anaclk2 {
138                 compatible = "fixed-clock";
139                 #clock-cells = <0>;
140                 clock-frequency = <0>;
141                 clock-output-names = "anaclk2";
142         };
143
144         tempmon: tempmon {
145                 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
146                 interrupt-parent = <&gpc>;
147                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
148                 fsl,tempmon = <&anatop>;
149                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
150                 nvmem-cell-names = "calib", "temp_grade";
151                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
152         };
153
154         pmu {
155                 compatible = "arm,cortex-a9-pmu";
156                 interrupt-parent = <&gpc>;
157                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
158         };
159
160         soc {
161                 #address-cells = <1>;
162                 #size-cells = <1>;
163                 compatible = "simple-bus";
164                 interrupt-parent = <&gpc>;
165                 ranges;
166
167                 ocram_s: sram@8f8000 {
168                         compatible = "mmio-sram";
169                         reg = <0x008f8000 0x4000>;
170                         ranges = <0 0x008f8000 0x4000>;
171                         #address-cells = <1>;
172                         #size-cells = <1>;
173                         clocks = <&clks IMX6SX_CLK_OCRAM_S>;
174                 };
175
176                 ocram: sram@900000 {
177                         compatible = "mmio-sram";
178                         reg = <0x00900000 0x20000>;
179                         ranges = <0 0x00900000 0x20000>;
180                         #address-cells = <1>;
181                         #size-cells = <1>;
182                         clocks = <&clks IMX6SX_CLK_OCRAM>;
183                 };
184
185                 L2: l2-cache@a02000 {
186                         compatible = "arm,pl310-cache";
187                         reg = <0x00a02000 0x1000>;
188                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
189                         cache-unified;
190                         cache-level = <2>;
191                         arm,tag-latency = <4 2 3>;
192                         arm,data-latency = <4 2 3>;
193                 };
194
195                 gpu: gpu@1800000 {
196                         compatible = "vivante,gc";
197                         reg = <0x01800000 0x4000>;
198                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
199                         clocks = <&clks IMX6SX_CLK_GPU>,
200                                  <&clks IMX6SX_CLK_GPU>,
201                                  <&clks IMX6SX_CLK_GPU>;
202                         clock-names = "bus", "core", "shader";
203                         power-domains = <&pd_pu>;
204                 };
205
206                 dma_apbh: dma-apbh@1804000 {
207                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
208                         reg = <0x01804000 0x2000>;
209                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
210                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
211                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
212                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
213                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
214                         #dma-cells = <1>;
215                         dma-channels = <4>;
216                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
217                 };
218
219                 gpmi: gpmi-nand@1806000{
220                         compatible = "fsl,imx6sx-gpmi-nand";
221                         #address-cells = <1>;
222                         #size-cells = <1>;
223                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
224                         reg-names = "gpmi-nand", "bch";
225                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
226                         interrupt-names = "bch";
227                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
228                                  <&clks IMX6SX_CLK_GPMI_APB>,
229                                  <&clks IMX6SX_CLK_GPMI_BCH>,
230                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
231                                  <&clks IMX6SX_CLK_PER1_BCH>;
232                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
233                                       "gpmi_bch_apb", "per1_bch";
234                         dmas = <&dma_apbh 0>;
235                         dma-names = "rx-tx";
236                         status = "disabled";
237                 };
238
239                 aips1: aips-bus@2000000 {
240                         compatible = "fsl,aips-bus", "simple-bus";
241                         #address-cells = <1>;
242                         #size-cells = <1>;
243                         reg = <0x02000000 0x100000>;
244                         ranges;
245
246                         spba-bus@2000000 {
247                                 compatible = "fsl,spba-bus", "simple-bus";
248                                 #address-cells = <1>;
249                                 #size-cells = <1>;
250                                 reg = <0x02000000 0x40000>;
251                                 ranges;
252
253                                 spdif: spdif@2004000 {
254                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
255                                         reg = <0x02004000 0x4000>;
256                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
257                                         dmas = <&sdma 14 18 0>,
258                                                <&sdma 15 18 0>;
259                                         dma-names = "rx", "tx";
260                                         clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
261                                                  <&clks IMX6SX_CLK_OSC>,
262                                                  <&clks IMX6SX_CLK_SPDIF>,
263                                                  <&clks 0>, <&clks 0>, <&clks 0>,
264                                                  <&clks IMX6SX_CLK_IPG>,
265                                                  <&clks 0>, <&clks 0>,
266                                                  <&clks IMX6SX_CLK_SPBA>;
267                                         clock-names = "core", "rxtx0",
268                                                       "rxtx1", "rxtx2",
269                                                       "rxtx3", "rxtx4",
270                                                       "rxtx5", "rxtx6",
271                                                       "rxtx7", "spba";
272                                         status = "disabled";
273                                 };
274
275                                 ecspi1: ecspi@2008000 {
276                                         #address-cells = <1>;
277                                         #size-cells = <0>;
278                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
279                                         reg = <0x02008000 0x4000>;
280                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
281                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
282                                                  <&clks IMX6SX_CLK_ECSPI1>;
283                                         clock-names = "ipg", "per";
284                                         status = "disabled";
285                                 };
286
287                                 ecspi2: ecspi@200c000 {
288                                         #address-cells = <1>;
289                                         #size-cells = <0>;
290                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
291                                         reg = <0x0200c000 0x4000>;
292                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
293                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
294                                                  <&clks IMX6SX_CLK_ECSPI2>;
295                                         clock-names = "ipg", "per";
296                                         status = "disabled";
297                                 };
298
299                                 ecspi3: ecspi@2010000 {
300                                         #address-cells = <1>;
301                                         #size-cells = <0>;
302                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
303                                         reg = <0x02010000 0x4000>;
304                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
305                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
306                                                  <&clks IMX6SX_CLK_ECSPI3>;
307                                         clock-names = "ipg", "per";
308                                         status = "disabled";
309                                 };
310
311                                 ecspi4: ecspi@2014000 {
312                                         #address-cells = <1>;
313                                         #size-cells = <0>;
314                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
315                                         reg = <0x02014000 0x4000>;
316                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
317                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
318                                                  <&clks IMX6SX_CLK_ECSPI4>;
319                                         clock-names = "ipg", "per";
320                                         status = "disabled";
321                                 };
322
323                                 uart1: serial@2020000 {
324                                         compatible = "fsl,imx6sx-uart",
325                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
326                                         reg = <0x02020000 0x4000>;
327                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
328                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
329                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
330                                         clock-names = "ipg", "per";
331                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
332                                         dma-names = "rx", "tx";
333                                         status = "disabled";
334                                 };
335
336                                 esai: esai@2024000 {
337                                         reg = <0x02024000 0x4000>;
338                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
339                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
340                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
341                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
342                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
343                                                  <&clks IMX6SX_CLK_SPBA>;
344                                         clock-names = "core", "mem", "extal",
345                                                       "fsys", "spba";
346                                         status = "disabled";
347                                 };
348
349                                 ssi1: ssi@2028000 {
350                                         #sound-dai-cells = <0>;
351                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
352                                         reg = <0x02028000 0x4000>;
353                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
354                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
355                                                  <&clks IMX6SX_CLK_SSI1>;
356                                         clock-names = "ipg", "baud";
357                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
358                                         dma-names = "rx", "tx";
359                                         fsl,fifo-depth = <15>;
360                                         status = "disabled";
361                                 };
362
363                                 ssi2: ssi@202c000 {
364                                         #sound-dai-cells = <0>;
365                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
366                                         reg = <0x0202c000 0x4000>;
367                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
368                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
369                                                  <&clks IMX6SX_CLK_SSI2>;
370                                         clock-names = "ipg", "baud";
371                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
372                                         dma-names = "rx", "tx";
373                                         fsl,fifo-depth = <15>;
374                                         status = "disabled";
375                                 };
376
377                                 ssi3: ssi@2030000 {
378                                         #sound-dai-cells = <0>;
379                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
380                                         reg = <0x02030000 0x4000>;
381                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
382                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
383                                                  <&clks IMX6SX_CLK_SSI3>;
384                                         clock-names = "ipg", "baud";
385                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
386                                         dma-names = "rx", "tx";
387                                         fsl,fifo-depth = <15>;
388                                         status = "disabled";
389                                 };
390
391                                 asrc: asrc@2034000 {
392                                         reg = <0x02034000 0x4000>;
393                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
394                                         clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
395                                                  <&clks IMX6SX_CLK_ASRC_IPG>,
396                                                  <&clks IMX6SX_CLK_SPDIF>,
397                                                  <&clks IMX6SX_CLK_SPBA>;
398                                         clock-names = "mem", "ipg", "asrck", "spba";
399                                         dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
400                                                <&sdma 19 20 1>, <&sdma 20 20 1>,
401                                                <&sdma 21 20 1>, <&sdma 22 20 1>;
402                                         dma-names = "rxa", "rxb", "rxc",
403                                                     "txa", "txb", "txc";
404                                         status = "okay";
405                                 };
406                         };
407
408                         pwm1: pwm@2080000 {
409                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
410                                 reg = <0x02080000 0x4000>;
411                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
412                                 clocks = <&clks IMX6SX_CLK_PWM1>,
413                                          <&clks IMX6SX_CLK_PWM1>;
414                                 clock-names = "ipg", "per";
415                                 #pwm-cells = <2>;
416                         };
417
418                         pwm2: pwm@2084000 {
419                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
420                                 reg = <0x02084000 0x4000>;
421                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
422                                 clocks = <&clks IMX6SX_CLK_PWM2>,
423                                          <&clks IMX6SX_CLK_PWM2>;
424                                 clock-names = "ipg", "per";
425                                 #pwm-cells = <2>;
426                         };
427
428                         pwm3: pwm@2088000 {
429                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
430                                 reg = <0x02088000 0x4000>;
431                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
432                                 clocks = <&clks IMX6SX_CLK_PWM3>,
433                                          <&clks IMX6SX_CLK_PWM3>;
434                                 clock-names = "ipg", "per";
435                                 #pwm-cells = <2>;
436                         };
437
438                         pwm4: pwm@208c000 {
439                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
440                                 reg = <0x0208c000 0x4000>;
441                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
442                                 clocks = <&clks IMX6SX_CLK_PWM4>,
443                                          <&clks IMX6SX_CLK_PWM4>;
444                                 clock-names = "ipg", "per";
445                                 #pwm-cells = <2>;
446                         };
447
448                         flexcan1: can@2090000 {
449                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
450                                 reg = <0x02090000 0x4000>;
451                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
452                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
453                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
454                                 clock-names = "ipg", "per";
455                                 status = "disabled";
456                         };
457
458                         flexcan2: can@2094000 {
459                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
460                                 reg = <0x02094000 0x4000>;
461                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
462                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
463                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
464                                 clock-names = "ipg", "per";
465                                 status = "disabled";
466                         };
467
468                         gpt: gpt@2098000 {
469                                 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
470                                 reg = <0x02098000 0x4000>;
471                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
472                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
473                                          <&clks IMX6SX_CLK_GPT_3M>;
474                                 clock-names = "ipg", "per";
475                         };
476
477                         gpio1: gpio@209c000 {
478                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
479                                 reg = <0x0209c000 0x4000>;
480                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
481                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
482                                 gpio-controller;
483                                 #gpio-cells = <2>;
484                                 interrupt-controller;
485                                 #interrupt-cells = <2>;
486                                 gpio-ranges = <&iomuxc 0 5 26>;
487                         };
488
489                         gpio2: gpio@20a0000 {
490                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
491                                 reg = <0x020a0000 0x4000>;
492                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
493                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
494                                 gpio-controller;
495                                 #gpio-cells = <2>;
496                                 interrupt-controller;
497                                 #interrupt-cells = <2>;
498                                 gpio-ranges = <&iomuxc 0 31 20>;
499                         };
500
501                         gpio3: gpio@20a4000 {
502                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
503                                 reg = <0x020a4000 0x4000>;
504                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
505                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
506                                 gpio-controller;
507                                 #gpio-cells = <2>;
508                                 interrupt-controller;
509                                 #interrupt-cells = <2>;
510                                 gpio-ranges = <&iomuxc 0 51 29>;
511                         };
512
513                         gpio4: gpio@20a8000 {
514                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
515                                 reg = <0x020a8000 0x4000>;
516                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
517                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
518                                 gpio-controller;
519                                 #gpio-cells = <2>;
520                                 interrupt-controller;
521                                 #interrupt-cells = <2>;
522                                 gpio-ranges = <&iomuxc 0 80 32>;
523                         };
524
525                         gpio5: gpio@20ac000 {
526                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
527                                 reg = <0x020ac000 0x4000>;
528                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
529                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
530                                 gpio-controller;
531                                 #gpio-cells = <2>;
532                                 interrupt-controller;
533                                 #interrupt-cells = <2>;
534                                 gpio-ranges = <&iomuxc 0 112 24>;
535                         };
536
537                         gpio6: gpio@20b0000 {
538                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
539                                 reg = <0x020b0000 0x4000>;
540                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
541                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
542                                 gpio-controller;
543                                 #gpio-cells = <2>;
544                                 interrupt-controller;
545                                 #interrupt-cells = <2>;
546                                 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
547                         };
548
549                         gpio7: gpio@20b4000 {
550                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
551                                 reg = <0x020b4000 0x4000>;
552                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
553                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
554                                 gpio-controller;
555                                 #gpio-cells = <2>;
556                                 interrupt-controller;
557                                 #interrupt-cells = <2>;
558                                 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
559                         };
560
561                         kpp: kpp@20b8000 {
562                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
563                                 reg = <0x020b8000 0x4000>;
564                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
565                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
566                                 status = "disabled";
567                         };
568
569                         wdog1: wdog@20bc000 {
570                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
571                                 reg = <0x020bc000 0x4000>;
572                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
573                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
574                         };
575
576                         wdog2: wdog@20c0000 {
577                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
578                                 reg = <0x020c0000 0x4000>;
579                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
580                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
581                                 status = "disabled";
582                         };
583
584                         clks: ccm@20c4000 {
585                                 compatible = "fsl,imx6sx-ccm";
586                                 reg = <0x020c4000 0x4000>;
587                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
588                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
589                                 #clock-cells = <1>;
590                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
591                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
592                         };
593
594                         anatop: anatop@20c8000 {
595                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
596                                              "syscon", "simple-bus";
597                                 reg = <0x020c8000 0x1000>;
598                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
599                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
600                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
601
602                                 regulator-1p1 {
603                                         compatible = "fsl,anatop-regulator";
604                                         regulator-name = "vdd1p1";
605                                         regulator-min-microvolt = <1000000>;
606                                         regulator-max-microvolt = <1200000>;
607                                         regulator-always-on;
608                                         anatop-reg-offset = <0x110>;
609                                         anatop-vol-bit-shift = <8>;
610                                         anatop-vol-bit-width = <5>;
611                                         anatop-min-bit-val = <4>;
612                                         anatop-min-voltage = <800000>;
613                                         anatop-max-voltage = <1375000>;
614                                         anatop-enable-bit = <0>;
615                                 };
616
617                                 regulator-3p0 {
618                                         compatible = "fsl,anatop-regulator";
619                                         regulator-name = "vdd3p0";
620                                         regulator-min-microvolt = <2800000>;
621                                         regulator-max-microvolt = <3150000>;
622                                         regulator-always-on;
623                                         anatop-reg-offset = <0x120>;
624                                         anatop-vol-bit-shift = <8>;
625                                         anatop-vol-bit-width = <5>;
626                                         anatop-min-bit-val = <0>;
627                                         anatop-min-voltage = <2625000>;
628                                         anatop-max-voltage = <3400000>;
629                                         anatop-enable-bit = <0>;
630                                 };
631
632                                 regulator-2p5 {
633                                         compatible = "fsl,anatop-regulator";
634                                         regulator-name = "vdd2p5";
635                                         regulator-min-microvolt = <2250000>;
636                                         regulator-max-microvolt = <2750000>;
637                                         regulator-always-on;
638                                         anatop-reg-offset = <0x130>;
639                                         anatop-vol-bit-shift = <8>;
640                                         anatop-vol-bit-width = <5>;
641                                         anatop-min-bit-val = <0>;
642                                         anatop-min-voltage = <2100000>;
643                                         anatop-max-voltage = <2875000>;
644                                         anatop-enable-bit = <0>;
645                                 };
646
647                                 reg_arm: regulator-vddcore {
648                                         compatible = "fsl,anatop-regulator";
649                                         regulator-name = "vddarm";
650                                         regulator-min-microvolt = <725000>;
651                                         regulator-max-microvolt = <1450000>;
652                                         regulator-always-on;
653                                         anatop-reg-offset = <0x140>;
654                                         anatop-vol-bit-shift = <0>;
655                                         anatop-vol-bit-width = <5>;
656                                         anatop-delay-reg-offset = <0x170>;
657                                         anatop-delay-bit-shift = <24>;
658                                         anatop-delay-bit-width = <2>;
659                                         anatop-min-bit-val = <1>;
660                                         anatop-min-voltage = <725000>;
661                                         anatop-max-voltage = <1450000>;
662                                 };
663
664                                 reg_pcie: regulator-vddpcie {
665                                         compatible = "fsl,anatop-regulator";
666                                         regulator-name = "vddpcie";
667                                         regulator-min-microvolt = <725000>;
668                                         regulator-max-microvolt = <1450000>;
669                                         anatop-reg-offset = <0x140>;
670                                         anatop-vol-bit-shift = <9>;
671                                         anatop-vol-bit-width = <5>;
672                                         anatop-delay-reg-offset = <0x170>;
673                                         anatop-delay-bit-shift = <26>;
674                                         anatop-delay-bit-width = <2>;
675                                         anatop-min-bit-val = <1>;
676                                         anatop-min-voltage = <725000>;
677                                         anatop-max-voltage = <1450000>;
678                                 };
679
680                                 reg_soc: regulator-vddsoc {
681                                         compatible = "fsl,anatop-regulator";
682                                         regulator-name = "vddsoc";
683                                         regulator-min-microvolt = <725000>;
684                                         regulator-max-microvolt = <1450000>;
685                                         regulator-always-on;
686                                         anatop-reg-offset = <0x140>;
687                                         anatop-vol-bit-shift = <18>;
688                                         anatop-vol-bit-width = <5>;
689                                         anatop-delay-reg-offset = <0x170>;
690                                         anatop-delay-bit-shift = <28>;
691                                         anatop-delay-bit-width = <2>;
692                                         anatop-min-bit-val = <1>;
693                                         anatop-min-voltage = <725000>;
694                                         anatop-max-voltage = <1450000>;
695                                 };
696                         };
697
698                         usbphy1: usbphy@20c9000 {
699                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
700                                 reg = <0x020c9000 0x1000>;
701                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
702                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
703                                 fsl,anatop = <&anatop>;
704                         };
705
706                         usbphy2: usbphy@20ca000 {
707                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
708                                 reg = <0x020ca000 0x1000>;
709                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
710                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
711                                 fsl,anatop = <&anatop>;
712                         };
713
714                         snvs: snvs@20cc000 {
715                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
716                                 reg = <0x020cc000 0x4000>;
717
718                                 snvs_rtc: snvs-rtc-lp {
719                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
720                                         regmap = <&snvs>;
721                                         offset = <0x34>;
722                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
723                                 };
724
725                                 snvs_poweroff: snvs-poweroff {
726                                         compatible = "syscon-poweroff";
727                                         regmap = <&snvs>;
728                                         offset = <0x38>;
729                                         value = <0x60>;
730                                         mask = <0x60>;
731                                         status = "disabled";
732                                 };
733
734                                 snvs_pwrkey: snvs-powerkey {
735                                         compatible = "fsl,sec-v4.0-pwrkey";
736                                         regmap = <&snvs>;
737                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
738                                         linux,keycode = <KEY_POWER>;
739                                         wakeup-source;
740                                 };
741                         };
742
743                         epit1: epit@20d0000 {
744                                 reg = <0x020d0000 0x4000>;
745                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
746                         };
747
748                         epit2: epit@20d4000 {
749                                 reg = <0x020d4000 0x4000>;
750                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
751                         };
752
753                         src: src@20d8000 {
754                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
755                                 reg = <0x020d8000 0x4000>;
756                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
757                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
758                                 #reset-cells = <1>;
759                         };
760
761                         gpc: gpc@20dc000 {
762                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
763                                 reg = <0x020dc000 0x4000>;
764                                 interrupt-controller;
765                                 #interrupt-cells = <3>;
766                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
767                                 interrupt-parent = <&intc>;
768                                 clocks = <&clks IMX6SX_CLK_IPG>;
769                                 clock-names = "ipg";
770
771                                 pgc {
772                                         #address-cells = <1>;
773                                         #size-cells = <0>;
774
775                                         power-domain@0 {
776                                                 reg = <0>;
777                                                 #power-domain-cells = <0>;
778                                         };
779
780                                         pd_pu: power-domain@1 {
781                                                 reg = <1>;
782                                                 #power-domain-cells = <0>;
783                                                 power-supply = <&reg_soc>;
784                                                 clocks = <&clks IMX6SX_CLK_GPU>;
785                                         };
786
787                                         pd_pci: power-domain@3 {
788                                                 reg = <3>;
789                                                 #power-domain-cells = <0>;
790                                                 power-supply = <&reg_pcie>;
791                                         };
792                                 };
793                         };
794
795                         iomuxc: iomuxc@20e0000 {
796                                 compatible = "fsl,imx6sx-iomuxc";
797                                 reg = <0x020e0000 0x4000>;
798                         };
799
800                         gpr: iomuxc-gpr@20e4000 {
801                                 compatible = "fsl,imx6sx-iomuxc-gpr",
802                                              "fsl,imx6q-iomuxc-gpr", "syscon";
803                                 reg = <0x020e4000 0x4000>;
804                         };
805
806                         sdma: sdma@20ec000 {
807                                 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
808                                 reg = <0x020ec000 0x4000>;
809                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
810                                 clocks = <&clks IMX6SX_CLK_IPG>,
811                                          <&clks IMX6SX_CLK_SDMA>;
812                                 clock-names = "ipg", "ahb";
813                                 #dma-cells = <3>;
814                                 /* imx6sx reuses imx6q sdma firmware */
815                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
816                         };
817                 };
818
819                 aips2: aips-bus@2100000 {
820                         compatible = "fsl,aips-bus", "simple-bus";
821                         #address-cells = <1>;
822                         #size-cells = <1>;
823                         reg = <0x02100000 0x100000>;
824                         ranges;
825
826                         crypto: caam@2100000 {
827                                 compatible = "fsl,sec-v4.0";
828                                 #address-cells = <1>;
829                                 #size-cells = <1>;
830                                 reg = <0x2100000 0x10000>;
831                                 ranges = <0 0x2100000 0x10000>;
832                                 interrupt-parent = <&intc>;
833                                 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
834                                          <&clks IMX6SX_CLK_CAAM_ACLK>,
835                                          <&clks IMX6SX_CLK_CAAM_IPG>,
836                                          <&clks IMX6SX_CLK_EIM_SLOW>;
837                                 clock-names = "mem", "aclk", "ipg", "emi_slow";
838
839                                 sec_jr0: jr0@1000 {
840                                         compatible = "fsl,sec-v4.0-job-ring";
841                                         reg = <0x1000 0x1000>;
842                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
843                                 };
844
845                                 sec_jr1: jr1@2000 {
846                                         compatible = "fsl,sec-v4.0-job-ring";
847                                         reg = <0x2000 0x1000>;
848                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
849                                 };
850                         };
851
852                         usbotg1: usb@2184000 {
853                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
854                                 reg = <0x02184000 0x200>;
855                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
856                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
857                                 fsl,usbphy = <&usbphy1>;
858                                 fsl,usbmisc = <&usbmisc 0>;
859                                 fsl,anatop = <&anatop>;
860                                 ahb-burst-config = <0x0>;
861                                 tx-burst-size-dword = <0x10>;
862                                 rx-burst-size-dword = <0x10>;
863                                 status = "disabled";
864                         };
865
866                         usbotg2: usb@2184200 {
867                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
868                                 reg = <0x02184200 0x200>;
869                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
870                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
871                                 fsl,usbphy = <&usbphy2>;
872                                 fsl,usbmisc = <&usbmisc 1>;
873                                 ahb-burst-config = <0x0>;
874                                 tx-burst-size-dword = <0x10>;
875                                 rx-burst-size-dword = <0x10>;
876                                 status = "disabled";
877                         };
878
879                         usbh: usb@2184400 {
880                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
881                                 reg = <0x02184400 0x200>;
882                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
883                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
884                                 fsl,usbmisc = <&usbmisc 2>;
885                                 phy_type = "hsic";
886                                 fsl,anatop = <&anatop>;
887                                 dr_mode = "host";
888                                 ahb-burst-config = <0x0>;
889                                 tx-burst-size-dword = <0x10>;
890                                 rx-burst-size-dword = <0x10>;
891                                 status = "disabled";
892                         };
893
894                         usbmisc: usbmisc@2184800 {
895                                 #index-cells = <1>;
896                                 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
897                                 reg = <0x02184800 0x200>;
898                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
899                         };
900
901                         fec1: ethernet@2188000 {
902                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
903                                 reg = <0x02188000 0x4000>;
904                                 interrupt-names = "int0", "pps";
905                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
906                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
907                                 clocks = <&clks IMX6SX_CLK_ENET>,
908                                          <&clks IMX6SX_CLK_ENET_AHB>,
909                                          <&clks IMX6SX_CLK_ENET_PTP>,
910                                          <&clks IMX6SX_CLK_ENET_REF>,
911                                          <&clks IMX6SX_CLK_ENET_PTP>;
912                                 clock-names = "ipg", "ahb", "ptp",
913                                               "enet_clk_ref", "enet_out";
914                                 fsl,num-tx-queues=<3>;
915                                 fsl,num-rx-queues=<3>;
916                                 status = "disabled";
917                         };
918
919                         mlb: mlb@218c000 {
920                                 reg = <0x0218c000 0x4000>;
921                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
922                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
923                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
924                                 clocks = <&clks IMX6SX_CLK_MLB>;
925                                 status = "disabled";
926                         };
927
928                         usdhc1: usdhc@2190000 {
929                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
930                                 reg = <0x02190000 0x4000>;
931                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
932                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
933                                          <&clks IMX6SX_CLK_USDHC1>,
934                                          <&clks IMX6SX_CLK_USDHC1>;
935                                 clock-names = "ipg", "ahb", "per";
936                                 bus-width = <4>;
937                                 status = "disabled";
938                         };
939
940                         usdhc2: usdhc@2194000 {
941                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
942                                 reg = <0x02194000 0x4000>;
943                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
944                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
945                                          <&clks IMX6SX_CLK_USDHC2>,
946                                          <&clks IMX6SX_CLK_USDHC2>;
947                                 clock-names = "ipg", "ahb", "per";
948                                 bus-width = <4>;
949                                 status = "disabled";
950                         };
951
952                         usdhc3: usdhc@2198000 {
953                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
954                                 reg = <0x02198000 0x4000>;
955                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
956                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
957                                          <&clks IMX6SX_CLK_USDHC3>,
958                                          <&clks IMX6SX_CLK_USDHC3>;
959                                 clock-names = "ipg", "ahb", "per";
960                                 bus-width = <4>;
961                                 status = "disabled";
962                         };
963
964                         usdhc4: usdhc@219c000 {
965                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
966                                 reg = <0x0219c000 0x4000>;
967                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
968                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
969                                          <&clks IMX6SX_CLK_USDHC4>,
970                                          <&clks IMX6SX_CLK_USDHC4>;
971                                 clock-names = "ipg", "ahb", "per";
972                                 bus-width = <4>;
973                                 status = "disabled";
974                         };
975
976                         i2c1: i2c@21a0000 {
977                                 #address-cells = <1>;
978                                 #size-cells = <0>;
979                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
980                                 reg = <0x021a0000 0x4000>;
981                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
982                                 clocks = <&clks IMX6SX_CLK_I2C1>;
983                                 status = "disabled";
984                         };
985
986                         i2c2: i2c@21a4000 {
987                                 #address-cells = <1>;
988                                 #size-cells = <0>;
989                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
990                                 reg = <0x021a4000 0x4000>;
991                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
992                                 clocks = <&clks IMX6SX_CLK_I2C2>;
993                                 status = "disabled";
994                         };
995
996                         i2c3: i2c@21a8000 {
997                                 #address-cells = <1>;
998                                 #size-cells = <0>;
999                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1000                                 reg = <0x021a8000 0x4000>;
1001                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1002                                 clocks = <&clks IMX6SX_CLK_I2C3>;
1003                                 status = "disabled";
1004                         };
1005
1006                         mmdc: mmdc@21b0000 {
1007                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1008                                 reg = <0x021b0000 0x4000>;
1009                         };
1010
1011                         fec2: ethernet@21b4000 {
1012                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1013                                 reg = <0x021b4000 0x4000>;
1014                                 interrupt-names = "int0", "pps";
1015                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1016                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1017                                 clocks = <&clks IMX6SX_CLK_ENET>,
1018                                          <&clks IMX6SX_CLK_ENET_AHB>,
1019                                          <&clks IMX6SX_CLK_ENET_PTP>,
1020                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
1021                                          <&clks IMX6SX_CLK_ENET_PTP>;
1022                                 clock-names = "ipg", "ahb", "ptp",
1023                                               "enet_clk_ref", "enet_out";
1024                                 status = "disabled";
1025                         };
1026
1027                         weim: weim@21b8000 {
1028                                 #address-cells = <2>;
1029                                 #size-cells = <1>;
1030                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1031                                 reg = <0x021b8000 0x4000>;
1032                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1033                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1034                                 fsl,weim-cs-gpr = <&gpr>;
1035                                 status = "disabled";
1036                         };
1037
1038                         ocotp: ocotp@21bc000 {
1039                                 #address-cells = <1>;
1040                                 #size-cells = <1>;
1041                                 compatible = "fsl,imx6sx-ocotp", "syscon";
1042                                 reg = <0x021bc000 0x4000>;
1043                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1044
1045                                 tempmon_calib: calib@38 {
1046                                         reg = <0x38 4>;
1047                                 };
1048
1049                                 tempmon_temp_grade: temp-grade@20 {
1050                                         reg = <0x20 4>;
1051                                 };
1052                         };
1053
1054                         sai1: sai@21d4000 {
1055                                 compatible = "fsl,imx6sx-sai";
1056                                 reg = <0x021d4000 0x4000>;
1057                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1058                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1059                                          <&clks IMX6SX_CLK_SAI1>,
1060                                          <&clks 0>, <&clks 0>;
1061                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1062                                 dma-names = "rx", "tx";
1063                                 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1064                                 status = "disabled";
1065                         };
1066
1067                         audmux: audmux@21d8000 {
1068                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1069                                 reg = <0x021d8000 0x4000>;
1070                                 status = "disabled";
1071                         };
1072
1073                         sai2: sai@21dc000 {
1074                                 compatible = "fsl,imx6sx-sai";
1075                                 reg = <0x021dc000 0x4000>;
1076                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1077                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1078                                          <&clks IMX6SX_CLK_SAI2>,
1079                                          <&clks 0>, <&clks 0>;
1080                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1081                                 dma-names = "rx", "tx";
1082                                 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1083                                 status = "disabled";
1084                         };
1085
1086                         qspi1: qspi@21e0000 {
1087                                 #address-cells = <1>;
1088                                 #size-cells = <0>;
1089                                 compatible = "fsl,imx6sx-qspi";
1090                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1091                                 reg-names = "QuadSPI", "QuadSPI-memory";
1092                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1093                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1094                                          <&clks IMX6SX_CLK_QSPI1>;
1095                                 clock-names = "qspi_en", "qspi";
1096                                 status = "disabled";
1097                         };
1098
1099                         qspi2: qspi@21e4000 {
1100                                 #address-cells = <1>;
1101                                 #size-cells = <0>;
1102                                 compatible = "fsl,imx6sx-qspi";
1103                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1104                                 reg-names = "QuadSPI", "QuadSPI-memory";
1105                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1106                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1107                                          <&clks IMX6SX_CLK_QSPI2>;
1108                                 clock-names = "qspi_en", "qspi";
1109                                 status = "disabled";
1110                         };
1111
1112                         uart2: serial@21e8000 {
1113                                 compatible = "fsl,imx6sx-uart",
1114                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1115                                 reg = <0x021e8000 0x4000>;
1116                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1117                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1118                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1119                                 clock-names = "ipg", "per";
1120                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1121                                 dma-names = "rx", "tx";
1122                                 status = "disabled";
1123                         };
1124
1125                         uart3: serial@21ec000 {
1126                                 compatible = "fsl,imx6sx-uart",
1127                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1128                                 reg = <0x021ec000 0x4000>;
1129                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1130                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1131                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1132                                 clock-names = "ipg", "per";
1133                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1134                                 dma-names = "rx", "tx";
1135                                 status = "disabled";
1136                         };
1137
1138                         uart4: serial@21f0000 {
1139                                 compatible = "fsl,imx6sx-uart",
1140                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1141                                 reg = <0x021f0000 0x4000>;
1142                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1143                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1144                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1145                                 clock-names = "ipg", "per";
1146                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1147                                 dma-names = "rx", "tx";
1148                                 status = "disabled";
1149                         };
1150
1151                         uart5: serial@21f4000 {
1152                                 compatible = "fsl,imx6sx-uart",
1153                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1154                                 reg = <0x021f4000 0x4000>;
1155                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1156                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1157                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1158                                 clock-names = "ipg", "per";
1159                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1160                                 dma-names = "rx", "tx";
1161                                 status = "disabled";
1162                         };
1163
1164                         i2c4: i2c@21f8000 {
1165                                 #address-cells = <1>;
1166                                 #size-cells = <0>;
1167                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1168                                 reg = <0x021f8000 0x4000>;
1169                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1170                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1171                                 status = "disabled";
1172                         };
1173                 };
1174
1175                 aips3: aips-bus@2200000 {
1176                         compatible = "fsl,aips-bus", "simple-bus";
1177                         #address-cells = <1>;
1178                         #size-cells = <1>;
1179                         reg = <0x02200000 0x100000>;
1180                         ranges;
1181
1182                         spba-bus@2240000 {
1183                                 compatible = "fsl,spba-bus", "simple-bus";
1184                                 #address-cells = <1>;
1185                                 #size-cells = <1>;
1186                                 reg = <0x02240000 0x40000>;
1187                                 ranges;
1188
1189                                 csi1: csi@2214000 {
1190                                         reg = <0x02214000 0x4000>;
1191                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1192                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1193                                                  <&clks IMX6SX_CLK_CSI>,
1194                                                  <&clks IMX6SX_CLK_DCIC1>;
1195                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1196                                         status = "disabled";
1197                                 };
1198
1199                                 pxp: pxp@2218000 {
1200                                         reg = <0x02218000 0x4000>;
1201                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1202                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1203                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1204                                         clock-names = "pxp-axi", "disp-axi";
1205                                         status = "disabled";
1206                                 };
1207
1208                                 csi2: csi@221c000 {
1209                                         reg = <0x0221c000 0x4000>;
1210                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1211                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1212                                                  <&clks IMX6SX_CLK_CSI>,
1213                                                  <&clks IMX6SX_CLK_DCIC2>;
1214                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1215                                         status = "disabled";
1216                                 };
1217
1218                                 lcdif1: lcdif@2220000 {
1219                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1220                                         reg = <0x02220000 0x4000>;
1221                                         interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1222                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1223                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1224                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1225                                         clock-names = "pix", "axi", "disp_axi";
1226                                         status = "disabled";
1227                                 };
1228
1229                                 lcdif2: lcdif@2224000 {
1230                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1231                                         reg = <0x02224000 0x4000>;
1232                                         interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1233                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1234                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1235                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1236                                         clock-names = "pix", "axi", "disp_axi";
1237                                         status = "disabled";
1238                                 };
1239
1240                                 vadc: vadc@2228000 {
1241                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1242                                         reg-names = "vadc-vafe", "vadc-vdec";
1243                                         clocks = <&clks IMX6SX_CLK_VADC>,
1244                                                  <&clks IMX6SX_CLK_CSI>;
1245                                         clock-names = "vadc", "csi";
1246                                         status = "disabled";
1247                                 };
1248                         };
1249
1250                         adc1: adc@2280000 {
1251                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1252                                 reg = <0x02280000 0x4000>;
1253                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1254                                 clocks = <&clks IMX6SX_CLK_IPG>;
1255                                 clock-names = "adc";
1256                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1257                                                          <20000000>;
1258                                 status = "disabled";
1259                         };
1260
1261                         adc2: adc@2284000 {
1262                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1263                                 reg = <0x02284000 0x4000>;
1264                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1265                                 clocks = <&clks IMX6SX_CLK_IPG>;
1266                                 clock-names = "adc";
1267                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1268                                                          <20000000>;
1269                                 status = "disabled";
1270                         };
1271
1272                         wdog3: wdog@2288000 {
1273                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1274                                 reg = <0x02288000 0x4000>;
1275                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1276                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
1277                                 status = "disabled";
1278                         };
1279
1280                         ecspi5: ecspi@228c000 {
1281                                 #address-cells = <1>;
1282                                 #size-cells = <0>;
1283                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1284                                 reg = <0x0228c000 0x4000>;
1285                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1286                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1287                                          <&clks IMX6SX_CLK_ECSPI5>;
1288                                 clock-names = "ipg", "per";
1289                                 status = "disabled";
1290                         };
1291
1292                         uart6: serial@22a0000 {
1293                                 compatible = "fsl,imx6sx-uart",
1294                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1295                                 reg = <0x022a0000 0x4000>;
1296                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1297                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1298                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1299                                 clock-names = "ipg", "per";
1300                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1301                                 dma-names = "rx", "tx";
1302                                 status = "disabled";
1303                         };
1304
1305                         pwm5: pwm@22a4000 {
1306                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1307                                 reg = <0x022a4000 0x4000>;
1308                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1309                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1310                                          <&clks IMX6SX_CLK_PWM5>;
1311                                 clock-names = "ipg", "per";
1312                                 #pwm-cells = <2>;
1313                         };
1314
1315                         pwm6: pwm@22a8000 {
1316                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1317                                 reg = <0x022a8000 0x4000>;
1318                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1319                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1320                                          <&clks IMX6SX_CLK_PWM6>;
1321                                 clock-names = "ipg", "per";
1322                                 #pwm-cells = <2>;
1323                         };
1324
1325                         pwm7: pwm@22ac000 {
1326                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1327                                 reg = <0x022ac000 0x4000>;
1328                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1329                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1330                                          <&clks IMX6SX_CLK_PWM7>;
1331                                 clock-names = "ipg", "per";
1332                                 #pwm-cells = <2>;
1333                         };
1334
1335                         pwm8: pwm@22b0000 {
1336                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1337                                 reg = <0x0022b0000 0x4000>;
1338                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1339                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1340                                          <&clks IMX6SX_CLK_PWM8>;
1341                                 clock-names = "ipg", "per";
1342                                 #pwm-cells = <2>;
1343                         };
1344                 };
1345
1346                 pcie: pcie@8ffc000 {
1347                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1348                         reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1349                         reg-names = "dbi", "config";
1350                         #address-cells = <3>;
1351                         #size-cells = <2>;
1352                         device_type = "pci";
1353                         bus-range = <0x00 0xff>;
1354                         ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
1355                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1356                         num-lanes = <1>;
1357                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1358                         interrupt-names = "msi";
1359                         #interrupt-cells = <1>;
1360                         interrupt-map-mask = <0 0 0 0x7>;
1361                         interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1362                                         <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1363                                         <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1364                                         <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1365                         clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1366                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1367                                  <&clks IMX6SX_CLK_PCIE_REF_125M>,
1368                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1369                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1370                         power-domains = <&pd_pci>;
1371                         status = "disabled";
1372                 };
1373         };
1374 };