arch/arm/boot/dts/imx6ul-pico-hobbit.dts

   1 /*
   2  * Copyright 2015 Technexion Ltd.
   3  *
   4  * Author: Wig Cheng  <wig.cheng@technexion.com>
   5  *         Richard Hu <richard.hu@technexion.com>
   6  *         Tapani Utriainen <tapani@technexion.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPL or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This file is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License
  15  *     version 2 as published by the Free Software Foundation.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 /dts-v1/;
  47
  48 #include "imx6ul.dtsi"
  49
  50 / {
  51         model = "Technexion Pico i.MX6UL Board";
  52         compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";
  53
  54         /* Will be filled by the bootloader */
  55         memory@80000000 {
  56                 device_type = "memory";
  57                 reg = <0x80000000 0>;
  58         };
  59
  60         chosen {
  61                 stdout-path = &uart6;
  62         };
  63
  64         backlight {
  65                 compatible = "pwm-backlight";
  66                 pwms = <&pwm3 0 5000000>;
  67                 brightness-levels = <0 4 8 16 32 64 128 255>;
  68                 default-brightness-level = <6>;
  69                 status = "okay";
  70         };
  71
  72         reg_2p5v: regulator-2p5v {
  73                 compatible = "regulator-fixed";
  74                 regulator-name = "2P5V";
  75                 regulator-min-microvolt = <2500000>;
  76                 regulator-max-microvolt = <2500000>;
  77         };
  78
  79         reg_3p3v: regulator-3p3v {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "3P3V";
  82                 regulator-min-microvolt = <3300000>;
  83                 regulator-max-microvolt = <3300000>;
  84         };
  85
  86         reg_sd1_vmmc: regulator-sd1-vmmc {
  87                 compatible = "regulator-fixed";
  88                 regulator-name = "VSD_3V3";
  89                 regulator-min-microvolt = <3300000>;
  90                 regulator-max-microvolt = <3300000>;
  91                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  92                 enable-active-high;
  93         };
  94
  95         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  96                 compatible = "regulator-fixed";
  97                 pinctrl-names = "default";
  98                 pinctrl-0 = <&pinctrl_usb_otg1>;
  99                 regulator-name = "usb_otg_vbus";
 100                 regulator-min-microvolt = <5000000>;
 101                 regulator-max-microvolt = <5000000>;
 102                 gpio = <&gpio1 6 0>;
 103         };
 104
 105         reg_brcm: regulator-brcm {
 106                 compatible = "regulator-fixed";
 107                 enable-active-high;
 108                 gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
 109                 pinctrl-names = "default";
 110                 pinctrl-0 = <&pinctrl_brcm_reg>;
 111                 regulator-name = "brcm_reg";
 112                 regulator-min-microvolt = <3300000>;
 113                 regulator-max-microvolt = <3300000>;
 114                 startup-delay-us = <200000>;
 115         };
 116
 117         sound {
 118                 compatible = "fsl,imx-audio-sgtl5000";
 119                 model = "imx6ul-sgtl5000";
 120                 audio-cpu = <&sai1>;
 121                 audio-codec = <&codec>;
 122                 audio-routing =
 123                         "LINE_IN", "Line In Jack",
 124                         "MIC_IN", "Mic Jack",
 125                         "Mic Jack", "Mic Bias",
 126                         "Headphone Jack", "HP_OUT";
 127         };
 128
 129         sys_mclk: clock-sys-mclk {
 130                 compatible = "fixed-clock";
 131                 #clock-cells = <0>;
 132                 clock-frequency = <24576000>;
 133         };
 134
 135         leds {
 136                 compatible = "gpio-leds";
 137
 138                 hobbitled {
 139                         label = "hobbitled";
 140                         gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
 141                 };
 142         };
 143 };
 144
 145 &can1 {
 146         pinctrl-names = "default";
 147         pinctrl-0 = <&pinctrl_flexcan1>;
 148         status = "okay";
 149 };
 150
 151 &can2 {
 152         pinctrl-names = "default";
 153         pinctrl-0 = <&pinctrl_flexcan2>;
 154         status = "okay";
 155 };
 156
 157 &clks {
 158         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 159         assigned-clock-rates = <786432000>;
 160 };
 161
 162 &fec2 {
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_enet2>;
 165         phy-mode = "rmii";
 166         phy-handle = <&ethphy1>;
 167         status = "okay";
 168         phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
 169         phy-reset-duration = <1>;
 170
 171         mdio {
 172                 #address-cells = <1>;
 173                 #size-cells = <0>;
 174
 175                 ethphy1: ethernet-phy@1 {
 176                         compatible = "ethernet-phy-ieee802.3-c22";
 177                         reg = <1>;
 178                         max-speed = <100>;
 179                         interrupt-parent = <&gpio5>;
 180                         interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
 181                 };
 182         };
 183 };
 184
 185 &i2c1 {
 186         clock-frequency = <100000>;
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&pinctrl_i2c1>;
 189         status = "okay";
 190
 191         pmic: pfuze3000@8 {
 192                 compatible = "fsl,pfuze3000";
 193                 reg = <0x08>;
 194
 195                 regulators {
 196                         /* VDD_ARM_SOC_IN*/
 197                         sw1b_reg: sw1b {
 198                                 regulator-min-microvolt = <700000>;
 199                                 regulator-max-microvolt = <1475000>;
 200                                 regulator-boot-on;
 201                                 regulator-always-on;
 202                                 regulator-ramp-delay = <6250>;
 203                         };
 204
 205                         /* DRAM */
 206                         sw3a_reg: sw3 {
 207                                 regulator-min-microvolt = <900000>;
 208                                 regulator-max-microvolt = <1650000>;
 209                                 regulator-boot-on;
 210                                 regulator-always-on;
 211                         };
 212
 213                         /* DRAM */
 214                         vref_reg: vrefddr {
 215                                 regulator-boot-on;
 216                                 regulator-always-on;
 217                         };
 218                 };
 219         };
 220 };
 221
 222 &i2c2 {
 223         clock_frequency = <100000>;
 224         pinctrl-names = "default";
 225         pinctrl-0 = <&pinctrl_i2c2>;
 226         status = "okay";
 227
 228         codec: sgtl5000@a {
 229                 reg = <0x0a>;
 230                 compatible = "fsl,sgtl5000";
 231                 clocks = <&sys_mclk>;
 232                 VDDA-supply = <&reg_2p5v>;
 233                 VDDIO-supply = <&reg_3p3v>;
 234         };
 235 };
 236
 237 &i2c3 {
 238         clock_frequency = <100000>;
 239         pinctrl-names = "default";
 240         pinctrl-0 = <&pinctrl_i2c3>;
 241         status = "okay";
 242 };
 243
 244 &lcdif {
 245         pinctrl-names = "default";
 246         pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
 247         display = <&display0>;
 248         status = "okay";
 249
 250         display0: display0 {
 251                 bits-per-pixel = <32>;
 252                 bus-width = <24>;
 253
 254                 display-timings {
 255                         native-mode = <&timing0>;
 256
 257                         timing0: timing0 {
 258                                 clock-frequency = <33200000>;
 259                                 hactive = <800>;
 260                                 vactive = <480>;
 261                                 hfront-porch = <210>;
 262                                 hback-porch = <46>;
 263                                 hsync-len = <1>;
 264                                 vback-porch = <22>;
 265                                 vfront-porch = <23>;
 266                                 vsync-len = <1>;
 267                                 hsync-active = <0>;
 268                                 vsync-active = <0>;
 269                                 de-active = <1>;
 270                                 pixelclk-active = <0>;
 271                         };
 272                 };
 273         };
 274 };
 275
 276 &pwm3 {
 277         pinctrl-names = "default";
 278         pinctrl-0 = <&pinctrl_pwm3>;
 279         status = "okay";
 280 };
 281
 282 &pwm7 {
 283         pinctrl-names = "default";
 284         pinctrl-0 = <&pinctrl_pwm7>;
 285         status = "okay";
 286 };
 287
 288 &pwm8 {
 289         pinctrl-names = "default";
 290         pinctrl-0 = <&pinctrl_pwm8>;
 291         status = "okay";
 292 };
 293
 294 &sai1 {
 295         pinctrl-names = "default";
 296         pinctrl-0 = <&pinctrl_sai1>;
 297         status = "okay";
 298 };
 299
 300 &uart3 {
 301         pinctrl-names = "default";
 302         pinctrl-0 = <&pinctrl_uart3>;
 303         uart-has-rtscts;
 304         status = "okay";
 305 };
 306
 307 &uart6 {
 308         pinctrl-names = "default";
 309         pinctrl-0 = <&pinctrl_uart6>;
 310         status = "okay";
 311 };
 312
 313 &usbotg1 {
 314         vbus-supply = <&reg_usb_otg_vbus>;
 315         pinctrl-names = "default";
 316         pinctrl-0 = <&pinctrl_usb_otg1_id>;
 317         dr_mode = "otg";
 318         disable-over-current;
 319         status = "okay";
 320 };
 321
 322 &usbotg2 {
 323         dr_mode = "host";
 324         disable-over-current;
 325         status = "okay";
 326 };
 327
 328 &usdhc1 {
 329         pinctrl-names = "default";
 330         pinctrl-0 = <&pinctrl_usdhc1>;
 331         bus-width = <8>;
 332         no-1-8-v;
 333         non-removable;
 334         keep-power-in-suspend;
 335         status = "okay";
 336 };
 337
 338 &usdhc2 {  /* Wifi SDIO */
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_usdhc2>;
 341         no-1-8-v;
 342         non-removable;
 343         keep-power-in-suspend;
 344         wakeup-source;
 345         vmmc-supply = <&reg_brcm>;
 346         status = "okay";
 347 };
 348
 349 &wdog1 {
 350         pinctrl-names = "default";
 351         pinctrl-0 = <&pinctrl_wdog>;
 352         fsl,ext-reset-output;
 353 };
 354
 355 &iomuxc {
 356         pinctrl_brcm_reg: brcmreggrp {
 357                 fsl,pins = <
 358                         MX6UL_PAD_NAND_DATA06__GPIO4_IO08       0x10b0  /* WL_REG_ON */
 359                         MX6UL_PAD_NAND_DATA04__GPIO4_IO06       0x10b0  /* WL_HOST_WAKE */
 360                 >;
 361         };
 362
 363         pinctrl_enet2: enet2grp {
 364                 fsl,pins = <
 365                         MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO    0x1b0b0
 366                         MX6UL_PAD_ENET1_TX_EN__ENET2_MDC        0x1b0b0
 367                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 368                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 369                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 370                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 371                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 372                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 373                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 374                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 375                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x800
 376                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x79
 377                 >;
 378         };
 379
 380         pinctrl_flexcan1: flexcan1grp {
 381                 fsl,pins = <
 382                         MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX   0x1b020
 383                         MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX   0x1b020
 384                 >;
 385         };
 386
 387         pinctrl_flexcan2: flexcan2grp {
 388                 fsl,pins = <
 389                         MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX   0x1b020
 390                         MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX      0x1b020
 391                 >;
 392         };
 393
 394         pinctrl_i2c1: i2c1grp {
 395                 fsl,pins = <
 396                         MX6UL_PAD_GPIO1_IO02__I2C1_SCL          0x4001b8b0
 397                         MX6UL_PAD_GPIO1_IO03__I2C1_SDA          0x4001b8b0
 398                 >;
 399         };
 400
 401         pinctrl_i2c2: i2c2grp {
 402                 fsl,pins = <
 403                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL       0x4001b8b0
 404                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA       0x4001b8b0
 405                 >;
 406         };
 407
 408         pinctrl_i2c3: i2c3grp {
 409                 fsl,pins = <
 410                         MX6UL_PAD_UART1_TX_DATA__I2C3_SCL       0x4001b8b0
 411                         MX6UL_PAD_UART1_RX_DATA__I2C3_SDA       0x4001b8b0
 412                         >;
 413         };
 414
 415         pinctrl_lcdif_dat: lcdifdatgrp {
 416                 fsl,pins = <
 417                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x79
 418                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x79
 419                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x79
 420                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x79
 421                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x79
 422                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x79
 423                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x79
 424                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x79
 425                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x79
 426                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x79
 427                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x79
 428                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x79
 429                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x79
 430                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x79
 431                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x79
 432                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x79
 433                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x79
 434                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x79
 435                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x79
 436                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x79
 437                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x79
 438                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x79
 439                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x79
 440                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x79
 441                 >;
 442         };
 443
 444         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 445                 fsl,pins = <
 446                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x79
 447                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x79
 448                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x79
 449                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x79
 450                         /* LCD reset */
 451                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x79
 452                 >;
 453         };
 454
 455         pinctrl_pwm3: pwm3grp {
 456                 fsl,pins = <
 457                         MX6UL_PAD_NAND_ALE__PWM3_OUT            0x110b0
 458                 >;
 459         };
 460
 461         pinctrl_pwm7: pwm7grp {
 462                 fsl,pins = <
 463                         MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT        0x110b0
 464                 >;
 465         };
 466
 467         pinctrl_pwm8: pwm8grp {
 468                 fsl,pins = <
 469                         MX6UL_PAD_ENET1_RX_ER__PWM8_OUT         0x110b0
 470                 >;
 471         };
 472
 473         pinctrl_sai1: sai1grp {
 474                 fsl,pins = <
 475                         MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC      0x1b0b0
 476                         MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK      0x1b0b0
 477                         MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA      0x110b0
 478                         MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA      0x1f0b8
 479                 >;
 480         };
 481
 482         pinctrl_uart3: uart3grp {
 483                 fsl,pins = <
 484                         MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x1b0b0
 485                         MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX   0x1b0b0
 486                         MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS    0x1b0b0
 487                         MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS    0x1b0b0
 488                 >;
 489         };
 490
 491         pinctrl_uart5: uart5grp {
 492                 fsl,pins = <
 493                         MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x1b0b1
 494                         MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x1b0b1
 495                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x1b0b1
 496                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x1b0b1
 497                 >;
 498         };
 499
 500         pinctrl_uart6: uart6grp {
 501                 fsl,pins = <
 502                         MX6UL_PAD_CSI_MCLK__UART6_DCE_TX        0x1b0b1
 503                         MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX      0x1b0b1
 504                 >;
 505         };
 506
 507         pinctrl_usb_otg1: usbotg1grp {
 508                 fsl,pins = <
 509                         MX6UL_PAD_GPIO1_IO06__GPIO1_IO06        0x10b0
 510                         >;
 511         };
 512
 513         pinctrl_usb_otg1_id: usbotg1idgrp {
 514                 fsl,pins = <
 515                         MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
 516                 >;
 517         };
 518
 519         pinctrl_usdhc1: usdhc1grp {
 520                 fsl,pins = <
 521                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 522                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10071
 523                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 524                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 525                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 526                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 527                         MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B      0x03029
 528                         MX6UL_PAD_NAND_READY_B__USDHC1_DATA4    0x17059
 529                         MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5      0x17059
 530                         MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6      0x17059
 531                         MX6UL_PAD_NAND_CLE__USDHC1_DATA7        0x17059
 532                 >;
 533         };
 534
 535         pinctrl_usdhc2: usdhc2grp {
 536                 fsl,pins = <
 537                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x17059
 538                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x10059
 539                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x17059
 540                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x17059
 541                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x17059
 542                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x17059
 543                 >;
 544         };
 545
 546         pinctrl_wdog: wdoggrp {
 547                 fsl,pins = <
 548                         MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
 549                 >;
 550         };
 551 };