arch/arm/boot/dts/imx7s-warp.dts

   1 /*
   2  * Copyright (C) 2016 NXP Semiconductors.
   3  * Author: Fabio Estevam <fabio.estevam@nxp.com>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 /dts-v1/;
  45
  46 #include <dt-bindings/input/input.h>
  47 #include "imx7s.dtsi"
  48
  49 / {
  50         model = "Warp i.MX7 Board";
  51         compatible = "warp,imx7s-warp", "fsl,imx7s";
  52
  53         memory@80000000 {
  54                 device_type = "memory";
  55                 reg = <0x80000000 0x20000000>;
  56         };
  57
  58         gpio-keys {
  59                 compatible = "gpio-keys";
  60                 pinctrl-0 = <&pinctrl_gpio>;
  61                 autorepeat;
  62
  63                 back {
  64                         label = "Back";
  65                         gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  66                         linux,code = <KEY_BACK>;
  67                         wakeup-source;
  68                 };
  69         };
  70
  71         reg_brcm: regulator-brcm {
  72                 compatible = "regulator-fixed";
  73                 enable-active-high;
  74                 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
  75                 pinctrl-names = "default";
  76                 pinctrl-0 = <&pinctrl_brcm_reg>;
  77                 regulator-name = "brcm_reg";
  78                 regulator-min-microvolt = <3300000>;
  79                 regulator-max-microvolt = <3300000>;
  80                 startup-delay-us = <200000>;
  81         };
  82
  83         reg_bt: regulator-bt {
  84                 compatible = "regulator-fixed";
  85                 pinctrl-names = "default";
  86                 pinctrl-0 = <&pinctrl_bt_reg>;
  87                 enable-active-high;
  88                 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
  89                 regulator-name = "bt_reg";
  90                 regulator-min-microvolt = <3300000>;
  91                 regulator-max-microvolt = <3300000>;
  92                 regulator-always-on;
  93         };
  94
  95         sound {
  96                 compatible = "simple-audio-card";
  97                 simple-audio-card,name = "imx7-sgtl5000";
  98                 simple-audio-card,format = "i2s";
  99                 simple-audio-card,bitclock-master = <&dailink_master>;
 100                 simple-audio-card,frame-master = <&dailink_master>;
 101                 simple-audio-card,cpu {
 102                         sound-dai = <&sai1>;
 103                 };
 104
 105                 dailink_master: simple-audio-card,codec {
 106                         sound-dai = <&codec>;
 107                         clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 108                 };
 109         };
 110 };
 111
 112 &clks {
 113         assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 114         assigned-clock-rates = <884736000>;
 115 };
 116
 117 &i2c1 {
 118         pinctrl-names = "default";
 119         pinctrl-0 = <&pinctrl_i2c1>;
 120         status = "okay";
 121
 122         pmic: pfuze3000@8 {
 123                 compatible = "fsl,pfuze3000";
 124                 reg = <0x08>;
 125
 126                 regulators {
 127                         sw1a_reg: sw1a {
 128                                 regulator-min-microvolt = <700000>;
 129                                 regulator-max-microvolt = <1475000>;
 130                                 regulator-boot-on;
 131                                 regulator-always-on;
 132                                 regulator-ramp-delay = <6250>;
 133                         };
 134
 135                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 136                         sw1c_reg: sw1b {
 137                                 regulator-min-microvolt = <700000>;
 138                                 regulator-max-microvolt = <1475000>;
 139                                 regulator-boot-on;
 140                                 regulator-always-on;
 141                                 regulator-ramp-delay = <6250>;
 142                         };
 143
 144                         sw2_reg: sw2 {
 145                                 regulator-min-microvolt = <1500000>;
 146                                 regulator-max-microvolt = <1850000>;
 147                                 regulator-boot-on;
 148                                 regulator-always-on;
 149                         };
 150
 151                         sw3a_reg: sw3 {
 152                                 regulator-min-microvolt = <900000>;
 153                                 regulator-max-microvolt = <1650000>;
 154                                 regulator-boot-on;
 155                                 regulator-always-on;
 156                         };
 157
 158                         swbst_reg: swbst {
 159                                 regulator-min-microvolt = <5000000>;
 160                                 regulator-max-microvolt = <5150000>;
 161                         };
 162
 163                         snvs_reg: vsnvs {
 164                                 regulator-min-microvolt = <1000000>;
 165                                 regulator-max-microvolt = <3000000>;
 166                                 regulator-boot-on;
 167                                 regulator-always-on;
 168                         };
 169
 170                         vref_reg: vrefddr {
 171                                 regulator-boot-on;
 172                                 regulator-always-on;
 173                         };
 174
 175                         vgen1_reg: vldo1 {
 176                                 regulator-min-microvolt = <1800000>;
 177                                 regulator-max-microvolt = <3300000>;
 178                                 regulator-always-on;
 179                         };
 180
 181                         vgen2_reg: vldo2 {
 182                                 regulator-min-microvolt = <800000>;
 183                                 regulator-max-microvolt = <1550000>;
 184                         };
 185
 186                         vgen3_reg: vccsd {
 187                                 regulator-min-microvolt = <2850000>;
 188                                 regulator-max-microvolt = <3300000>;
 189                                 regulator-always-on;
 190                         };
 191
 192                         vgen4_reg: v33 {
 193                                 regulator-min-microvolt = <2850000>;
 194                                 regulator-max-microvolt = <3300000>;
 195                                 regulator-always-on;
 196                         };
 197
 198                         vgen5_reg: vldo3 {
 199                                 regulator-min-microvolt = <1800000>;
 200                                 regulator-max-microvolt = <3300000>;
 201                                 regulator-always-on;
 202                         };
 203
 204                         vgen6_reg: vldo4 {
 205                                 regulator-min-microvolt = <1800000>;
 206                                 regulator-max-microvolt = <3300000>;
 207                                 regulator-always-on;
 208                         };
 209                 };
 210         };
 211 };
 212
 213 &i2c2 {
 214         clock-frequency = <100000>;
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_i2c2>;
 217         status = "okay";
 218 };
 219
 220 &i2c4 {
 221         clock-frequency = <100000>;
 222         pinctrl-names = "default";
 223         pinctrl-0 = <&pinctrl_i2c4>;
 224         status = "okay";
 225
 226         codec: sgtl5000@a {
 227                 #sound-dai-cells = <0>;
 228                 reg = <0x0a>;
 229                 compatible = "fsl,sgtl5000";
 230                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 231                 pinctrl-names = "default";
 232                 pinctrl-0 = <&pinctrl_sai1_mclk>;
 233                 VDDA-supply = <&vgen4_reg>;
 234                 VDDIO-supply = <&vgen4_reg>;
 235                 VDDD-supply = <&vgen2_reg>;
 236         };
 237
 238         mpl3115@60 {
 239                 compatible = "fsl,mpl3115";
 240                 reg = <0x60>;
 241         };
 242 };
 243
 244 &sai1 {
 245         pinctrl-names = "default";
 246         pinctrl-0 = <&pinctrl_sai1>;
 247         assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
 248                           <&clks IMX7D_SAI1_ROOT_CLK>;
 249         assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 250         assigned-clock-rates = <0>, <36864000>;
 251         status = "okay";
 252 };
 253
 254 &uart1 {
 255         pinctrl-names = "default";
 256         pinctrl-0 = <&pinctrl_uart1>;
 257         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 258         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 259         status = "okay";
 260 };
 261
 262 &uart3  {
 263         pinctrl-names = "default";
 264         pinctrl-0 = <&pinctrl_uart3>;
 265         assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 266         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 267         uart-has-rtscts;
 268         status = "okay";
 269 };
 270
 271 &uart6 {
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_uart6>;
 274         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 275         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 276         fsl,dte-mode;
 277         status = "okay";
 278 };
 279
 280 &usbotg1 {
 281         dr_mode = "peripheral";
 282         status = "okay";
 283 };
 284
 285 &usdhc1 {
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&pinctrl_usdhc1>;
 288         bus-width = <4>;
 289         keep-power-in-suspend;
 290         no-1-8-v;
 291         non-removable;
 292         vmmc-supply = <&reg_brcm>;
 293         status = "okay";
 294 };
 295
 296 &usdhc3 {
 297         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 298         pinctrl-0 = <&pinctrl_usdhc3>;
 299         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 300         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 301         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 302         assigned-clock-rates = <400000000>;
 303         bus-width = <8>;
 304         no-1-8-v;
 305         fsl,tuning-step = <2>;
 306         non-removable;
 307         status = "okay";
 308 };
 309
 310 &wdog1 {
 311         pinctrl-names = "default";
 312         pinctrl-0 = <&pinctrl_wdog>;
 313         fsl,ext-reset-output;
 314         status = "okay";
 315 };
 316
 317 &iomuxc {
 318         pinctrl_brcm_reg: brcmreggrp {
 319                 fsl,pins = <
 320                         MX7D_PAD_SD2_WP__GPIO5_IO10     0x14 /* WL_REG_ON */
 321                 >;
 322         };
 323
 324         pinctrl_bt_reg: btreggrp {
 325                 fsl,pins = <
 326                         MX7D_PAD_SD2_DATA3__GPIO5_IO17  0x14 /* BT_REG_ON */
 327                 >;
 328         };
 329
 330         pinctrl_gpio: gpiogrp {
 331                 fsl,pins = <
 332                         MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1     0x14
 333                 >;
 334         };
 335
 336         pinctrl_i2c1: i2c1grp {
 337                 fsl,pins = <
 338                         MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 339                         MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 340                 >;
 341         };
 342
 343         pinctrl_i2c2: i2c2grp {
 344                 fsl,pins = <
 345                         MX7D_PAD_I2C2_SDA__I2C2_SDA     0x4000007f
 346                         MX7D_PAD_I2C2_SCL__I2C2_SCL     0x4000007f
 347                 >;
 348         };
 349
 350         pinctrl_i2c4: i2c4grp {
 351                 fsl,pins = <
 352                         MX7D_PAD_I2C4_SCL__I2C4_SCL     0x4000007f
 353                         MX7D_PAD_I2C4_SDA__I2C4_SDA     0x4000007f
 354                 >;
 355         };
 356
 357         pinctrl_sai1: sai1grp {
 358                 fsl,pins = <
 359                         MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0    0x1f
 360                         MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK     0x1f
 361                         MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
 362                         MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0    0x30
 363                 >;
 364         };
 365
 366         pinctrl_sai1_mclk: sai1mclkgrp {
 367                 fsl,pins = <
 368                         MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
 369                 >;
 370         };
 371
 372         pinctrl_uart1: uart1grp {
 373                 fsl,pins = <
 374                         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 375                         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 376                 >;
 377         };
 378
 379         pinctrl_uart3: uart3grp {
 380                 fsl,pins = <
 381                         MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x79
 382                         MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x79
 383                         MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS     0x79
 384                         MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS     0x79
 385                 >;
 386         };
 387
 388         pinctrl_uart6: uart6grp {
 389                 fsl,pins = <
 390                         MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX      0x79
 391                         MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX      0x79
 392                 >;
 393         };
 394
 395         pinctrl_usdhc1: usdhc1grp {
 396                 fsl,pins = <
 397                         MX7D_PAD_SD1_CMD__SD1_CMD       0x59
 398                         MX7D_PAD_SD1_CLK__SD1_CLK       0x19
 399                         MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
 400                         MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
 401                         MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
 402                         MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
 403                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
 404                 >;
 405         };
 406
 407         pinctrl_usdhc3: usdhc3grp {
 408                 fsl,pins = <
 409                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 410                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 411                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 412                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 413                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 414                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 415                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 416                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 417                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 418                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 419                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x19
 420                 >;
 421         };
 422
 423         pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 424                 fsl,pins = <
 425                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 426                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 427                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 428                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 429                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 430                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 431                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 432                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 433                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 434                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 435                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x1a
 436                 >;
 437         };
 438
 439         pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 440                 fsl,pins = <
 441                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 442                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 443                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 444                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 445                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 446                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 447                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 448                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 449                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 450                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 451                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x1b
 452                 >;
 453         };
 454 };
 455
 456 &iomuxc_lpsr {
 457         pinctrl_wdog: wdoggrp {
 458                 fsl,pins = <
 459                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B  0x74
 460                 >;
 461         };
 462 };