arch/arm/boot/dts/logicpd-som-lv.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #include <dt-bindings/input/input.h>
   8
   9 / {
  10         cpus {
  11                 cpu@0 {
  12                         cpu0-supply = <&vcc>;
  13                 };
  14         };
  15
  16         memory@80000000 {
  17                 device_type = "memory";
  18                 reg = <0x80000000 0>;
  19         };
  20
  21         wl12xx_vmmc: wl12xx_vmmc {
  22                 compatible = "regulator-fixed";
  23                 regulator-name = "vwl1271";
  24                 regulator-min-microvolt = <1800000>;
  25                 regulator-max-microvolt = <1800000>;
  26                 gpio = <&gpio1 3 0>;   /* gpio_3 */
  27                 startup-delay-us = <70000>;
  28                 enable-active-high;
  29                 vin-supply = <&vmmc2>;
  30         };
  31
  32         /* HS USB Host PHY on PORT 1 */
  33         hsusb2_phy: hsusb2_phy {
  34                 compatible = "usb-nop-xceiv";
  35                 reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
  36         };
  37 };
  38
  39 &gpmc {
  40         ranges = <0 0 0x30000000 0x1000000>;    /* CS0: 16MB for NAND */
  41
  42         nand@0,0 {
  43                 compatible = "ti,omap2-nand";
  44                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  45                 interrupt-parent = <&gpmc>;
  46                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  47                              <1 IRQ_TYPE_NONE>; /* termcount */
  48                 linux,mtd-name = "micron,mt29f4g16abbda3w";
  49                 nand-bus-width = <16>;
  50                 ti,nand-ecc-opt = "bch8";
  51                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  52                 gpmc,sync-clk-ps = <0>;
  53                 gpmc,cs-on-ns = <0>;
  54                 gpmc,cs-rd-off-ns = <44>;
  55                 gpmc,cs-wr-off-ns = <44>;
  56                 gpmc,adv-on-ns = <6>;
  57                 gpmc,adv-rd-off-ns = <34>;
  58                 gpmc,adv-wr-off-ns = <44>;
  59                 gpmc,we-off-ns = <40>;
  60                 gpmc,oe-off-ns = <54>;
  61                 gpmc,access-ns = <64>;
  62                 gpmc,rd-cycle-ns = <82>;
  63                 gpmc,wr-cycle-ns = <82>;
  64                 gpmc,wr-access-ns = <40>;
  65                 gpmc,wr-data-mux-bus-ns = <0>;
  66                 gpmc,device-width = <2>;
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69
  70                 /* u-boot uses mtdparts=omap2-nand.0:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs) */
  71
  72                 x-loader@0 {
  73                         label = "x-loader";
  74                         reg = <0 0x80000>;
  75                 };
  76
  77                 bootloaders@80000 {
  78                         label = "u-boot";
  79                         reg = <0x80000 0x1e0000>;
  80                 };
  81
  82                 bootloaders_env@260000 {
  83                         label = "u-boot-env";
  84                         reg = <0x260000 0x20000>;
  85                 };
  86
  87                 kernel@280000 {
  88                         label = "kernel";
  89                         reg = <0x280000 0x400000>;
  90                 };
  91
  92                 filesystem@680000 {
  93                         label = "fs";
  94                         reg = <0x680000 0>;     /* 0 = MTDPART_SIZ_FULL */
  95                 };
  96         };
  97 };
  98
  99 &i2c1 {
 100         pinctrl-names = "default";
 101         pinctrl-0 = <&i2c1_pins>;
 102         clock-frequency = <2600000>;
 103
 104         twl: twl@48 {
 105                 reg = <0x48>;
 106                 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
 107                 interrupt-parent = <&intc>;
 108                 twl_audio: audio {
 109                         compatible = "ti,twl4030-audio";
 110                         codec {
 111                                 ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
 112                         };
 113                 };
 114         };
 115 };
 116
 117 &i2c2 {
 118         pinctrl-names = "default";
 119         pinctrl-0 = <&i2c2_pins>;
 120         clock-frequency = <400000>;
 121 };
 122
 123 &i2c3 {
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&i2c3_pins>;
 126         clock-frequency = <400000>;
 127 };
 128
 129 &mmc3 {
 130         interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
 131         pinctrl-0 = <&mmc3_pins &wl127x_gpio>;
 132         pinctrl-names = "default";
 133         vmmc-supply = <&wl12xx_vmmc>;
 134         non-removable;
 135         bus-width = <4>;
 136         cap-power-off-card;
 137         #address-cells = <1>;
 138         #size-cells = <0>;
 139         wlcore: wlcore@2 {
 140                 compatible = "ti,wl1273";
 141                 reg = <2>;
 142                 interrupt-parent = <&gpio1>;
 143                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 2 */
 144                 ref-clock-frequency = <26000000>;
 145         };
 146 };
 147
 148 &usbhshost {
 149         port2-mode = "ehci-phy";
 150 };
 151
 152 &usbhsehci {
 153         phys = <0 &hsusb2_phy>;
 154 };
 155
 156
 157 &omap3_pmx_core {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&hsusb2_pins>;
 160
 161         mmc3_pins: pinmux_mm3_pins {
 162                 pinctrl-single,pins = <
 163                         OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */
 164                         OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */
 165                         OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */
 166                         OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */
 167                         OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
 168                         OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */
 169                 >;
 170         };
 171         mcbsp2_pins: pinmux_mcbsp2_pins {
 172                 pinctrl-single,pins = <
 173                         OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx */
 174                         OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_clkx */
 175                         OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr */
 176                         OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dx */
 177                 >;
 178         };
 179         uart2_pins: pinmux_uart2_pins {
 180                 pinctrl-single,pins = <
 181                         OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)        /* uart2_cts.uart2_cts */
 182                         OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)       /* uart2_rts .uart2_rts*/
 183                         OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)       /* uart2_tx.uart2_tx */
 184                         OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)        /* uart2_rx.uart2_rx */
 185                         OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)       /* GPIO_162,BT_EN */
 186                 >;
 187         };
 188         mcspi1_pins: pinmux_mcspi1_pins {
 189                 pinctrl-single,pins = <
 190                         OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk.mcspi1_clk */
 191                         OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_simo.mcspi1_simo */
 192                         OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
 193                         OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_cs0.mcspi1_cs0 */
 194                 >;
 195         };
 196
 197         hsusb2_pins: pinmux_hsusb2_pins {
 198                 pinctrl-single,pins = <
 199                         OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi1_cs3.hsusb2_data2 */
 200                         OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_clk.hsusb2_data7 */
 201                         OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_simo.hsusb2_data4 */
 202                         OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_somi.hsusb2_data5 */
 203                         OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs0.hsusb2_data6 */
 204                         OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs1.hsusb2_data3 */
 205                 >;
 206         };
 207
 208         hsusb_otg_pins: pinmux_hsusb_otg_pins {
 209                 pinctrl-single,pins = <
 210                         OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)        /* hsusb0_clk.hsusb0_clk */
 211                         OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)       /* hsusb0_stp.hsusb0_stp */
 212                         OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)        /* hsusb0_dir.hsusb0_dir */
 213                         OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)        /* hsusb0_nxt.hsusb0_nxt */
 214                         OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)        /* hsusb0_data0.hsusb0_data0 */
 215                         OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)        /* hsusb0_data1.hsusb0_data1 */
 216                         OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)        /* hsusb0_data2.hsusb0_data2 */
 217                         OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)        /* hsusb0_data3.hsusb0_data3 */
 218                         OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)        /* hsusb0_data4.hsusb0_data4 */
 219                         OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)        /* hsusb0_data5.hsusb0_data5 */
 220                         OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)        /* hsusb0_data6.hsusb0_data6 */
 221                         OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)        /* hsusb0_data7.hsusb0_data7 */
 222                 >;
 223         };
 224
 225         i2c1_pins: pinmux_i2c1_pins {
 226                 pinctrl-single,pins = <
 227                         OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)        /* i2c1_scl.i2c1_scl */
 228                         OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)        /* i2c1_sda.i2c1_sda */
 229                         OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4)        /* gpmc_ncs6.gpio_57 */
 230                 >;
 231         };
 232 };
 233
 234 &omap3_pmx_wkup {
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&hsusb2_reset_pin>;
 237         hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
 238                 pinctrl-single,pins = <
 239                         OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4)        /* sys_boot2.gpio_4 */
 240                 >;
 241         };
 242         wl127x_gpio: pinmux_wl127x_gpio_pin {
 243                 pinctrl-single,pins = <
 244                         OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4)         /* sys_boot0.gpio_2 */
 245                         OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4)        /* sys_boot1.gpio_3 */
 246                 >;
 247         };
 248         i2c2_pins: pinmux_i2c2_pins {
 249                 pinctrl-single,pins = <
 250                         OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)        /* i2c2_scl */
 251                         OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)        /* i2c2_sda */
 252                 >;
 253         };
 254         i2c3_pins: pinmux_i2c3_pins {
 255                 pinctrl-single,pins = <
 256                         OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)        /* i2c3_scl */
 257                         OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)        /* i2c3_sda */
 258                 >;
 259         };
 260 };
 261
 262 &omap3_pmx_core2 {
 263         pinctrl-names = "default";
 264         pinctrl-0 = <&hsusb2_2_pins>;
 265         hsusb2_2_pins: pinmux_hsusb2_2_pins {
 266                 pinctrl-single,pins = <
 267                         OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
 268                         OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
 269                         OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
 270                         OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
 271                         OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
 272                         OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
 273                 >;
 274         };
 275 };
 276
 277 &uart2 {
 278         interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
 279         pinctrl-names = "default";
 280         pinctrl-0 = <&uart2_pins>;
 281 };
 282
 283 &mcspi1 {
 284         pinctrl-names = "default";
 285         pinctrl-0 = <&mcspi1_pins>;
 286 };
 287
 288 #include "twl4030.dtsi"
 289 #include "twl4030_omap3.dtsi"
 290
 291 &twl {
 292         twl_power: power {
 293                 compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
 294                 ti,use_poweroff;
 295         };
 296 };
 297
 298 &twl_gpio {
 299         ti,use-leds;
 300 };