GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / meson8b.dtsi
1 /*
2  * Copyright 2015 Endless Mobile, Inc.
3  * Author: Carlo Caione <carlo@endlessm.com>
4  *
5  * This file is dual-licensed: you can use it either under the terms
6  * of the GPL or the X11 license, at your option. Note that this dual
7  * licensing only applies to this file, and not this project as a
8  * whole.
9  *
10  *  a) This library is free software; you can redistribute it and/or
11  *     modify it under the terms of the GNU General Public License as
12  *     published by the Free Software Foundation; either version 2 of the
13  *     License, or (at your option) any later version.
14  *
15  *     This library is distributed in the hope that it will be useful,
16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  *     GNU General Public License for more details.
19  *
20  *     You should have received a copy of the GNU General Public License
21  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
22  *
23  * Or, alternatively,
24  *
25  *  b) Permission is hereby granted, free of charge, to any person
26  *     obtaining a copy of this software and associated documentation
27  *     files (the "Software"), to deal in the Software without
28  *     restriction, including without limitation the rights to use,
29  *     copy, modify, merge, publish, distribute, sublicense, and/or
30  *     sell copies of the Software, and to permit persons to whom the
31  *     Software is furnished to do so, subject to the following
32  *     conditions:
33  *
34  *     The above copyright notice and this permission notice shall be
35  *     included in all copies or substantial portions of the Software.
36  *
37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44  *     OTHER DEALINGS IN THE SOFTWARE.
45  */
46
47 #include <dt-bindings/clock/meson8b-clkc.h>
48 #include <dt-bindings/gpio/meson8b-gpio.h>
49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
50 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
51 #include "meson.dtsi"
52
53 / {
54         cpus {
55                 #address-cells = <1>;
56                 #size-cells = <0>;
57
58                 cpu0: cpu@200 {
59                         device_type = "cpu";
60                         compatible = "arm,cortex-a5";
61                         next-level-cache = <&L2>;
62                         reg = <0x200>;
63                         enable-method = "amlogic,meson8b-smp";
64                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
65                 };
66
67                 cpu1: cpu@201 {
68                         device_type = "cpu";
69                         compatible = "arm,cortex-a5";
70                         next-level-cache = <&L2>;
71                         reg = <0x201>;
72                         enable-method = "amlogic,meson8b-smp";
73                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
74                 };
75
76                 cpu2: cpu@202 {
77                         device_type = "cpu";
78                         compatible = "arm,cortex-a5";
79                         next-level-cache = <&L2>;
80                         reg = <0x202>;
81                         enable-method = "amlogic,meson8b-smp";
82                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
83                 };
84
85                 cpu3: cpu@203 {
86                         device_type = "cpu";
87                         compatible = "arm,cortex-a5";
88                         next-level-cache = <&L2>;
89                         reg = <0x203>;
90                         enable-method = "amlogic,meson8b-smp";
91                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
92                 };
93         };
94
95         pmu {
96                 compatible = "arm,cortex-a5-pmu";
97                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
98                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
99                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
100                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
101                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
102         };
103
104         reserved-memory {
105                 #address-cells = <1>;
106                 #size-cells = <1>;
107                 ranges;
108
109                 /* 2 MiB reserved for Hardware ROM Firmware? */
110                 hwrom@0 {
111                         reg = <0x0 0x200000>;
112                         no-map;
113                 };
114         };
115
116         scu@c4300000 {
117                 compatible = "arm,cortex-a5-scu";
118                 reg = <0xc4300000 0x100>;
119         };
120 }; /* end of / */
121
122 &aobus {
123         pmu: pmu@e0 {
124                 compatible = "amlogic,meson8b-pmu", "syscon";
125                 reg = <0xe0 0x18>;
126         };
127
128         pinctrl_aobus: pinctrl@84 {
129                 compatible = "amlogic,meson8b-aobus-pinctrl";
130                 reg = <0x84 0xc>;
131                 #address-cells = <1>;
132                 #size-cells = <1>;
133                 ranges;
134
135                 gpio_ao: ao-bank@14 {
136                         reg = <0x14 0x4>,
137                                 <0x2c 0x4>,
138                                 <0x24 0x8>;
139                         reg-names = "mux", "pull", "gpio";
140                         gpio-controller;
141                         #gpio-cells = <2>;
142                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
143                 };
144
145                 uart_ao_a_pins: uart_ao_a {
146                         mux {
147                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
148                                 function = "uart_ao";
149                         };
150                 };
151
152                 ir_recv_pins: remote {
153                         mux {
154                                 groups = "remote_input";
155                                 function = "remote";
156                         };
157                 };
158         };
159 };
160
161 &cbus {
162         clkc: clock-controller@4000 {
163                 #clock-cells = <1>;
164                 #reset-cells = <1>;
165                 compatible = "amlogic,meson8b-clkc";
166                 reg = <0x8000 0x4>, <0x4000 0x400>;
167         };
168
169         reset: reset-controller@4404 {
170                 compatible = "amlogic,meson8b-reset";
171                 reg = <0x4404 0x9c>;
172                 #reset-cells = <1>;
173         };
174
175         analog_top: analog-top@81a8 {
176                 compatible = "amlogic,meson8b-analog-top", "syscon";
177                 reg = <0x81a8 0x14>;
178         };
179
180         pwm_ef: pwm@86c0 {
181                 compatible = "amlogic,meson8b-pwm";
182                 reg = <0x86c0 0x10>;
183                 #pwm-cells = <3>;
184                 status = "disabled";
185         };
186
187         pinctrl_cbus: pinctrl@9880 {
188                 compatible = "amlogic,meson8b-cbus-pinctrl";
189                 reg = <0x9880 0x10>;
190                 #address-cells = <1>;
191                 #size-cells = <1>;
192                 ranges;
193
194                 gpio: banks@80b0 {
195                         reg = <0x80b0 0x28>,
196                                 <0x80e8 0x18>,
197                                 <0x8120 0x18>,
198                                 <0x8030 0x38>;
199                         reg-names = "mux", "pull", "pull-enable", "gpio";
200                         gpio-controller;
201                         #gpio-cells = <2>;
202                         gpio-ranges = <&pinctrl_cbus 0 0 83>;
203                 };
204
205                 eth_rgmii_pins: eth-rgmii {
206                         mux {
207                                 groups = "eth_tx_clk",
208                                          "eth_tx_en",
209                                          "eth_txd1_0",
210                                          "eth_txd0_0",
211                                          "eth_rx_clk",
212                                          "eth_rx_dv",
213                                          "eth_rxd1",
214                                          "eth_rxd0",
215                                          "eth_mdio_en",
216                                          "eth_mdc",
217                                          "eth_ref_clk",
218                                          "eth_txd2",
219                                          "eth_txd3",
220                                          "eth_rxd3",
221                                          "eth_rxd2";
222                                 function = "ethernet";
223                         };
224                 };
225
226                 sd_b_pins: sd-b {
227                         mux {
228                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
229                                         "sd_d3_b", "sd_clk_b", "sd_cmd_b";
230                                 function = "sd_b";
231                         };
232                 };
233         };
234 };
235
236 &ahb_sram {
237         smp-sram@1ff80 {
238                 compatible = "amlogic,meson8b-smp-sram";
239                 reg = <0x1ff80 0x8>;
240         };
241 };
242
243
244 &efuse {
245         compatible = "amlogic,meson8b-efuse";
246         clocks = <&clkc CLKID_EFUSE>;
247         clock-names = "core";
248 };
249
250 &ethmac {
251         compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
252
253         reg = <0xc9410000 0x10000
254                0xc1108140 0x4>;
255
256         clocks = <&clkc CLKID_ETH>,
257                  <&clkc CLKID_MPLL2>,
258                  <&clkc CLKID_MPLL2>;
259         clock-names = "stmmaceth", "clkin0", "clkin1";
260
261         resets = <&reset RESET_ETHERNET>;
262         reset-names = "stmmaceth";
263 };
264
265 &gpio_intc {
266         compatible = "amlogic,meson-gpio-intc",
267                      "amlogic,meson8b-gpio-intc";
268         status = "okay";
269 };
270
271 &hwrng {
272         compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
273         clocks = <&clkc CLKID_RNG0>;
274         clock-names = "core";
275 };
276
277 &i2c_AO {
278         clocks = <&clkc CLKID_CLK81>;
279 };
280
281 &i2c_A {
282         clocks = <&clkc CLKID_I2C>;
283 };
284
285 &i2c_B {
286         clocks = <&clkc CLKID_I2C>;
287 };
288
289 &L2 {
290         arm,data-latency = <3 3 3>;
291         arm,tag-latency = <2 2 2>;
292         arm,filter-ranges = <0x100000 0xc0000000>;
293         prefetch-data = <1>;
294         prefetch-instr = <1>;
295         arm,shared-override;
296 };
297
298 &pwm_ab {
299         compatible = "amlogic,meson8b-pwm";
300 };
301
302 &pwm_cd {
303         compatible = "amlogic,meson8b-pwm";
304 };
305
306 &saradc {
307         compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
308         clocks = <&clkc CLKID_XTAL>,
309                 <&clkc CLKID_SAR_ADC>;
310         clock-names = "clkin", "core";
311 };
312
313 &sdio {
314         compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
315         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
316         clock-names = "core", "clkin";
317 };
318
319 &uart_AO {
320         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
321         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
322         clock-names = "baud", "xtal", "pclk";
323 };
324
325 &uart_A {
326         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
327         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
328         clock-names = "baud", "xtal", "pclk";
329 };
330
331 &uart_B {
332         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
333         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
334         clock-names = "baud", "xtal", "pclk";
335 };
336
337 &uart_C {
338         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
339         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
340         clock-names = "baud", "xtal", "pclk";
341 };
342
343 &usb0 {
344         compatible = "amlogic,meson8b-usb", "snps,dwc2";
345         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
346         clock-names = "otg";
347 };
348
349 &usb1 {
350         compatible = "amlogic,meson8b-usb", "snps,dwc2";
351         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
352         clock-names = "otg";
353 };
354
355 &usb0_phy {
356         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
357         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
358         clock-names = "usb_general", "usb";
359         resets = <&reset RESET_USB_OTG>;
360 };
361
362 &usb1_phy {
363         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
364         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
365         clock-names = "usb_general", "usb";
366         resets = <&reset RESET_USB_OTG>;
367 };
368
369 &wdt {
370         compatible = "amlogic,meson8b-wdt";
371 };