arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/bus/ti-sysc.h>
  10 #include <dt-bindings/clock/omap4.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/pinctrl/omap.h>
  14 #include <dt-bindings/clock/omap4.h>
  15
  16 / {
  17         compatible = "ti,omap4430", "ti,omap4";
  18         interrupt-parent = <&wakeupgen>;
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21         chosen { };
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 mmc0 = &mmc1;
  29                 mmc1 = &mmc2;
  30                 mmc2 = &mmc3;
  31                 mmc3 = &mmc4;
  32                 mmc4 = &mmc5;
  33                 serial0 = &uart1;
  34                 serial1 = &uart2;
  35                 serial2 = &uart3;
  36                 serial3 = &uart4;
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42
  43                 cpu@0 {
  44                         compatible = "arm,cortex-a9";
  45                         device_type = "cpu";
  46                         next-level-cache = <&L2>;
  47                         reg = <0x0>;
  48
  49                         clocks = <&dpll_mpu_ck>;
  50                         clock-names = "cpu";
  51
  52                         clock-latency = <300000>; /* From omap-cpufreq driver */
  53                 };
  54                 cpu@1 {
  55                         compatible = "arm,cortex-a9";
  56                         device_type = "cpu";
  57                         next-level-cache = <&L2>;
  58                         reg = <0x1>;
  59                 };
  60         };
  61
  62         /*
  63          * Note that 4430 needs cross trigger interface (CTI) supported
  64          * before we can configure the interrupts. This means sampling
  65          * events are not supported for pmu. Note that 4460 does not use
  66          * CTI, see also 4460.dtsi.
  67          */
  68         pmu {
  69                 compatible = "arm,cortex-a9-pmu";
  70                 ti,hwmods = "debugss";
  71         };
  72
  73         gic: interrupt-controller@48241000 {
  74                 compatible = "arm,cortex-a9-gic";
  75                 interrupt-controller;
  76                 #interrupt-cells = <3>;
  77                 reg = <0x48241000 0x1000>,
  78                       <0x48240100 0x0100>;
  79                 interrupt-parent = <&gic>;
  80         };
  81
  82         L2: l2-cache-controller@48242000 {
  83                 compatible = "arm,pl310-cache";
  84                 reg = <0x48242000 0x1000>;
  85                 cache-unified;
  86                 cache-level = <2>;
  87         };
  88
  89         local-timer@48240600 {
  90                 compatible = "arm,cortex-a9-twd-timer";
  91                 clocks = <&mpu_periphclk>;
  92                 reg = <0x48240600 0x20>;
  93                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
  94                 interrupt-parent = <&gic>;
  95         };
  96
  97         wakeupgen: interrupt-controller@48281000 {
  98                 compatible = "ti,omap4-wugen-mpu";
  99                 interrupt-controller;
 100                 #interrupt-cells = <3>;
 101                 reg = <0x48281000 0x1000>;
 102                 interrupt-parent = <&gic>;
 103         };
 104
 105         /*
 106          * The soc node represents the soc top level view. It is used for IPs
 107          * that are not memory mapped in the MPU view or for the MPU itself.
 108          */
 109         soc {
 110                 compatible = "ti,omap-infra";
 111                 mpu {
 112                         compatible = "ti,omap4-mpu";
 113                         ti,hwmods = "mpu";
 114                         sram = <&ocmcram>;
 115                 };
 116
 117                 dsp {
 118                         compatible = "ti,omap3-c64";
 119                         ti,hwmods = "dsp";
 120                 };
 121
 122                 iva {
 123                         compatible = "ti,ivahd";
 124                         ti,hwmods = "iva";
 125                 };
 126         };
 127
 128         /*
 129          * XXX: Use a flat representation of the OMAP4 interconnect.
 130          * The real OMAP interconnect network is quite complex.
 131          * Since it will not bring real advantage to represent that in DT for
 132          * the moment, just use a fake OCP bus entry to represent the whole bus
 133          * hierarchy.
 134          */
 135         ocp {
 136                 compatible = "ti,omap4-l3-noc", "simple-bus";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 ranges;
 140                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 141                 reg = <0x44000000 0x1000>,
 142                       <0x44800000 0x2000>,
 143                       <0x45000000 0x1000>;
 144                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 146
 147                 l4_wkup: interconnect@4a300000 {
 148                 };
 149
 150                 l4_cfg: interconnect@4a000000 {
 151                 };
 152
 153                 l4_per: interconnect@48000000 {
 154                 };
 155
 156                 ocmcram: ocmcram@40304000 {
 157                         compatible = "mmio-sram";
 158                         reg = <0x40304000 0xa000>; /* 40k */
 159                 };
 160
 161                 gpmc: gpmc@50000000 {
 162                         compatible = "ti,omap4430-gpmc";
 163                         reg = <0x50000000 0x1000>;
 164                         #address-cells = <2>;
 165                         #size-cells = <1>;
 166                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 167                         dmas = <&sdma 4>;
 168                         dma-names = "rxtx";
 169                         gpmc,num-cs = <8>;
 170                         gpmc,num-waitpins = <4>;
 171                         ti,hwmods = "gpmc";
 172                         ti,no-idle-on-init;
 173                         clocks = <&l3_div_ck>;
 174                         clock-names = "fck";
 175                         interrupt-controller;
 176                         #interrupt-cells = <2>;
 177                         gpio-controller;
 178                         #gpio-cells = <2>;
 179                 };
 180
 181                 mmu_dsp: mmu@4a066000 {
 182                         compatible = "ti,omap4-iommu";
 183                         reg = <0x4a066000 0x100>;
 184                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 185                         ti,hwmods = "mmu_dsp";
 186                         #iommu-cells = <0>;
 187                 };
 188
 189                 target-module@52000000 {
 190                         compatible = "ti,sysc-omap4", "ti,sysc";
 191                         ti,hwmods = "iss";
 192                         reg = <0x52000000 0x4>,
 193                               <0x52000010 0x4>;
 194                         reg-names = "rev", "sysc";
 195                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 196                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 197                                         <SYSC_IDLE_NO>,
 198                                         <SYSC_IDLE_SMART>,
 199                                         <SYSC_IDLE_SMART_WKUP>;
 200                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 201                                         <SYSC_IDLE_NO>,
 202                                         <SYSC_IDLE_SMART>,
 203                                         <SYSC_IDLE_SMART_WKUP>;
 204                         ti,sysc-delay-us = <2>;
 205                         clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
 206                         clock-names = "fck";
 207                         #address-cells = <1>;
 208                         #size-cells = <1>;
 209                         ranges = <0 0x52000000 0x1000000>;
 210
 211                         /* No child device binding, driver in staging */
 212                 };
 213
 214                 mmu_ipu: mmu@55082000 {
 215                         compatible = "ti,omap4-iommu";
 216                         reg = <0x55082000 0x100>;
 217                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 218                         ti,hwmods = "mmu_ipu";
 219                         #iommu-cells = <0>;
 220                         ti,iommu-bus-err-back;
 221                 };
 222                 target-module@40130000 {
 223                         compatible = "ti,sysc-omap2", "ti,sysc";
 224                         ti,hwmods = "wd_timer3";
 225                         reg = <0x40130000 0x4>,
 226                               <0x40130010 0x4>,
 227                               <0x40130014 0x4>;
 228                         reg-names = "rev", "sysc", "syss";
 229                         ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
 230                                          SYSC_OMAP2_SOFTRESET)>;
 231                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 232                                         <SYSC_IDLE_NO>,
 233                                         <SYSC_IDLE_SMART>,
 234                                         <SYSC_IDLE_SMART_WKUP>;
 235                         ti,syss-mask = <1>;
 236                         /* Domains (V, P, C): abe, abe_pwrdm, abe_clkdm */
 237                         clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
 238                         clock-names = "fck";
 239                         #address-cells = <1>;
 240                         #size-cells = <1>;
 241                         ranges = <0x00000000 0x40130000 0x1000>, /* MPU private access */
 242                                  <0x49030000 0x49030000 0x0080>; /* L3 Interconnect */
 243
 244                         wdt3: wdt@0 {
 245                                 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 246                                 reg = <0x0 0x80>;
 247                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 248                         };
 249                 };
 250
 251                 mcpdm: mcpdm@40132000 {
 252                         compatible = "ti,omap4-mcpdm";
 253                         reg = <0x40132000 0x7f>, /* MPU private access */
 254                               <0x49032000 0x7f>; /* L3 Interconnect */
 255                         reg-names = "mpu", "dma";
 256                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 257                         ti,hwmods = "mcpdm";
 258                         dmas = <&sdma 65>,
 259                                <&sdma 66>;
 260                         dma-names = "up_link", "dn_link";
 261                         status = "disabled";
 262                 };
 263
 264                 dmic: dmic@4012e000 {
 265                         compatible = "ti,omap4-dmic";
 266                         reg = <0x4012e000 0x7f>, /* MPU private access */
 267                               <0x4902e000 0x7f>; /* L3 Interconnect */
 268                         reg-names = "mpu", "dma";
 269                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 270                         ti,hwmods = "dmic";
 271                         dmas = <&sdma 67>;
 272                         dma-names = "up_link";
 273                         status = "disabled";
 274                 };
 275
 276                 mcbsp1: mcbsp@40122000 {
 277                         compatible = "ti,omap4-mcbsp";
 278                         reg = <0x40122000 0xff>, /* MPU private access */
 279                               <0x49022000 0xff>; /* L3 Interconnect */
 280                         reg-names = "mpu", "dma";
 281                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 282                         interrupt-names = "common";
 283                         ti,buffer-size = <128>;
 284                         ti,hwmods = "mcbsp1";
 285                         dmas = <&sdma 33>,
 286                                <&sdma 34>;
 287                         dma-names = "tx", "rx";
 288                         status = "disabled";
 289                 };
 290
 291                 mcbsp2: mcbsp@40124000 {
 292                         compatible = "ti,omap4-mcbsp";
 293                         reg = <0x40124000 0xff>, /* MPU private access */
 294                               <0x49024000 0xff>; /* L3 Interconnect */
 295                         reg-names = "mpu", "dma";
 296                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 297                         interrupt-names = "common";
 298                         ti,buffer-size = <128>;
 299                         ti,hwmods = "mcbsp2";
 300                         dmas = <&sdma 17>,
 301                                <&sdma 18>;
 302                         dma-names = "tx", "rx";
 303                         status = "disabled";
 304                 };
 305
 306                 mcbsp3: mcbsp@40126000 {
 307                         compatible = "ti,omap4-mcbsp";
 308                         reg = <0x40126000 0xff>, /* MPU private access */
 309                               <0x49026000 0xff>; /* L3 Interconnect */
 310                         reg-names = "mpu", "dma";
 311                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 312                         interrupt-names = "common";
 313                         ti,buffer-size = <128>;
 314                         ti,hwmods = "mcbsp3";
 315                         dmas = <&sdma 19>,
 316                                <&sdma 20>;
 317                         dma-names = "tx", "rx";
 318                         status = "disabled";
 319                 };
 320
 321                 target-module@40128000 {
 322                         compatible = "ti,sysc-mcasp", "ti,sysc";
 323                         ti,hwmods = "mcasp";
 324                         reg = <0x40128000 0x4>,
 325                               <0x40128004 0x4>;
 326                         reg-names = "rev", "sysc";
 327                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 328                                         <SYSC_IDLE_NO>,
 329                                         <SYSC_IDLE_SMART>,
 330                                         <SYSC_IDLE_SMART_WKUP>;
 331                         clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
 332                         clock-names = "fck";
 333                         #address-cells = <1>;
 334                         #size-cells = <1>;
 335                         ranges = <0x00000000 0x40128000 0x1000>, /* MPU */
 336                                  <0x49028000 0x49028000 0x1000>; /* L3 */
 337
 338                         /*
 339                          * Child device unsupported by davinci-mcasp. At least
 340                          * RX path is disabled for omap4, and only DIT mode
 341                          * works with no I2S. See also old Android kernel
 342                          * omap-mcasp driver for more information.
 343                          */
 344                 };
 345
 346                 target-module@4012c000 {
 347                         compatible = "ti,sysc-omap4", "ti,sysc";
 348                         ti,hwmods = "slimbus1";
 349                         reg = <0x4012c000 0x4>,
 350                               <0x4012c010 0x4>;
 351                         reg-names = "rev", "sysc";
 352                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 353                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 354                                         <SYSC_IDLE_NO>,
 355                                         <SYSC_IDLE_SMART>,
 356                                         <SYSC_IDLE_SMART_WKUP>;
 357                         clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
 358                         clock-names = "fck";
 359                         #address-cells = <1>;
 360                         #size-cells = <1>;
 361                         ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
 362                                  <0x4902c000 0x4902c000 0x1000>; /* L3 */
 363
 364                         /* No child device binding or driver in mainline */
 365                 };
 366
 367                 target-module@401f1000 {
 368                         compatible = "ti,sysc-omap4", "ti,sysc";
 369                         ti,hwmods = "aess";
 370                         reg = <0x401f1000 0x4>,
 371                               <0x401f1010 0x4>;
 372                         reg-names = "rev", "sysc";
 373                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 374                                         <SYSC_IDLE_NO>,
 375                                         <SYSC_IDLE_SMART>,
 376                                         <SYSC_IDLE_SMART_WKUP>;
 377                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 378                                         <SYSC_IDLE_NO>,
 379                                         <SYSC_IDLE_SMART>;
 380                         clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
 381                         clock-names = "fck";
 382                         #address-cells = <1>;
 383                         #size-cells = <1>;
 384                         ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */
 385                                  <0x490f1000 0x490f1000 0x1000>; /* L3 */
 386
 387                         /*
 388                          * No child device binding or driver in mainline.
 389                          * See Android tree and related upstreaming efforts
 390                          * for the old driver.
 391                          */
 392                 };
 393
 394                 dmm@4e000000 {
 395                         compatible = "ti,omap4-dmm";
 396                         reg = <0x4e000000 0x800>;
 397                         interrupts = <0 113 0x4>;
 398                         ti,hwmods = "dmm";
 399                 };
 400
 401                 emif1: emif@4c000000 {
 402                         compatible = "ti,emif-4d";
 403                         reg = <0x4c000000 0x100>;
 404                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 405                         ti,hwmods = "emif1";
 406                         ti,no-idle-on-init;
 407                         phy-type = <1>;
 408                         hw-caps-read-idle-ctrl;
 409                         hw-caps-ll-interface;
 410                         hw-caps-temp-alert;
 411                 };
 412
 413                 emif2: emif@4d000000 {
 414                         compatible = "ti,emif-4d";
 415                         reg = <0x4d000000 0x100>;
 416                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 417                         ti,hwmods = "emif2";
 418                         ti,no-idle-on-init;
 419                         phy-type = <1>;
 420                         hw-caps-read-idle-ctrl;
 421                         hw-caps-ll-interface;
 422                         hw-caps-temp-alert;
 423                 };
 424
 425                 timer5: timer@40138000 {
 426                         compatible = "ti,omap4430-timer";
 427                         reg = <0x40138000 0x80>,
 428                               <0x49038000 0x80>;
 429                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 430                         ti,hwmods = "timer5";
 431                         ti,timer-dsp;
 432                 };
 433
 434                 timer6: timer@4013a000 {
 435                         compatible = "ti,omap4430-timer";
 436                         reg = <0x4013a000 0x80>,
 437                               <0x4903a000 0x80>;
 438                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 439                         ti,hwmods = "timer6";
 440                         ti,timer-dsp;
 441                 };
 442
 443                 timer7: timer@4013c000 {
 444                         compatible = "ti,omap4430-timer";
 445                         reg = <0x4013c000 0x80>,
 446                               <0x4903c000 0x80>;
 447                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 448                         ti,hwmods = "timer7";
 449                         ti,timer-dsp;
 450                 };
 451
 452                 timer8: timer@4013e000 {
 453                         compatible = "ti,omap4430-timer";
 454                         reg = <0x4013e000 0x80>,
 455                               <0x4903e000 0x80>;
 456                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 457                         ti,hwmods = "timer8";
 458                         ti,timer-pwm;
 459                         ti,timer-dsp;
 460                 };
 461
 462                 aes1: aes@4b501000 {
 463                         compatible = "ti,omap4-aes";
 464                         ti,hwmods = "aes1";
 465                         reg = <0x4b501000 0xa0>;
 466                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 467                         dmas = <&sdma 111>, <&sdma 110>;
 468                         dma-names = "tx", "rx";
 469                 };
 470
 471                 aes2: aes@4b701000 {
 472                         compatible = "ti,omap4-aes";
 473                         ti,hwmods = "aes2";
 474                         reg = <0x4b701000 0xa0>;
 475                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 476                         dmas = <&sdma 114>, <&sdma 113>;
 477                         dma-names = "tx", "rx";
 478                 };
 479
 480                 des: des@480a5000 {
 481                         compatible = "ti,omap4-des";
 482                         ti,hwmods = "des";
 483                         reg = <0x480a5000 0xa0>;
 484                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 485                         dmas = <&sdma 117>, <&sdma 116>;
 486                         dma-names = "tx", "rx";
 487                 };
 488
 489                 sham: sham@4b100000 {
 490                         compatible = "ti,omap4-sham";
 491                         ti,hwmods = "sham";
 492                         reg = <0x4b100000 0x300>;
 493                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 494                         dmas = <&sdma 119>;
 495                         dma-names = "rx";
 496                 };
 497
 498                 abb_mpu: regulator-abb-mpu {
 499                         compatible = "ti,abb-v2";
 500                         regulator-name = "abb_mpu";
 501                         #address-cells = <0>;
 502                         #size-cells = <0>;
 503                         ti,tranxdone-status-mask = <0x80>;
 504                         clocks = <&sys_clkin_ck>;
 505                         ti,settling-time = <50>;
 506                         ti,clock-cycles = <16>;
 507
 508                         status = "disabled";
 509                 };
 510
 511                 abb_iva: regulator-abb-iva {
 512                         compatible = "ti,abb-v2";
 513                         regulator-name = "abb_iva";
 514                         #address-cells = <0>;
 515                         #size-cells = <0>;
 516                         ti,tranxdone-status-mask = <0x80000000>;
 517                         clocks = <&sys_clkin_ck>;
 518                         ti,settling-time = <50>;
 519                         ti,clock-cycles = <16>;
 520
 521                         status = "disabled";
 522                 };
 523
 524                 sgx_module: target-module@56000000 {
 525                         compatible = "ti,sysc-omap4", "ti,sysc";
 526                         ti,hwmods = "gpu";
 527                         reg = <0x5601fc00 0x4>,
 528                               <0x5601fc10 0x4>;
 529                         reg-names = "rev", "sysc";
 530                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 531                                         <SYSC_IDLE_NO>,
 532                                         <SYSC_IDLE_SMART>,
 533                                         <SYSC_IDLE_SMART_WKUP>;
 534                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 535                                         <SYSC_IDLE_NO>,
 536                                         <SYSC_IDLE_SMART>,
 537                                         <SYSC_IDLE_SMART_WKUP>;
 538                         clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
 539                         clock-names = "fck";
 540                         #address-cells = <1>;
 541                         #size-cells = <1>;
 542                         ranges = <0 0x56000000 0x2000000>;
 543
 544                         /*
 545                          * Closed source PowerVR driver, no child device
 546                          * binding or driver in mainline
 547                          */
 548                 };
 549
 550                 dss: dss@58000000 {
 551                         compatible = "ti,omap4-dss";
 552                         reg = <0x58000000 0x80>;
 553                         status = "disabled";
 554                         ti,hwmods = "dss_core";
 555                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
 556                         clock-names = "fck";
 557                         #address-cells = <1>;
 558                         #size-cells = <1>;
 559                         ranges;
 560
 561                         dispc@58001000 {
 562                                 compatible = "ti,omap4-dispc";
 563                                 reg = <0x58001000 0x1000>;
 564                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 565                                 ti,hwmods = "dss_dispc";
 566                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
 567                                 clock-names = "fck";
 568                         };
 569
 570                         rfbi: encoder@58002000  {
 571                                 compatible = "ti,omap4-rfbi";
 572                                 reg = <0x58002000 0x1000>;
 573                                 status = "disabled";
 574                                 ti,hwmods = "dss_rfbi";
 575                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
 576                                 clock-names = "fck", "ick";
 577                         };
 578
 579                         venc: encoder@58003000 {
 580                                 compatible = "ti,omap4-venc";
 581                                 reg = <0x58003000 0x1000>;
 582                                 status = "disabled";
 583                                 ti,hwmods = "dss_venc";
 584                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
 585                                 clock-names = "fck";
 586                         };
 587
 588                         dsi1: encoder@58004000 {
 589                                 compatible = "ti,omap4-dsi";
 590                                 reg = <0x58004000 0x200>,
 591                                       <0x58004200 0x40>,
 592                                       <0x58004300 0x20>;
 593                                 reg-names = "proto", "phy", "pll";
 594                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 595                                 status = "disabled";
 596                                 ti,hwmods = "dss_dsi1";
 597                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 598                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 599                                 clock-names = "fck", "sys_clk";
 600                         };
 601
 602                         dsi2: encoder@58005000 {
 603                                 compatible = "ti,omap4-dsi";
 604                                 reg = <0x58005000 0x200>,
 605                                       <0x58005200 0x40>,
 606                                       <0x58005300 0x20>;
 607                                 reg-names = "proto", "phy", "pll";
 608                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 609                                 status = "disabled";
 610                                 ti,hwmods = "dss_dsi2";
 611                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 612                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 613                                 clock-names = "fck", "sys_clk";
 614                         };
 615
 616                         hdmi: encoder@58006000 {
 617                                 compatible = "ti,omap4-hdmi";
 618                                 reg = <0x58006000 0x200>,
 619                                       <0x58006200 0x100>,
 620                                       <0x58006300 0x100>,
 621                                       <0x58006400 0x1000>;
 622                                 reg-names = "wp", "pll", "phy", "core";
 623                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 624                                 status = "disabled";
 625                                 ti,hwmods = "dss_hdmi";
 626                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
 627                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 628                                 clock-names = "fck", "sys_clk";
 629                                 dmas = <&sdma 76>;
 630                                 dma-names = "audio_tx";
 631                         };
 632                 };
 633         };
 634 };
 635
 636 #include "omap4-l4.dtsi"
 637 #include "omap44xx-clocks.dtsi"