GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / qcom-msm8960.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 /include/ "skeleton.dtsi"
5
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
8 #include <dt-bindings/mfd/qcom-rpm.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10
11 / {
12         model = "Qualcomm MSM8960";
13         compatible = "qcom,msm8960";
14         interrupt-parent = <&intc>;
15
16         cpus {
17                 #address-cells = <1>;
18                 #size-cells = <0>;
19                 interrupts = <1 14 0x304>;
20
21                 cpu@0 {
22                         compatible = "qcom,krait";
23                         enable-method = "qcom,kpss-acc-v1";
24                         device_type = "cpu";
25                         reg = <0>;
26                         next-level-cache = <&L2>;
27                         qcom,acc = <&acc0>;
28                         qcom,saw = <&saw0>;
29                 };
30
31                 cpu@1 {
32                         compatible = "qcom,krait";
33                         enable-method = "qcom,kpss-acc-v1";
34                         device_type = "cpu";
35                         reg = <1>;
36                         next-level-cache = <&L2>;
37                         qcom,acc = <&acc1>;
38                         qcom,saw = <&saw1>;
39                 };
40
41                 L2: l2-cache {
42                         compatible = "cache";
43                         cache-level = <2>;
44                 };
45         };
46
47         cpu-pmu {
48                 compatible = "qcom,krait-pmu";
49                 interrupts = <1 10 0x304>;
50                 qcom,no-pc-write;
51         };
52
53         clocks {
54                 cxo_board {
55                         compatible = "fixed-clock";
56                         #clock-cells = <0>;
57                         clock-frequency = <19200000>;
58                         clock-output-names = "cxo_board";
59                 };
60
61                 pxo_board {
62                         compatible = "fixed-clock";
63                         #clock-cells = <0>;
64                         clock-frequency = <27000000>;
65                         clock-output-names = "pxo_board";
66                 };
67
68                 sleep_clk {
69                         compatible = "fixed-clock";
70                         #clock-cells = <0>;
71                         clock-frequency = <32768>;
72                         clock-output-names = "sleep_clk";
73                 };
74         };
75
76         soc: soc {
77                 #address-cells = <1>;
78                 #size-cells = <1>;
79                 ranges;
80                 compatible = "simple-bus";
81
82                 intc: interrupt-controller@2000000 {
83                         compatible = "qcom,msm-qgic2";
84                         interrupt-controller;
85                         #interrupt-cells = <3>;
86                         reg = <0x02000000 0x1000>,
87                               <0x02002000 0x1000>;
88                 };
89
90                 timer@200a000 {
91                         compatible = "qcom,kpss-timer",
92                                      "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
93                         interrupts = <1 1 0x301>,
94                                      <1 2 0x301>,
95                                      <1 3 0x301>;
96                         reg = <0x0200a000 0x100>;
97                         clock-frequency = <27000000>,
98                                           <32768>;
99                         cpu-offset = <0x80000>;
100                 };
101
102                 msmgpio: pinctrl@800000 {
103                         compatible = "qcom,msm8960-pinctrl";
104                         gpio-controller;
105                         #gpio-cells = <2>;
106                         interrupts = <0 16 0x4>;
107                         interrupt-controller;
108                         #interrupt-cells = <2>;
109                         reg = <0x800000 0x4000>;
110                 };
111
112                 gcc: clock-controller@900000 {
113                         compatible = "qcom,gcc-msm8960";
114                         #clock-cells = <1>;
115                         #reset-cells = <1>;
116                         reg = <0x900000 0x4000>;
117                 };
118
119                 lcc: clock-controller@28000000 {
120                         compatible = "qcom,lcc-msm8960";
121                         reg = <0x28000000 0x1000>;
122                         #clock-cells = <1>;
123                         #reset-cells = <1>;
124                 };
125
126                 clock-controller@4000000 {
127                         compatible = "qcom,mmcc-msm8960";
128                         reg = <0x4000000 0x1000>;
129                         #clock-cells = <1>;
130                         #reset-cells = <1>;
131                 };
132
133                 l2cc: clock-controller@2011000 {
134                         compatible      = "syscon";
135                         reg             = <0x2011000 0x1000>;
136                 };
137
138                 rpm@108000 {
139                         compatible      = "qcom,rpm-msm8960";
140                         reg             = <0x108000 0x1000>;
141                         qcom,ipc        = <&l2cc 0x8 2>;
142
143                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
144                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
145                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
146                         interrupt-names = "ack", "err", "wakeup";
147
148                         regulators {
149                                 compatible = "qcom,rpm-pm8921-regulators";
150                         };
151                 };
152
153                 acc0: clock-controller@2088000 {
154                         compatible = "qcom,kpss-acc-v1";
155                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
156                 };
157
158                 acc1: clock-controller@2098000 {
159                         compatible = "qcom,kpss-acc-v1";
160                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
161                 };
162
163                 saw0: regulator@2089000 {
164                         compatible = "qcom,saw2";
165                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
166                         regulator;
167                 };
168
169                 saw1: regulator@2099000 {
170                         compatible = "qcom,saw2";
171                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
172                         regulator;
173                 };
174
175                 gsbi5: gsbi@16400000 {
176                         compatible = "qcom,gsbi-v1.0.0";
177                         cell-index = <5>;
178                         reg = <0x16400000 0x100>;
179                         clocks = <&gcc GSBI5_H_CLK>;
180                         clock-names = "iface";
181                         #address-cells = <1>;
182                         #size-cells = <1>;
183                         ranges;
184
185                         syscon-tcsr = <&tcsr>;
186
187                         gsbi5_serial: serial@16440000 {
188                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
189                                 reg = <0x16440000 0x1000>,
190                                       <0x16400000 0x1000>;
191                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
192                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
193                                 clock-names = "core", "iface";
194                                 status = "disabled";
195                         };
196                 };
197
198                 qcom,ssbi@500000 {
199                         compatible = "qcom,ssbi";
200                         reg = <0x500000 0x1000>;
201                         qcom,controller-type = "pmic-arbiter";
202
203                         pmicintc: pmic@0 {
204                                 compatible = "qcom,pm8921";
205                                 interrupt-parent = <&msmgpio>;
206                                 interrupts = <104 8>;
207                                 #interrupt-cells = <2>;
208                                 interrupt-controller;
209                                 #address-cells = <1>;
210                                 #size-cells = <0>;
211
212                                 pwrkey@1c {
213                                         compatible = "qcom,pm8921-pwrkey";
214                                         reg = <0x1c>;
215                                         interrupt-parent = <&pmicintc>;
216                                         interrupts = <50 1>, <51 1>;
217                                         debounce = <15625>;
218                                         pull-up;
219                                 };
220
221                                 keypad@148 {
222                                         compatible = "qcom,pm8921-keypad";
223                                         reg = <0x148>;
224                                         interrupt-parent = <&pmicintc>;
225                                         interrupts = <74 1>, <75 1>;
226                                         debounce = <15>;
227                                         scan-delay = <32>;
228                                         row-hold = <91500>;
229                                 };
230
231                                 rtc@11d {
232                                         compatible = "qcom,pm8921-rtc";
233                                         interrupt-parent = <&pmicintc>;
234                                         interrupts = <39 1>;
235                                         reg = <0x11d>;
236                                         allow-set-time;
237                                 };
238                         };
239                 };
240
241                 rng@1a500000 {
242                         compatible = "qcom,prng";
243                         reg = <0x1a500000 0x200>;
244                         clocks = <&gcc PRNG_CLK>;
245                         clock-names = "core";
246                 };
247
248                 /* Temporary fixed regulator */
249                 vsdcc_fixed: vsdcc-regulator {
250                         compatible = "regulator-fixed";
251                         regulator-name = "SDCC Power";
252                         regulator-min-microvolt = <2700000>;
253                         regulator-max-microvolt = <2700000>;
254                         regulator-always-on;
255                 };
256
257                 amba {
258                         compatible = "simple-bus";
259                         #address-cells = <1>;
260                         #size-cells = <1>;
261                         ranges;
262                         sdcc1: sdcc@12400000 {
263                                 status          = "disabled";
264                                 compatible      = "arm,pl18x", "arm,primecell";
265                                 arm,primecell-periphid = <0x00051180>;
266                                 reg             = <0x12400000 0x8000>;
267                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
268                                 interrupt-names = "cmd_irq";
269                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
270                                 clock-names     = "mclk", "apb_pclk";
271                                 bus-width       = <8>;
272                                 max-frequency   = <96000000>;
273                                 non-removable;
274                                 cap-sd-highspeed;
275                                 cap-mmc-highspeed;
276                                 vmmc-supply = <&vsdcc_fixed>;
277                         };
278
279                         sdcc3: sdcc@12180000 {
280                                 compatible      = "arm,pl18x", "arm,primecell";
281                                 arm,primecell-periphid = <0x00051180>;
282                                 status          = "disabled";
283                                 reg             = <0x12180000 0x8000>;
284                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
285                                 interrupt-names = "cmd_irq";
286                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
287                                 clock-names     = "mclk", "apb_pclk";
288                                 bus-width       = <4>;
289                                 cap-sd-highspeed;
290                                 cap-mmc-highspeed;
291                                 max-frequency   = <192000000>;
292                                 no-1-8-v;
293                                 vmmc-supply = <&vsdcc_fixed>;
294                         };
295                 };
296
297                 tcsr: syscon@1a400000 {
298                         compatible = "qcom,tcsr-msm8960", "syscon";
299                         reg = <0x1a400000 0x100>;
300                 };
301
302                 gsbi@16000000 {
303                         compatible = "qcom,gsbi-v1.0.0";
304                         cell-index = <1>;
305                         reg = <0x16000000 0x100>;
306                         clocks = <&gcc GSBI1_H_CLK>;
307                         clock-names = "iface";
308                         #address-cells = <1>;
309                         #size-cells = <1>;
310                         ranges;
311
312                         spi@16080000 {
313                                 compatible = "qcom,spi-qup-v1.1.1";
314                                 #address-cells = <1>;
315                                 #size-cells = <0>;
316                                 reg = <0x16080000 0x1000>;
317                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
318                                 spi-max-frequency = <24000000>;
319                                 cs-gpios = <&msmgpio 8 0>;
320
321                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
322                                 clock-names = "core", "iface";
323                                 status = "disabled";
324                         };
325                 };
326         };
327 };