arch/arm/boot/dts/r8a7793.dtsi

   1 /*
   2  * Device Tree Source for the r8a7793 SoC
   3  *
   4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7793-clock.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14 #include <dt-bindings/power/r8a7793-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a7793";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 i2c6 = &i2c6;
  30                 i2c7 = &i2c7;
  31                 i2c8 = &i2c8;
  32                 spi0 = &qspi;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38                 enable-method = "renesas,apmu";
  39
  40                 cpu0: cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0>;
  44                         clock-frequency = <1500000000>;
  45                         voltage-tolerance = <1>; /* 1% */
  46                         clocks = <&cpg_clocks R8A7793_CLK_Z>;
  47                         clock-latency = <300000>; /* 300 us */
  48                         power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
  49
  50                         /* kHz - uV - OPPs unknown yet */
  51                         operating-points = <1500000 1000000>,
  52                                            <1312500 1000000>,
  53                                            <1125000 1000000>,
  54                                            < 937500 1000000>,
  55                                            < 750000 1000000>,
  56                                            < 375000 1000000>;
  57                         next-level-cache = <&L2_CA15>;
  58                 };
  59
  60                 cpu1: cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a15";
  63                         reg = <1>;
  64                         clock-frequency = <1500000000>;
  65                         power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
  66                 };
  67
  68                 L2_CA15: cache-controller-0 {
  69                         compatible = "cache";
  70                         power-domains = <&sysc R8A7793_PD_CA15_SCU>;
  71                         cache-unified;
  72                         cache-level = <2>;
  73                 };
  74         };
  75
  76         apmu@e6152000 {
  77                 compatible = "renesas,r8a7793-apmu", "renesas,apmu";
  78                 reg = <0 0xe6152000 0 0x188>;
  79                 cpus = <&cpu0 &cpu1>;
  80         };
  81
  82         thermal-zones {
  83                 cpu_thermal: cpu-thermal {
  84                         polling-delay-passive   = <0>;
  85                         polling-delay           = <0>;
  86
  87                         thermal-sensors = <&thermal>;
  88
  89                         trips {
  90                                 cpu-crit {
  91                                         temperature     = <115000>;
  92                                         hysteresis      = <0>;
  93                                         type            = "critical";
  94                                 };
  95                         };
  96                         cooling-maps {
  97                         };
  98                 };
  99         };
 100
 101         gic: interrupt-controller@f1001000 {
 102                 compatible = "arm,gic-400";
 103                 #interrupt-cells = <3>;
 104                 #address-cells = <0>;
 105                 interrupt-controller;
 106                 reg = <0 0xf1001000 0 0x1000>,
 107                         <0 0xf1002000 0 0x1000>,
 108                         <0 0xf1004000 0 0x2000>,
 109                         <0 0xf1006000 0 0x2000>;
 110                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 111         };
 112
 113         gpio0: gpio@e6050000 {
 114                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 115                 reg = <0 0xe6050000 0 0x50>;
 116                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 117                 #gpio-cells = <2>;
 118                 gpio-controller;
 119                 gpio-ranges = <&pfc 0 0 32>;
 120                 #interrupt-cells = <2>;
 121                 interrupt-controller;
 122                 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
 123                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 124         };
 125
 126         gpio1: gpio@e6051000 {
 127                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 128                 reg = <0 0xe6051000 0 0x50>;
 129                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 130                 #gpio-cells = <2>;
 131                 gpio-controller;
 132                 gpio-ranges = <&pfc 0 32 26>;
 133                 #interrupt-cells = <2>;
 134                 interrupt-controller;
 135                 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
 136                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 137         };
 138
 139         gpio2: gpio@e6052000 {
 140                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 141                 reg = <0 0xe6052000 0 0x50>;
 142                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 143                 #gpio-cells = <2>;
 144                 gpio-controller;
 145                 gpio-ranges = <&pfc 0 64 32>;
 146                 #interrupt-cells = <2>;
 147                 interrupt-controller;
 148                 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
 149                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 150         };
 151
 152         gpio3: gpio@e6053000 {
 153                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 154                 reg = <0 0xe6053000 0 0x50>;
 155                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 156                 #gpio-cells = <2>;
 157                 gpio-controller;
 158                 gpio-ranges = <&pfc 0 96 32>;
 159                 #interrupt-cells = <2>;
 160                 interrupt-controller;
 161                 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
 162                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 163         };
 164
 165         gpio4: gpio@e6054000 {
 166                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 167                 reg = <0 0xe6054000 0 0x50>;
 168                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 169                 #gpio-cells = <2>;
 170                 gpio-controller;
 171                 gpio-ranges = <&pfc 0 128 32>;
 172                 #interrupt-cells = <2>;
 173                 interrupt-controller;
 174                 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
 175                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 176         };
 177
 178         gpio5: gpio@e6055000 {
 179                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 180                 reg = <0 0xe6055000 0 0x50>;
 181                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 182                 #gpio-cells = <2>;
 183                 gpio-controller;
 184                 gpio-ranges = <&pfc 0 160 32>;
 185                 #interrupt-cells = <2>;
 186                 interrupt-controller;
 187                 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
 188                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 189         };
 190
 191         gpio6: gpio@e6055400 {
 192                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 193                 reg = <0 0xe6055400 0 0x50>;
 194                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 195                 #gpio-cells = <2>;
 196                 gpio-controller;
 197                 gpio-ranges = <&pfc 0 192 32>;
 198                 #interrupt-cells = <2>;
 199                 interrupt-controller;
 200                 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
 201                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 202         };
 203
 204         gpio7: gpio@e6055800 {
 205                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 206                 reg = <0 0xe6055800 0 0x50>;
 207                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 208                 #gpio-cells = <2>;
 209                 gpio-controller;
 210                 gpio-ranges = <&pfc 0 224 26>;
 211                 #interrupt-cells = <2>;
 212                 interrupt-controller;
 213                 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
 214                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 215         };
 216
 217         thermal: thermal@e61f0000 {
 218                 compatible =    "renesas,thermal-r8a7793",
 219                                 "renesas,rcar-gen2-thermal",
 220                                 "renesas,rcar-thermal";
 221                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 222                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 223                 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
 224                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 225                 #thermal-sensor-cells = <0>;
 226         };
 227
 228         timer {
 229                 compatible = "arm,armv7-timer";
 230                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 231                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 232                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 233                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 234         };
 235
 236         cmt0: timer@ffca0000 {
 237                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 238                 reg = <0 0xffca0000 0 0x1004>;
 239                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
 242                 clock-names = "fck";
 243                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 244
 245                 renesas,channels-mask = <0x60>;
 246
 247                 status = "disabled";
 248         };
 249
 250         cmt1: timer@e6130000 {
 251                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 252                 reg = <0 0xe6130000 0 0x1004>;
 253                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 261                 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
 262                 clock-names = "fck";
 263                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 264
 265                 renesas,channels-mask = <0xff>;
 266
 267                 status = "disabled";
 268         };
 269
 270         irqc0: interrupt-controller@e61c0000 {
 271                 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
 272                 #interrupt-cells = <2>;
 273                 interrupt-controller;
 274                 reg = <0 0xe61c0000 0 0x200>;
 275                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 285                 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
 286                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 287         };
 288
 289         dmac0: dma-controller@e6700000 {
 290                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 291                 reg = <0 0xe6700000 0 0x20000>;
 292                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 293                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 294                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 295                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 296                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 297                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 298                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 299                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 300                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 301                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 302                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 303                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 304                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 305                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 306                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 307                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 308                 interrupt-names = "error",
 309                                 "ch0", "ch1", "ch2", "ch3",
 310                                 "ch4", "ch5", "ch6", "ch7",
 311                                 "ch8", "ch9", "ch10", "ch11",
 312                                 "ch12", "ch13", "ch14";
 313                 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
 314                 clock-names = "fck";
 315                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 316                 #dma-cells = <1>;
 317                 dma-channels = <15>;
 318         };
 319
 320         dmac1: dma-controller@e6720000 {
 321                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 322                 reg = <0 0xe6720000 0 0x20000>;
 323                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 324                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 325                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 326                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 327                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 328                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 329                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 330                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 331                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 332                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 333                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 334                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 335                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 336                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 337                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 338                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 339                 interrupt-names = "error",
 340                                 "ch0", "ch1", "ch2", "ch3",
 341                                 "ch4", "ch5", "ch6", "ch7",
 342                                 "ch8", "ch9", "ch10", "ch11",
 343                                 "ch12", "ch13", "ch14";
 344                 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
 345                 clock-names = "fck";
 346                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 347                 #dma-cells = <1>;
 348                 dma-channels = <15>;
 349         };
 350
 351         audma0: dma-controller@ec700000 {
 352                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 353                 reg = <0 0xec700000 0 0x10000>;
 354                 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
 355                               GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
 356                               GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
 357                               GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
 358                               GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
 359                               GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
 360                               GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
 361                               GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
 362                               GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
 363                               GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
 364                               GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
 365                               GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
 366                               GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
 367                               GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 368                 interrupt-names = "error",
 369                                 "ch0", "ch1", "ch2", "ch3",
 370                                 "ch4", "ch5", "ch6", "ch7",
 371                                 "ch8", "ch9", "ch10", "ch11",
 372                                 "ch12";
 373                 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
 374                 clock-names = "fck";
 375                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 376                 #dma-cells = <1>;
 377                 dma-channels = <13>;
 378         };
 379
 380         audma1: dma-controller@ec720000 {
 381                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 382                 reg = <0 0xec720000 0 0x10000>;
 383                 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
 384                               GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
 385                               GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
 386                               GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
 387                               GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
 388                               GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
 389                               GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
 390                               GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
 391                               GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
 392                               GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
 393                               GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
 394                               GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
 395                               GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
 396                               GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 397                 interrupt-names = "error",
 398                                 "ch0", "ch1", "ch2", "ch3",
 399                                 "ch4", "ch5", "ch6", "ch7",
 400                                 "ch8", "ch9", "ch10", "ch11",
 401                                 "ch12";
 402                 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
 403                 clock-names = "fck";
 404                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 405                 #dma-cells = <1>;
 406                 dma-channels = <13>;
 407         };
 408
 409         /* The memory map in the User's Manual maps the cores to bus numbers */
 410         i2c0: i2c@e6508000 {
 411                 #address-cells = <1>;
 412                 #size-cells = <0>;
 413                 compatible = "renesas,i2c-r8a7793";
 414                 reg = <0 0xe6508000 0 0x40>;
 415                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 416                 clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
 417                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 418                 i2c-scl-internal-delay-ns = <6>;
 419                 status = "disabled";
 420         };
 421
 422         i2c1: i2c@e6518000 {
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 compatible = "renesas,i2c-r8a7793";
 426                 reg = <0 0xe6518000 0 0x40>;
 427                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 428                 clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
 429                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 430                 i2c-scl-internal-delay-ns = <6>;
 431                 status = "disabled";
 432         };
 433
 434         i2c2: i2c@e6530000 {
 435                 #address-cells = <1>;
 436                 #size-cells = <0>;
 437                 compatible = "renesas,i2c-r8a7793";
 438                 reg = <0 0xe6530000 0 0x40>;
 439                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 440                 clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
 441                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 442                 i2c-scl-internal-delay-ns = <6>;
 443                 status = "disabled";
 444         };
 445
 446         i2c3: i2c@e6540000 {
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 compatible = "renesas,i2c-r8a7793";
 450                 reg = <0 0xe6540000 0 0x40>;
 451                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 452                 clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
 453                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 454                 i2c-scl-internal-delay-ns = <6>;
 455                 status = "disabled";
 456         };
 457
 458         i2c4: i2c@e6520000 {
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 compatible = "renesas,i2c-r8a7793";
 462                 reg = <0 0xe6520000 0 0x40>;
 463                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 464                 clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
 465                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 466                 i2c-scl-internal-delay-ns = <6>;
 467                 status = "disabled";
 468         };
 469
 470         i2c5: i2c@e6528000 {
 471                 /* doesn't need pinmux */
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474                 compatible = "renesas,i2c-r8a7793";
 475                 reg = <0 0xe6528000 0 0x40>;
 476                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 477                 clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
 478                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 479                 i2c-scl-internal-delay-ns = <110>;
 480                 status = "disabled";
 481         };
 482
 483         i2c6: i2c@e60b0000 {
 484                 /* doesn't need pinmux */
 485                 #address-cells = <1>;
 486                 #size-cells = <0>;
 487                 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
 488                 reg = <0 0xe60b0000 0 0x425>;
 489                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 490                 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
 491                 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
 492                        <&dmac1 0x77>, <&dmac1 0x78>;
 493                 dma-names = "tx", "rx", "tx", "rx";
 494                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 495                 status = "disabled";
 496         };
 497
 498         i2c7: i2c@e6500000 {
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
 502                 reg = <0 0xe6500000 0 0x425>;
 503                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 504                 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
 505                 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
 506                        <&dmac1 0x61>, <&dmac1 0x62>;
 507                 dma-names = "tx", "rx", "tx", "rx";
 508                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 509                 status = "disabled";
 510         };
 511
 512         i2c8: i2c@e6510000 {
 513                 #address-cells = <1>;
 514                 #size-cells = <0>;
 515                 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
 516                 reg = <0 0xe6510000 0 0x425>;
 517                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 518                 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
 519                 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
 520                        <&dmac1 0x65>, <&dmac1 0x66>;
 521                 dma-names = "tx", "rx", "tx", "rx";
 522                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 523                 status = "disabled";
 524         };
 525
 526         pfc: pfc@e6060000 {
 527                 compatible = "renesas,pfc-r8a7793";
 528                 reg = <0 0xe6060000 0 0x250>;
 529         };
 530
 531         sdhi0: sd@ee100000 {
 532                 compatible = "renesas,sdhi-r8a7793";
 533                 reg = <0 0xee100000 0 0x328>;
 534                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 535                 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
 536                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 537                        <&dmac1 0xcd>, <&dmac1 0xce>;
 538                 dma-names = "tx", "rx", "tx", "rx";
 539                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 540                 status = "disabled";
 541         };
 542
 543         sdhi1: sd@ee140000 {
 544                 compatible = "renesas,sdhi-r8a7793";
 545                 reg = <0 0xee140000 0 0x100>;
 546                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 547                 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
 548                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
 549                        <&dmac1 0xc1>, <&dmac1 0xc2>;
 550                 dma-names = "tx", "rx", "tx", "rx";
 551                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 552                 status = "disabled";
 553         };
 554
 555         sdhi2: sd@ee160000 {
 556                 compatible = "renesas,sdhi-r8a7793";
 557                 reg = <0 0xee160000 0 0x100>;
 558                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 559                 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
 560                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
 561                        <&dmac1 0xd3>, <&dmac1 0xd4>;
 562                 dma-names = "tx", "rx", "tx", "rx";
 563                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 564                 status = "disabled";
 565         };
 566
 567         mmcif0: mmc@ee200000 {
 568                 compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
 569                 reg = <0 0xee200000 0 0x80>;
 570                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 571                 clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>;
 572                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
 573                        <&dmac1 0xd1>, <&dmac1 0xd2>;
 574                 dma-names = "tx", "rx", "tx", "rx";
 575                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 576                 reg-io-width = <4>;
 577                 status = "disabled";
 578                 max-frequency = <97500000>;
 579         };
 580
 581         scifa0: serial@e6c40000 {
 582                 compatible = "renesas,scifa-r8a7793",
 583                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 584                 reg = <0 0xe6c40000 0 64>;
 585                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 586                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
 587                 clock-names = "fck";
 588                 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 589                        <&dmac1 0x21>, <&dmac1 0x22>;
 590                 dma-names = "tx", "rx", "tx", "rx";
 591                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 592                 status = "disabled";
 593         };
 594
 595         scifa1: serial@e6c50000 {
 596                 compatible = "renesas,scifa-r8a7793",
 597                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 598                 reg = <0 0xe6c50000 0 64>;
 599                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 600                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
 601                 clock-names = "fck";
 602                 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 603                        <&dmac1 0x25>, <&dmac1 0x26>;
 604                 dma-names = "tx", "rx", "tx", "rx";
 605                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 606                 status = "disabled";
 607         };
 608
 609         scifa2: serial@e6c60000 {
 610                 compatible = "renesas,scifa-r8a7793",
 611                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 612                 reg = <0 0xe6c60000 0 64>;
 613                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 614                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
 615                 clock-names = "fck";
 616                 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 617                        <&dmac1 0x27>, <&dmac1 0x28>;
 618                 dma-names = "tx", "rx", "tx", "rx";
 619                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 620                 status = "disabled";
 621         };
 622
 623         scifa3: serial@e6c70000 {
 624                 compatible = "renesas,scifa-r8a7793",
 625                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 626                 reg = <0 0xe6c70000 0 64>;
 627                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 628                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
 629                 clock-names = "fck";
 630                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 631                        <&dmac1 0x1b>, <&dmac1 0x1c>;
 632                 dma-names = "tx", "rx", "tx", "rx";
 633                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 634                 status = "disabled";
 635         };
 636
 637         scifa4: serial@e6c78000 {
 638                 compatible = "renesas,scifa-r8a7793",
 639                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 640                 reg = <0 0xe6c78000 0 64>;
 641                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 642                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
 643                 clock-names = "fck";
 644                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 645                        <&dmac1 0x1f>, <&dmac1 0x20>;
 646                 dma-names = "tx", "rx", "tx", "rx";
 647                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 648                 status = "disabled";
 649         };
 650
 651         scifa5: serial@e6c80000 {
 652                 compatible = "renesas,scifa-r8a7793",
 653                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 654                 reg = <0 0xe6c80000 0 64>;
 655                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 656                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
 657                 clock-names = "fck";
 658                 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 659                        <&dmac1 0x23>, <&dmac1 0x24>;
 660                 dma-names = "tx", "rx", "tx", "rx";
 661                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 662                 status = "disabled";
 663         };
 664
 665         scifb0: serial@e6c20000 {
 666                 compatible = "renesas,scifb-r8a7793",
 667                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 668                 reg = <0 0xe6c20000 0 64>;
 669                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 670                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
 671                 clock-names = "fck";
 672                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 673                        <&dmac1 0x3d>, <&dmac1 0x3e>;
 674                 dma-names = "tx", "rx", "tx", "rx";
 675                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 676                 status = "disabled";
 677         };
 678
 679         scifb1: serial@e6c30000 {
 680                 compatible = "renesas,scifb-r8a7793",
 681                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 682                 reg = <0 0xe6c30000 0 64>;
 683                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 684                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
 685                 clock-names = "fck";
 686                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 687                        <&dmac1 0x19>, <&dmac1 0x1a>;
 688                 dma-names = "tx", "rx", "tx", "rx";
 689                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 690                 status = "disabled";
 691         };
 692
 693         scifb2: serial@e6ce0000 {
 694                 compatible = "renesas,scifb-r8a7793",
 695                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 696                 reg = <0 0xe6ce0000 0 64>;
 697                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 698                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
 699                 clock-names = "fck";
 700                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 701                        <&dmac1 0x1d>, <&dmac1 0x1e>;
 702                 dma-names = "tx", "rx", "tx", "rx";
 703                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 704                 status = "disabled";
 705         };
 706
 707         scif0: serial@e6e60000 {
 708                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 709                              "renesas,scif";
 710                 reg = <0 0xe6e60000 0 64>;
 711                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 712                 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
 713                          <&scif_clk>;
 714                 clock-names = "fck", "brg_int", "scif_clk";
 715                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 716                        <&dmac1 0x29>, <&dmac1 0x2a>;
 717                 dma-names = "tx", "rx", "tx", "rx";
 718                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 719                 status = "disabled";
 720         };
 721
 722         scif1: serial@e6e68000 {
 723                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 724                              "renesas,scif";
 725                 reg = <0 0xe6e68000 0 64>;
 726                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 727                 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
 728                          <&scif_clk>;
 729                 clock-names = "fck", "brg_int", "scif_clk";
 730                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 731                        <&dmac1 0x2d>, <&dmac1 0x2e>;
 732                 dma-names = "tx", "rx", "tx", "rx";
 733                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 734                 status = "disabled";
 735         };
 736
 737         scif2: serial@e6e58000 {
 738                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 739                              "renesas,scif";
 740                 reg = <0 0xe6e58000 0 64>;
 741                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 742                 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
 743                          <&scif_clk>;
 744                 clock-names = "fck", "brg_int", "scif_clk";
 745                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 746                        <&dmac1 0x2b>, <&dmac1 0x2c>;
 747                 dma-names = "tx", "rx", "tx", "rx";
 748                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 749                 status = "disabled";
 750         };
 751
 752         scif3: serial@e6ea8000 {
 753                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 754                              "renesas,scif";
 755                 reg = <0 0xe6ea8000 0 64>;
 756                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 757                 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
 758                          <&scif_clk>;
 759                 clock-names = "fck", "brg_int", "scif_clk";
 760                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 761                        <&dmac1 0x2f>, <&dmac1 0x30>;
 762                 dma-names = "tx", "rx", "tx", "rx";
 763                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 764                 status = "disabled";
 765         };
 766
 767         scif4: serial@e6ee0000 {
 768                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 769                              "renesas,scif";
 770                 reg = <0 0xe6ee0000 0 64>;
 771                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 772                 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
 773                          <&scif_clk>;
 774                 clock-names = "fck", "brg_int", "scif_clk";
 775                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 776                        <&dmac1 0xfb>, <&dmac1 0xfc>;
 777                 dma-names = "tx", "rx", "tx", "rx";
 778                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 779                 status = "disabled";
 780         };
 781
 782         scif5: serial@e6ee8000 {
 783                 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
 784                              "renesas,scif";
 785                 reg = <0 0xe6ee8000 0 64>;
 786                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 787                 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
 788                          <&scif_clk>;
 789                 clock-names = "fck", "brg_int", "scif_clk";
 790                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 791                        <&dmac1 0xfd>, <&dmac1 0xfe>;
 792                 dma-names = "tx", "rx", "tx", "rx";
 793                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 794                 status = "disabled";
 795         };
 796
 797         hscif0: serial@e62c0000 {
 798                 compatible = "renesas,hscif-r8a7793",
 799                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 800                 reg = <0 0xe62c0000 0 96>;
 801                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 802                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
 803                          <&scif_clk>;
 804                 clock-names = "fck", "brg_int", "scif_clk";
 805                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 806                        <&dmac1 0x39>, <&dmac1 0x3a>;
 807                 dma-names = "tx", "rx", "tx", "rx";
 808                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 809                 status = "disabled";
 810         };
 811
 812         hscif1: serial@e62c8000 {
 813                 compatible = "renesas,hscif-r8a7793",
 814                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 815                 reg = <0 0xe62c8000 0 96>;
 816                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 817                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
 818                          <&scif_clk>;
 819                 clock-names = "fck", "brg_int", "scif_clk";
 820                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 821                        <&dmac1 0x4d>, <&dmac1 0x4e>;
 822                 dma-names = "tx", "rx", "tx", "rx";
 823                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 824                 status = "disabled";
 825         };
 826
 827         hscif2: serial@e62d0000 {
 828                 compatible = "renesas,hscif-r8a7793",
 829                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 830                 reg = <0 0xe62d0000 0 96>;
 831                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 832                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
 833                          <&scif_clk>;
 834                 clock-names = "fck", "brg_int", "scif_clk";
 835                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 836                        <&dmac1 0x3b>, <&dmac1 0x3c>;
 837                 dma-names = "tx", "rx", "tx", "rx";
 838                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 839                 status = "disabled";
 840         };
 841
 842         ether: ethernet@ee700000 {
 843                 compatible = "renesas,ether-r8a7793";
 844                 reg = <0 0xee700000 0 0x400>;
 845                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 846                 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
 847                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 848                 phy-mode = "rmii";
 849                 #address-cells = <1>;
 850                 #size-cells = <0>;
 851                 status = "disabled";
 852         };
 853
 854         qspi: spi@e6b10000 {
 855                 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
 856                 reg = <0 0xe6b10000 0 0x2c>;
 857                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 858                 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
 859                 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 860                        <&dmac1 0x17>, <&dmac1 0x18>;
 861                 dma-names = "tx", "rx", "tx", "rx";
 862                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 863                 num-cs = <1>;
 864                 #address-cells = <1>;
 865                 #size-cells = <0>;
 866                 status = "disabled";
 867         };
 868
 869         du: display@feb00000 {
 870                 compatible = "renesas,du-r8a7793";
 871                 reg = <0 0xfeb00000 0 0x40000>,
 872                       <0 0xfeb90000 0 0x1c>;
 873                 reg-names = "du", "lvds.0";
 874                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 875                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 876                 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
 877                          <&mstp7_clks R8A7793_CLK_DU1>,
 878                          <&mstp7_clks R8A7793_CLK_LVDS0>;
 879                 clock-names = "du.0", "du.1", "lvds.0";
 880                 status = "disabled";
 881
 882                 ports {
 883                         #address-cells = <1>;
 884                         #size-cells = <0>;
 885
 886                         port@0 {
 887                                 reg = <0>;
 888                                 du_out_rgb: endpoint {
 889                                 };
 890                         };
 891                         port@1 {
 892                                 reg = <1>;
 893                                 du_out_lvds0: endpoint {
 894                                 };
 895                         };
 896                 };
 897         };
 898
 899         can0: can@e6e80000 {
 900                 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
 901                 reg = <0 0xe6e80000 0 0x1000>;
 902                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 903                 clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
 904                          <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
 905                 clock-names = "clkp1", "clkp2", "can_clk";
 906                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 907                 status = "disabled";
 908         };
 909
 910         can1: can@e6e88000 {
 911                 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
 912                 reg = <0 0xe6e88000 0 0x1000>;
 913                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 914                 clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
 915                          <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
 916                 clock-names = "clkp1", "clkp2", "can_clk";
 917                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 918                 status = "disabled";
 919         };
 920
 921         clocks {
 922                 #address-cells = <2>;
 923                 #size-cells = <2>;
 924                 ranges;
 925
 926                 /* External root clock */
 927                 extal_clk: extal {
 928                         compatible = "fixed-clock";
 929                         #clock-cells = <0>;
 930                         /* This value must be overridden by the board. */
 931                         clock-frequency = <0>;
 932                 };
 933
 934                 /*
 935                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 936                  * default. Boards that provide audio clocks should override them.
 937                  */
 938                 audio_clk_a: audio_clk_a {
 939                         compatible = "fixed-clock";
 940                         #clock-cells = <0>;
 941                         clock-frequency = <0>;
 942                 };
 943                 audio_clk_b: audio_clk_b {
 944                         compatible = "fixed-clock";
 945                         #clock-cells = <0>;
 946                         clock-frequency = <0>;
 947                 };
 948                 audio_clk_c: audio_clk_c {
 949                         compatible = "fixed-clock";
 950                         #clock-cells = <0>;
 951                         clock-frequency = <0>;
 952                 };
 953
 954                 /* External USB clock - can be overridden by the board */
 955                 usb_extal_clk: usb_extal {
 956                         compatible = "fixed-clock";
 957                         #clock-cells = <0>;
 958                         clock-frequency = <48000000>;
 959                 };
 960
 961                 /* External CAN clock */
 962                 can_clk: can {
 963                         compatible = "fixed-clock";
 964                         #clock-cells = <0>;
 965                         /* This value must be overridden by the board. */
 966                         clock-frequency = <0>;
 967                 };
 968
 969                 /* External SCIF clock */
 970                 scif_clk: scif {
 971                         compatible = "fixed-clock";
 972                         #clock-cells = <0>;
 973                         /* This value must be overridden by the board. */
 974                         clock-frequency = <0>;
 975                 };
 976
 977                 /* Special CPG clocks */
 978                 cpg_clocks: cpg_clocks@e6150000 {
 979                         compatible = "renesas,r8a7793-cpg-clocks",
 980                                      "renesas,rcar-gen2-cpg-clocks";
 981                         reg = <0 0xe6150000 0 0x1000>;
 982                         clocks = <&extal_clk &usb_extal_clk>;
 983                         #clock-cells = <1>;
 984                         clock-output-names = "main", "pll0", "pll1", "pll3",
 985                                              "lb", "qspi", "sdh", "sd0", "z",
 986                                              "rcan", "adsp";
 987                         #power-domain-cells = <0>;
 988                 };
 989
 990                 /* Variable factor clocks */
 991                 sd2_clk: sd2@e6150078 {
 992                         compatible = "renesas,r8a7793-div6-clock",
 993                                      "renesas,cpg-div6-clock";
 994                         reg = <0 0xe6150078 0 4>;
 995                         clocks = <&pll1_div2_clk>;
 996                         #clock-cells = <0>;
 997                 };
 998                 sd3_clk: sd3@e615026c {
 999                         compatible = "renesas,r8a7793-div6-clock",
1000                                      "renesas,cpg-div6-clock";
1001                         reg = <0 0xe615026c 0 4>;
1002                         clocks = <&pll1_div2_clk>;
1003                         #clock-cells = <0>;
1004                 };
1005                 mmc0_clk: mmc0@e6150240 {
1006                         compatible = "renesas,r8a7793-div6-clock",
1007                                      "renesas,cpg-div6-clock";
1008                         reg = <0 0xe6150240 0 4>;
1009                         clocks = <&pll1_div2_clk>;
1010                         #clock-cells = <0>;
1011                 };
1012
1013                 /* Fixed factor clocks */
1014                 pll1_div2_clk: pll1_div2 {
1015                         compatible = "fixed-factor-clock";
1016                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1017                         #clock-cells = <0>;
1018                         clock-div = <2>;
1019                         clock-mult = <1>;
1020                 };
1021                 zg_clk: zg {
1022                         compatible = "fixed-factor-clock";
1023                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1024                         #clock-cells = <0>;
1025                         clock-div = <5>;
1026                         clock-mult = <1>;
1027                 };
1028                 zx_clk: zx {
1029                         compatible = "fixed-factor-clock";
1030                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1031                         #clock-cells = <0>;
1032                         clock-div = <3>;
1033                         clock-mult = <1>;
1034                 };
1035                 zs_clk: zs {
1036                         compatible = "fixed-factor-clock";
1037                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1038                         #clock-cells = <0>;
1039                         clock-div = <6>;
1040                         clock-mult = <1>;
1041                 };
1042                 hp_clk: hp {
1043                         compatible = "fixed-factor-clock";
1044                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1045                         #clock-cells = <0>;
1046                         clock-div = <12>;
1047                         clock-mult = <1>;
1048                 };
1049                 p_clk: p {
1050                         compatible = "fixed-factor-clock";
1051                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1052                         #clock-cells = <0>;
1053                         clock-div = <24>;
1054                         clock-mult = <1>;
1055                 };
1056                 m2_clk: m2 {
1057                         compatible = "fixed-factor-clock";
1058                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1059                         #clock-cells = <0>;
1060                         clock-div = <8>;
1061                         clock-mult = <1>;
1062                 };
1063                 rclk_clk: rclk {
1064                         compatible = "fixed-factor-clock";
1065                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1066                         #clock-cells = <0>;
1067                         clock-div = <(48 * 1024)>;
1068                         clock-mult = <1>;
1069                 };
1070                 mp_clk: mp {
1071                         compatible = "fixed-factor-clock";
1072                         clocks = <&pll1_div2_clk>;
1073                         #clock-cells = <0>;
1074                         clock-div = <15>;
1075                         clock-mult = <1>;
1076                 };
1077                 cp_clk: cp {
1078                         compatible = "fixed-factor-clock";
1079                         clocks = <&extal_clk>;
1080                         #clock-cells = <0>;
1081                         clock-div = <2>;
1082                         clock-mult = <1>;
1083                 };
1084
1085                 /* Gate clocks */
1086                 mstp1_clks: mstp1_clks@e6150134 {
1087                         compatible = "renesas,r8a7793-mstp-clocks",
1088                                      "renesas,cpg-mstp-clocks";
1089                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1090                         clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1091                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
1092                                  <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1093                                  <&zs_clk>, <&zs_clk>, <&zs_clk>;
1094                         #clock-cells = <1>;
1095                         clock-indices = <
1096                                 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
1097                                 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
1098                                 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
1099                                 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
1100                                 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
1101                                 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
1102                                 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
1103                                 R8A7793_CLK_VSP1_S
1104                         >;
1105                         clock-output-names =
1106                                 "vcp0", "vpc0", "ssp_dev", "tmu1",
1107                                 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
1108                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
1109                                 "vsp1-du0", "vsps";
1110                 };
1111                 mstp2_clks: mstp2_clks@e6150138 {
1112                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1113                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1114                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1115                                  <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
1116                         #clock-cells = <1>;
1117                         clock-indices = <
1118                                 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
1119                                 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
1120                                 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
1121                         >;
1122                         clock-output-names =
1123                                 "scifa2", "scifa1", "scifa0", "scifb0",
1124                                 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
1125                 };
1126                 mstp3_clks: mstp3_clks@e615013c {
1127                         compatible = "renesas,r8a7793-mstp-clocks",
1128                                      "renesas,cpg-mstp-clocks";
1129                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1130                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
1131                                  <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
1132                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
1133                                  <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1134                         #clock-cells = <1>;
1135                         clock-indices = <
1136                                 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
1137                                 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
1138                                 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
1139                                 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
1140                                 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
1141                                 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
1142                         >;
1143                         clock-output-names =
1144                                 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1145                                 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1146                                 "usbdmac0", "usbdmac1";
1147                 };
1148                 mstp4_clks: mstp4_clks@e6150140 {
1149                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1150                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1151                         clocks = <&cp_clk>;
1152                         #clock-cells = <1>;
1153                         clock-indices = <R8A7793_CLK_IRQC>;
1154                         clock-output-names = "irqc";
1155                 };
1156                 mstp5_clks: mstp5_clks@e6150144 {
1157                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1158                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1159                         clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
1160                         #clock-cells = <1>;
1161                         clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
1162                                          R8A7793_CLK_THERMAL>;
1163                         clock-output-names = "audmac0", "audmac1", "thermal";
1164                 };
1165                 mstp7_clks: mstp7_clks@e615014c {
1166                         compatible = "renesas,r8a7793-mstp-clocks",
1167                                      "renesas,cpg-mstp-clocks";
1168                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1169                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>,
1170                                  <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1171                                  <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
1172                                  <&zx_clk>, <&zx_clk>;
1173                         #clock-cells = <1>;
1174                         clock-indices = <
1175                                 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
1176                                 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
1177                                 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
1178                                 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
1179                                 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
1180                                 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
1181                                 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
1182                         >;
1183                         clock-output-names =
1184                                 "ehci", "hsusb", "hscif2", "scif5", "scif4",
1185                                 "hscif1", "hscif0", "scif3", "scif2",
1186                                 "scif1", "scif0", "du1", "du0", "lvds0";
1187                 };
1188                 mstp8_clks: mstp8_clks@e6150990 {
1189                         compatible = "renesas,r8a7793-mstp-clocks",
1190                                      "renesas,cpg-mstp-clocks";
1191                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1192                         clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1193                                  <&p_clk>, <&zs_clk>, <&zs_clk>;
1194                         #clock-cells = <1>;
1195                         clock-indices = <
1196                                 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
1197                                 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
1198                                 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
1199                                 R8A7793_CLK_SATA0
1200                         >;
1201                         clock-output-names =
1202                                 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
1203                                 "sata1", "sata0";
1204                 };
1205                 mstp9_clks: mstp9_clks@e6150994 {
1206                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1207                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1208                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1209                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1210                                  <&p_clk>, <&p_clk>,
1211                                  <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
1212                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1213                                  <&hp_clk>, <&hp_clk>;
1214                         #clock-cells = <1>;
1215                         clock-indices = <
1216                                 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
1217                                 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
1218                                 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
1219                                 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
1220                                 R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
1221                                 R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
1222                                 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
1223                                 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
1224                                 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
1225                         >;
1226                         clock-output-names =
1227                                 "gpio7", "gpio6", "gpio5", "gpio4",
1228                                 "gpio3", "gpio2", "gpio1", "gpio0",
1229                                 "rcan1", "rcan0", "qspi_mod", "i2c5",
1230                                 "i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
1231                                 "i2c0";
1232                 };
1233                 mstp10_clks: mstp10_clks@e6150998 {
1234                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1235                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1236                         clocks = <&p_clk>,
1237                                 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1238                                 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1239                                 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1240                                 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1241                                 <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1242                                 <&p_clk>,
1243                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1244                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1245                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1246                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1247                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1248                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1249                                 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
1250
1251                         #clock-cells = <1>;
1252                         clock-indices = <
1253                                 R8A7793_CLK_SSI_ALL
1254                                 R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
1255                                 R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
1256                                 R8A7793_CLK_SCU_ALL
1257                                 R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
1258                                 R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
1259                                 R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
1260                                 R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
1261                         >;
1262                         clock-output-names =
1263                                 "ssi-all",
1264                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1265                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1266                                 "scu-all",
1267                                 "scu-dvc1", "scu-dvc0",
1268                                 "scu-ctu1-mix1", "scu-ctu0-mix0",
1269                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1270                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1271                 };
1272                 mstp11_clks: mstp11_clks@e615099c {
1273                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1274                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1275                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1276                         #clock-cells = <1>;
1277                         clock-indices = <
1278                                 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
1279                         >;
1280                         clock-output-names = "scifa3", "scifa4", "scifa5";
1281                 };
1282         };
1283
1284         sysc: system-controller@e6180000 {
1285                 compatible = "renesas,r8a7793-sysc";
1286                 reg = <0 0xe6180000 0 0x0200>;
1287                 #power-domain-cells = <1>;
1288         };
1289
1290         ipmmu_sy0: mmu@e6280000 {
1291                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1292                 reg = <0 0xe6280000 0 0x1000>;
1293                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1294                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1295                 #iommu-cells = <1>;
1296                 status = "disabled";
1297         };
1298
1299         ipmmu_sy1: mmu@e6290000 {
1300                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1301                 reg = <0 0xe6290000 0 0x1000>;
1302                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1303                 #iommu-cells = <1>;
1304                 status = "disabled";
1305         };
1306
1307         ipmmu_ds: mmu@e6740000 {
1308                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1309                 reg = <0 0xe6740000 0 0x1000>;
1310                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1311                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1312                 #iommu-cells = <1>;
1313                 status = "disabled";
1314         };
1315
1316         ipmmu_mp: mmu@ec680000 {
1317                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1318                 reg = <0 0xec680000 0 0x1000>;
1319                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1320                 #iommu-cells = <1>;
1321                 status = "disabled";
1322         };
1323
1324         ipmmu_mx: mmu@fe951000 {
1325                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1326                 reg = <0 0xfe951000 0 0x1000>;
1327                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1328                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1329                 #iommu-cells = <1>;
1330                 status = "disabled";
1331         };
1332
1333         ipmmu_rt: mmu@ffc80000 {
1334                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1335                 reg = <0 0xffc80000 0 0x1000>;
1336                 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1337                 #iommu-cells = <1>;
1338                 status = "disabled";
1339         };
1340
1341         ipmmu_gp: mmu@e62a0000 {
1342                 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1343                 reg = <0 0xe62a0000 0 0x1000>;
1344                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1345                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1346                 #iommu-cells = <1>;
1347                 status = "disabled";
1348         };
1349
1350         rcar_sound: sound@ec500000 {
1351                 /*
1352                  * #sound-dai-cells is required
1353                  *
1354                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1355                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1356                  */
1357                 compatible =  "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
1358                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1359                         <0 0xec5a0000 0 0x100>,  /* ADG */
1360                         <0 0xec540000 0 0x1000>, /* SSIU */
1361                         <0 0xec541000 0 0x280>,  /* SSI */
1362                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1363                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1364
1365                 clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1366                         <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
1367                         <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
1368                         <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
1369                         <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
1370                         <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
1371                         <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
1372                         <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
1373                         <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
1374                         <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
1375                         <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
1376                         <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
1377                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1378                 clock-names = "ssi-all",
1379                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1380                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1381                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1382                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1383                                 "dvc.0", "dvc.1",
1384                                 "clk_a", "clk_b", "clk_c", "clk_i";
1385                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1386
1387                 status = "disabled";
1388
1389                 rcar_sound,dvc {
1390                         dvc0: dvc-0 {
1391                                 dmas = <&audma0 0xbc>;
1392                                 dma-names = "tx";
1393                         };
1394                         dvc1: dvc-1 {
1395                                 dmas = <&audma0 0xbe>;
1396                                 dma-names = "tx";
1397                         };
1398                 };
1399
1400                 rcar_sound,src {
1401                         src0: src-0 {
1402                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1403                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1404                                 dma-names = "rx", "tx";
1405                         };
1406                         src1: src-1 {
1407                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1408                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1409                                 dma-names = "rx", "tx";
1410                         };
1411                         src2: src-2 {
1412                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1413                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1414                                 dma-names = "rx", "tx";
1415                         };
1416                         src3: src-3 {
1417                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1418                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1419                                 dma-names = "rx", "tx";
1420                         };
1421                         src4: src-4 {
1422                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1423                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1424                                 dma-names = "rx", "tx";
1425                         };
1426                         src5: src-5 {
1427                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1428                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1429                                 dma-names = "rx", "tx";
1430                         };
1431                         src6: src-6 {
1432                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1433                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1434                                 dma-names = "rx", "tx";
1435                         };
1436                         src7: src-7 {
1437                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1438                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1439                                 dma-names = "rx", "tx";
1440                         };
1441                         src8: src-8 {
1442                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1443                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1444                                 dma-names = "rx", "tx";
1445                         };
1446                         src9: src-9 {
1447                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1448                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1449                                 dma-names = "rx", "tx";
1450                         };
1451                 };
1452
1453                 rcar_sound,ssi {
1454                         ssi0: ssi-0 {
1455                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1456                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1457                                 dma-names = "rx", "tx", "rxu", "txu";
1458                         };
1459                         ssi1: ssi-1 {
1460                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1461                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1462                                 dma-names = "rx", "tx", "rxu", "txu";
1463                         };
1464                         ssi2: ssi-2 {
1465                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1466                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1467                                 dma-names = "rx", "tx", "rxu", "txu";
1468                         };
1469                         ssi3: ssi-3 {
1470                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1471                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1472                                 dma-names = "rx", "tx", "rxu", "txu";
1473                         };
1474                         ssi4: ssi-4 {
1475                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1476                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1477                                 dma-names = "rx", "tx", "rxu", "txu";
1478                         };
1479                         ssi5: ssi-5 {
1480                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1481                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1482                                 dma-names = "rx", "tx", "rxu", "txu";
1483                         };
1484                         ssi6: ssi-6 {
1485                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1486                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1487                                 dma-names = "rx", "tx", "rxu", "txu";
1488                         };
1489                         ssi7: ssi-7 {
1490                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1491                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1492                                 dma-names = "rx", "tx", "rxu", "txu";
1493                         };
1494                         ssi8: ssi-8 {
1495                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1496                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1497                                 dma-names = "rx", "tx", "rxu", "txu";
1498                         };
1499                         ssi9: ssi-9 {
1500                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1501                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1502                                 dma-names = "rx", "tx", "rxu", "txu";
1503                         };
1504                 };
1505         };
1506 };