arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include "skeleton.dtsi"
  49
  50 / {
  51         compatible = "rockchip,rk3288";
  52
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 mshc0 = &emmc;
  63                 mshc1 = &sdmmc;
  64                 mshc2 = &sdio0;
  65                 mshc3 = &sdio1;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74         };
  75
  76         arm-pmu {
  77                 compatible = "arm,cortex-a12-pmu";
  78                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  79                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  82                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  83         };
  84
  85         cpus {
  86                 #address-cells = <1>;
  87                 #size-cells = <0>;
  88                 enable-method = "rockchip,rk3066-smp";
  89                 rockchip,pmu = <&pmu>;
  90
  91                 cpu0: cpu@500 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a12";
  94                         reg = <0x500>;
  95                         resets = <&cru SRST_CORE0>;
  96                         operating-points = <
  97                                 /* KHz    uV */
  98                                 1608000 1350000
  99                                 1512000 1300000
 100                                 1416000 1200000
 101                                 1200000 1100000
 102                                 1008000 1050000
 103                                  816000 1000000
 104                                  696000  950000
 105                                  600000  900000
 106                                  408000  900000
 107                                  312000  900000
 108                                  216000  900000
 109                                  126000  900000
 110                         >;
 111                         #cooling-cells = <2>; /* min followed by max */
 112                         clock-latency = <40000>;
 113                         clocks = <&cru ARMCLK>;
 114                 };
 115                 cpu1: cpu@501 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a12";
 118                         reg = <0x501>;
 119                         resets = <&cru SRST_CORE1>;
 120                 };
 121                 cpu2: cpu@502 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a12";
 124                         reg = <0x502>;
 125                         resets = <&cru SRST_CORE2>;
 126                 };
 127                 cpu3: cpu@503 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a12";
 130                         reg = <0x503>;
 131                         resets = <&cru SRST_CORE3>;
 132                 };
 133         };
 134
 135         amba {
 136                 compatible = "arm,amba-bus";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 ranges;
 140
 141                 dmac_peri: dma-controller@ff250000 {
 142                         compatible = "arm,pl330", "arm,primecell";
 143                         reg = <0xff250000 0x4000>;
 144                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 145                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 146                         #dma-cells = <1>;
 147                         clocks = <&cru ACLK_DMAC2>;
 148                         clock-names = "apb_pclk";
 149                 };
 150
 151                 dmac_bus_ns: dma-controller@ff600000 {
 152                         compatible = "arm,pl330", "arm,primecell";
 153                         reg = <0xff600000 0x4000>;
 154                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 155                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 156                         #dma-cells = <1>;
 157                         clocks = <&cru ACLK_DMAC1>;
 158                         clock-names = "apb_pclk";
 159                         status = "disabled";
 160                 };
 161
 162                 dmac_bus_s: dma-controller@ffb20000 {
 163                         compatible = "arm,pl330", "arm,primecell";
 164                         reg = <0xffb20000 0x4000>;
 165                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 166                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 167                         #dma-cells = <1>;
 168                         clocks = <&cru ACLK_DMAC1>;
 169                         clock-names = "apb_pclk";
 170                 };
 171         };
 172
 173         reserved-memory {
 174                 #address-cells = <1>;
 175                 #size-cells = <1>;
 176                 ranges;
 177
 178                 /*
 179                  * The rk3288 cannot use the memory area above 0xfe000000
 180                  * for dma operations for some reason. While there is
 181                  * probably a better solution available somewhere, we
 182                  * haven't found it yet and while devices with 2GB of ram
 183                  * are not affected, this issue prevents 4GB from booting.
 184                  * So to make these devices at least bootable, block
 185                  * this area for the time being until the real solution
 186                  * is found.
 187                  */
 188                 dma-unusable@fe000000 {
 189                         reg = <0xfe000000 0x1000000>;
 190                 };
 191         };
 192
 193         xin24m: oscillator {
 194                 compatible = "fixed-clock";
 195                 clock-frequency = <24000000>;
 196                 clock-output-names = "xin24m";
 197                 #clock-cells = <0>;
 198         };
 199
 200         timer {
 201                 compatible = "arm,armv7-timer";
 202                 arm,cpu-registers-not-fw-configured;
 203                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 204                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 205                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 206                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 207                 clock-frequency = <24000000>;
 208                 arm,no-tick-in-suspend;
 209         };
 210
 211         timer: timer@ff810000 {
 212                 compatible = "rockchip,rk3288-timer";
 213                 reg = <0xff810000 0x20>;
 214                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 216                 clock-names = "timer", "pclk";
 217         };
 218
 219         display-subsystem {
 220                 compatible = "rockchip,display-subsystem";
 221                 ports = <&vopl_out>, <&vopb_out>;
 222         };
 223
 224         sdmmc: dwmmc@ff0c0000 {
 225                 compatible = "rockchip,rk3288-dw-mshc";
 226                 clock-freq-min-max = <400000 150000000>;
 227                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 228                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 229                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 230                 fifo-depth = <0x100>;
 231                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 232                 reg = <0xff0c0000 0x4000>;
 233                 status = "disabled";
 234         };
 235
 236         sdio0: dwmmc@ff0d0000 {
 237                 compatible = "rockchip,rk3288-dw-mshc";
 238                 clock-freq-min-max = <400000 150000000>;
 239                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 240                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 241                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 242                 fifo-depth = <0x100>;
 243                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 244                 reg = <0xff0d0000 0x4000>;
 245                 status = "disabled";
 246         };
 247
 248         sdio1: dwmmc@ff0e0000 {
 249                 compatible = "rockchip,rk3288-dw-mshc";
 250                 clock-freq-min-max = <400000 150000000>;
 251                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 252                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 253                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 254                 fifo-depth = <0x100>;
 255                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 256                 reg = <0xff0e0000 0x4000>;
 257                 status = "disabled";
 258         };
 259
 260         emmc: dwmmc@ff0f0000 {
 261                 compatible = "rockchip,rk3288-dw-mshc";
 262                 clock-freq-min-max = <400000 150000000>;
 263                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 264                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 265                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 266                 fifo-depth = <0x100>;
 267                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 268                 reg = <0xff0f0000 0x4000>;
 269                 status = "disabled";
 270         };
 271
 272         saradc: saradc@ff100000 {
 273                 compatible = "rockchip,saradc";
 274                 reg = <0xff100000 0x100>;
 275                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 276                 #io-channel-cells = <1>;
 277                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 278                 clock-names = "saradc", "apb_pclk";
 279                 status = "disabled";
 280         };
 281
 282         spi0: spi@ff110000 {
 283                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 284                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 285                 clock-names = "spiclk", "apb_pclk";
 286                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 287                 dma-names = "tx", "rx";
 288                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 289                 pinctrl-names = "default";
 290                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 291                 reg = <0xff110000 0x1000>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 status = "disabled";
 295         };
 296
 297         spi1: spi@ff120000 {
 298                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 299                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 300                 clock-names = "spiclk", "apb_pclk";
 301                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 302                 dma-names = "tx", "rx";
 303                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 306                 reg = <0xff120000 0x1000>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 status = "disabled";
 310         };
 311
 312         spi2: spi@ff130000 {
 313                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 314                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 315                 clock-names = "spiclk", "apb_pclk";
 316                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 317                 dma-names = "tx", "rx";
 318                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 319                 pinctrl-names = "default";
 320                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 321                 reg = <0xff130000 0x1000>;
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324                 status = "disabled";
 325         };
 326
 327         i2c1: i2c@ff140000 {
 328                 compatible = "rockchip,rk3288-i2c";
 329                 reg = <0xff140000 0x1000>;
 330                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 clock-names = "i2c";
 334                 clocks = <&cru PCLK_I2C1>;
 335                 pinctrl-names = "default";
 336                 pinctrl-0 = <&i2c1_xfer>;
 337                 status = "disabled";
 338         };
 339
 340         i2c3: i2c@ff150000 {
 341                 compatible = "rockchip,rk3288-i2c";
 342                 reg = <0xff150000 0x1000>;
 343                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 344                 #address-cells = <1>;
 345                 #size-cells = <0>;
 346                 clock-names = "i2c";
 347                 clocks = <&cru PCLK_I2C3>;
 348                 pinctrl-names = "default";
 349                 pinctrl-0 = <&i2c3_xfer>;
 350                 status = "disabled";
 351         };
 352
 353         i2c4: i2c@ff160000 {
 354                 compatible = "rockchip,rk3288-i2c";
 355                 reg = <0xff160000 0x1000>;
 356                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 357                 #address-cells = <1>;
 358                 #size-cells = <0>;
 359                 clock-names = "i2c";
 360                 clocks = <&cru PCLK_I2C4>;
 361                 pinctrl-names = "default";
 362                 pinctrl-0 = <&i2c4_xfer>;
 363                 status = "disabled";
 364         };
 365
 366         i2c5: i2c@ff170000 {
 367                 compatible = "rockchip,rk3288-i2c";
 368                 reg = <0xff170000 0x1000>;
 369                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 clock-names = "i2c";
 373                 clocks = <&cru PCLK_I2C5>;
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&i2c5_xfer>;
 376                 status = "disabled";
 377         };
 378
 379         uart0: serial@ff180000 {
 380                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 381                 reg = <0xff180000 0x100>;
 382                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 383                 reg-shift = <2>;
 384                 reg-io-width = <4>;
 385                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 386                 clock-names = "baudclk", "apb_pclk";
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&uart0_xfer>;
 389                 status = "disabled";
 390         };
 391
 392         uart1: serial@ff190000 {
 393                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 394                 reg = <0xff190000 0x100>;
 395                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 396                 reg-shift = <2>;
 397                 reg-io-width = <4>;
 398                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 399                 clock-names = "baudclk", "apb_pclk";
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&uart1_xfer>;
 402                 status = "disabled";
 403         };
 404
 405         uart2: serial@ff690000 {
 406                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 407                 reg = <0xff690000 0x100>;
 408                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 409                 reg-shift = <2>;
 410                 reg-io-width = <4>;
 411                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 412                 clock-names = "baudclk", "apb_pclk";
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&uart2_xfer>;
 415                 status = "disabled";
 416         };
 417
 418         uart3: serial@ff1b0000 {
 419                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 420                 reg = <0xff1b0000 0x100>;
 421                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 422                 reg-shift = <2>;
 423                 reg-io-width = <4>;
 424                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 425                 clock-names = "baudclk", "apb_pclk";
 426                 pinctrl-names = "default";
 427                 pinctrl-0 = <&uart3_xfer>;
 428                 status = "disabled";
 429         };
 430
 431         uart4: serial@ff1c0000 {
 432                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 433                 reg = <0xff1c0000 0x100>;
 434                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 435                 reg-shift = <2>;
 436                 reg-io-width = <4>;
 437                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 438                 clock-names = "baudclk", "apb_pclk";
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&uart4_xfer>;
 441                 status = "disabled";
 442         };
 443
 444         thermal-zones {
 445                 #include "rk3288-thermal.dtsi"
 446         };
 447
 448         tsadc: tsadc@ff280000 {
 449                 compatible = "rockchip,rk3288-tsadc";
 450                 reg = <0xff280000 0x100>;
 451                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 452                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 453                 clock-names = "tsadc", "apb_pclk";
 454                 resets = <&cru SRST_TSADC>;
 455                 reset-names = "tsadc-apb";
 456                 pinctrl-names = "init", "default", "sleep";
 457                 pinctrl-0 = <&otp_gpio>;
 458                 pinctrl-1 = <&otp_out>;
 459                 pinctrl-2 = <&otp_gpio>;
 460                 #thermal-sensor-cells = <1>;
 461                 rockchip,hw-tshut-temp = <95000>;
 462                 status = "disabled";
 463         };
 464
 465         gmac: ethernet@ff290000 {
 466                 compatible = "rockchip,rk3288-gmac";
 467                 reg = <0xff290000 0x10000>;
 468                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 469                 interrupt-names = "macirq";
 470                 rockchip,grf = <&grf>;
 471                 clocks = <&cru SCLK_MAC>,
 472                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 473                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 474                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 475                 clock-names = "stmmaceth",
 476                         "mac_clk_rx", "mac_clk_tx",
 477                         "clk_mac_ref", "clk_mac_refout",
 478                         "aclk_mac", "pclk_mac";
 479                 resets = <&cru SRST_MAC>;
 480                 reset-names = "stmmaceth";
 481                 status = "disabled";
 482         };
 483
 484         usb_host0_ehci: usb@ff500000 {
 485                 compatible = "generic-ehci";
 486                 reg = <0xff500000 0x100>;
 487                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 488                 clocks = <&cru HCLK_USBHOST0>;
 489                 clock-names = "usbhost";
 490                 phys = <&usbphy1>;
 491                 phy-names = "usb";
 492                 status = "disabled";
 493         };
 494
 495         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 496
 497         usb_host1: usb@ff540000 {
 498                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 499                                 "snps,dwc2";
 500                 reg = <0xff540000 0x40000>;
 501                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 502                 clocks = <&cru HCLK_USBHOST1>;
 503                 clock-names = "otg";
 504                 dr_mode = "host";
 505                 phys = <&usbphy2>;
 506                 phy-names = "usb2-phy";
 507                 status = "disabled";
 508         };
 509
 510         usb_otg: usb@ff580000 {
 511                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 512                                 "snps,dwc2";
 513                 reg = <0xff580000 0x40000>;
 514                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 515                 clocks = <&cru HCLK_OTG0>;
 516                 clock-names = "otg";
 517                 dr_mode = "otg";
 518                 g-np-tx-fifo-size = <16>;
 519                 g-rx-fifo-size = <275>;
 520                 g-tx-fifo-size = <256 128 128 64 64 32>;
 521                 g-use-dma;
 522                 phys = <&usbphy0>;
 523                 phy-names = "usb2-phy";
 524                 status = "disabled";
 525         };
 526
 527         usb_hsic: usb@ff5c0000 {
 528                 compatible = "generic-ehci";
 529                 reg = <0xff5c0000 0x100>;
 530                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 531                 clocks = <&cru HCLK_HSIC>;
 532                 clock-names = "usbhost";
 533                 status = "disabled";
 534         };
 535
 536         i2c0: i2c@ff650000 {
 537                 compatible = "rockchip,rk3288-i2c";
 538                 reg = <0xff650000 0x1000>;
 539                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 clock-names = "i2c";
 543                 clocks = <&cru PCLK_I2C0>;
 544                 pinctrl-names = "default";
 545                 pinctrl-0 = <&i2c0_xfer>;
 546                 status = "disabled";
 547         };
 548
 549         i2c2: i2c@ff660000 {
 550                 compatible = "rockchip,rk3288-i2c";
 551                 reg = <0xff660000 0x1000>;
 552                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 clock-names = "i2c";
 556                 clocks = <&cru PCLK_I2C2>;
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&i2c2_xfer>;
 559                 status = "disabled";
 560         };
 561
 562         pwm0: pwm@ff680000 {
 563                 compatible = "rockchip,rk3288-pwm";
 564                 reg = <0xff680000 0x10>;
 565                 #pwm-cells = <3>;
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&pwm0_pin>;
 568                 clocks = <&cru PCLK_PWM>;
 569                 clock-names = "pwm";
 570                 status = "disabled";
 571         };
 572
 573         pwm1: pwm@ff680010 {
 574                 compatible = "rockchip,rk3288-pwm";
 575                 reg = <0xff680010 0x10>;
 576                 #pwm-cells = <3>;
 577                 pinctrl-names = "default";
 578                 pinctrl-0 = <&pwm1_pin>;
 579                 clocks = <&cru PCLK_PWM>;
 580                 clock-names = "pwm";
 581                 status = "disabled";
 582         };
 583
 584         pwm2: pwm@ff680020 {
 585                 compatible = "rockchip,rk3288-pwm";
 586                 reg = <0xff680020 0x10>;
 587                 #pwm-cells = <3>;
 588                 pinctrl-names = "default";
 589                 pinctrl-0 = <&pwm2_pin>;
 590                 clocks = <&cru PCLK_PWM>;
 591                 clock-names = "pwm";
 592                 status = "disabled";
 593         };
 594
 595         pwm3: pwm@ff680030 {
 596                 compatible = "rockchip,rk3288-pwm";
 597                 reg = <0xff680030 0x10>;
 598                 #pwm-cells = <2>;
 599                 pinctrl-names = "default";
 600                 pinctrl-0 = <&pwm3_pin>;
 601                 clocks = <&cru PCLK_PWM>;
 602                 clock-names = "pwm";
 603                 status = "disabled";
 604         };
 605
 606         bus_intmem@ff700000 {
 607                 compatible = "mmio-sram";
 608                 reg = <0xff700000 0x18000>;
 609                 #address-cells = <1>;
 610                 #size-cells = <1>;
 611                 ranges = <0 0xff700000 0x18000>;
 612                 smp-sram@0 {
 613                         compatible = "rockchip,rk3066-smp-sram";
 614                         reg = <0x00 0x10>;
 615                 };
 616         };
 617
 618         sram@ff720000 {
 619                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 620                 reg = <0xff720000 0x1000>;
 621         };
 622
 623         pmu: power-management@ff730000 {
 624                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 625                 reg = <0xff730000 0x100>;
 626
 627                 power: power-controller {
 628                         compatible = "rockchip,rk3288-power-controller";
 629                         #power-domain-cells = <1>;
 630                         #address-cells = <1>;
 631                         #size-cells = <0>;
 632
 633                         /*
 634                          * Note: Although SCLK_* are the working clocks
 635                          * of device without including on the NOC, needed for
 636                          * synchronous reset.
 637                          *
 638                          * The clocks on the which NOC:
 639                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 640                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 641                          * ACLK_RGA is on ACLK_RGA_NIU.
 642                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 643                          *
 644                          * Which clock are device clocks:
 645                          *      clocks          devices
 646                          *      *_IEP           IEP:Image Enhancement Processor
 647                          *      *_ISP           ISP:Image Signal Processing
 648                          *      *_VIP           VIP:Video Input Processor
 649                          *      *_VOP*          VOP:Visual Output Processor
 650                          *      *_RGA           RGA
 651                          *      *_EDP*          EDP
 652                          *      *_LVDS_*        LVDS
 653                          *      *_HDMI          HDMI
 654                          *      *_MIPI_*        MIPI
 655                          */
 656                         pd_vio {
 657                                 reg = <RK3288_PD_VIO>;
 658                                 clocks = <&cru ACLK_IEP>,
 659                                          <&cru ACLK_ISP>,
 660                                          <&cru ACLK_RGA>,
 661                                          <&cru ACLK_VIP>,
 662                                          <&cru ACLK_VOP0>,
 663                                          <&cru ACLK_VOP1>,
 664                                          <&cru DCLK_VOP0>,
 665                                          <&cru DCLK_VOP1>,
 666                                          <&cru HCLK_IEP>,
 667                                          <&cru HCLK_ISP>,
 668                                          <&cru HCLK_RGA>,
 669                                          <&cru HCLK_VIP>,
 670                                          <&cru HCLK_VOP0>,
 671                                          <&cru HCLK_VOP1>,
 672                                          <&cru PCLK_EDP_CTRL>,
 673                                          <&cru PCLK_HDMI_CTRL>,
 674                                          <&cru PCLK_LVDS_PHY>,
 675                                          <&cru PCLK_MIPI_CSI>,
 676                                          <&cru PCLK_MIPI_DSI0>,
 677                                          <&cru PCLK_MIPI_DSI1>,
 678                                          <&cru SCLK_EDP_24M>,
 679                                          <&cru SCLK_EDP>,
 680                                          <&cru SCLK_ISP_JPE>,
 681                                          <&cru SCLK_ISP>,
 682                                          <&cru SCLK_RGA>;
 683                         };
 684
 685                         /*
 686                          * Note: The following 3 are HEVC(H.265) clocks,
 687                          * and on the ACLK_HEVC_NIU (NOC).
 688                          */
 689                         pd_hevc {
 690                                 reg = <RK3288_PD_HEVC>;
 691                                 clocks = <&cru ACLK_HEVC>,
 692                                          <&cru SCLK_HEVC_CABAC>,
 693                                          <&cru SCLK_HEVC_CORE>;
 694                         };
 695
 696                         /*
 697                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 698                          * (video endecoder & decoder) clocks that on the
 699                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 700                          */
 701                         pd_video {
 702                                 reg = <RK3288_PD_VIDEO>;
 703                                 clocks = <&cru ACLK_VCODEC>,
 704                                          <&cru HCLK_VCODEC>;
 705                         };
 706
 707                         /*
 708                          * Note: ACLK_GPU is the GPU clock,
 709                          * and on the ACLK_GPU_NIU (NOC).
 710                          */
 711                         pd_gpu {
 712                                 reg = <RK3288_PD_GPU>;
 713                                 clocks = <&cru ACLK_GPU>;
 714                         };
 715                 };
 716         };
 717
 718         sgrf: syscon@ff740000 {
 719                 compatible = "rockchip,rk3288-sgrf", "syscon";
 720                 reg = <0xff740000 0x1000>;
 721         };
 722
 723         cru: clock-controller@ff760000 {
 724                 compatible = "rockchip,rk3288-cru";
 725                 reg = <0xff760000 0x1000>;
 726                 rockchip,grf = <&grf>;
 727                 #clock-cells = <1>;
 728                 #reset-cells = <1>;
 729                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 730                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 731                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 732                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 733                                   <&cru PCLK_PERI>;
 734                 assigned-clock-rates = <594000000>, <400000000>,
 735                                        <500000000>, <300000000>,
 736                                        <150000000>, <75000000>,
 737                                        <300000000>, <150000000>,
 738                                        <75000000>;
 739         };
 740
 741         grf: syscon@ff770000 {
 742                 compatible = "rockchip,rk3288-grf", "syscon";
 743                 reg = <0xff770000 0x1000>;
 744         };
 745
 746         wdt: watchdog@ff800000 {
 747                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 748                 reg = <0xff800000 0x100>;
 749                 clocks = <&cru PCLK_WDT>;
 750                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 751                 status = "disabled";
 752         };
 753
 754         spdif: sound@ff88b0000 {
 755                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 756                 reg = <0xff8b0000 0x10000>;
 757                 #sound-dai-cells = <0>;
 758                 clock-names = "hclk", "mclk";
 759                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 760                 dmas = <&dmac_bus_s 3>;
 761                 dma-names = "tx";
 762                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 763                 pinctrl-names = "default";
 764                 pinctrl-0 = <&spdif_tx>;
 765                 rockchip,grf = <&grf>;
 766                 status = "disabled";
 767         };
 768
 769         i2s: i2s@ff890000 {
 770                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 771                 reg = <0xff890000 0x10000>;
 772                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 773                 #address-cells = <1>;
 774                 #size-cells = <0>;
 775                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 776                 dma-names = "tx", "rx";
 777                 clock-names = "i2s_hclk", "i2s_clk";
 778                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 779                 pinctrl-names = "default";
 780                 pinctrl-0 = <&i2s0_bus>;
 781                 status = "disabled";
 782         };
 783
 784         vopb: vop@ff930000 {
 785                 compatible = "rockchip,rk3288-vop";
 786                 reg = <0xff930000 0x19c>;
 787                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 788                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 789                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 790                 power-domains = <&power RK3288_PD_VIO>;
 791                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 792                 reset-names = "axi", "ahb", "dclk";
 793                 iommus = <&vopb_mmu>;
 794                 status = "disabled";
 795
 796                 vopb_out: port {
 797                         #address-cells = <1>;
 798                         #size-cells = <0>;
 799
 800                         vopb_out_hdmi: endpoint@0 {
 801                                 reg = <0>;
 802                                 remote-endpoint = <&hdmi_in_vopb>;
 803                         };
 804                 };
 805         };
 806
 807         vopb_mmu: iommu@ff930300 {
 808                 compatible = "rockchip,iommu";
 809                 reg = <0xff930300 0x100>;
 810                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 811                 interrupt-names = "vopb_mmu";
 812                 power-domains = <&power RK3288_PD_VIO>;
 813                 #iommu-cells = <0>;
 814                 status = "disabled";
 815         };
 816
 817         vopl: vop@ff940000 {
 818                 compatible = "rockchip,rk3288-vop";
 819                 reg = <0xff940000 0x19c>;
 820                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 821                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 822                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 823                 power-domains = <&power RK3288_PD_VIO>;
 824                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 825                 reset-names = "axi", "ahb", "dclk";
 826                 iommus = <&vopl_mmu>;
 827                 status = "disabled";
 828
 829                 vopl_out: port {
 830                         #address-cells = <1>;
 831                         #size-cells = <0>;
 832
 833                         vopl_out_hdmi: endpoint@0 {
 834                                 reg = <0>;
 835                                 remote-endpoint = <&hdmi_in_vopl>;
 836                         };
 837                 };
 838         };
 839
 840         vopl_mmu: iommu@ff940300 {
 841                 compatible = "rockchip,iommu";
 842                 reg = <0xff940300 0x100>;
 843                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 844                 interrupt-names = "vopl_mmu";
 845                 power-domains = <&power RK3288_PD_VIO>;
 846                 #iommu-cells = <0>;
 847                 status = "disabled";
 848         };
 849
 850         hdmi: hdmi@ff980000 {
 851                 compatible = "rockchip,rk3288-dw-hdmi";
 852                 reg = <0xff980000 0x20000>;
 853                 reg-io-width = <4>;
 854                 rockchip,grf = <&grf>;
 855                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 856                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 857                 clock-names = "iahb", "isfr";
 858                 power-domains = <&power RK3288_PD_VIO>;
 859                 status = "disabled";
 860
 861                 ports {
 862                         hdmi_in: port {
 863                                 #address-cells = <1>;
 864                                 #size-cells = <0>;
 865                                 hdmi_in_vopb: endpoint@0 {
 866                                         reg = <0>;
 867                                         remote-endpoint = <&vopb_out_hdmi>;
 868                                 };
 869                                 hdmi_in_vopl: endpoint@1 {
 870                                         reg = <1>;
 871                                         remote-endpoint = <&vopl_out_hdmi>;
 872                                 };
 873                         };
 874                 };
 875         };
 876
 877         gic: interrupt-controller@ffc01000 {
 878                 compatible = "arm,gic-400";
 879                 interrupt-controller;
 880                 #interrupt-cells = <3>;
 881                 #address-cells = <0>;
 882
 883                 reg = <0xffc01000 0x1000>,
 884                       <0xffc02000 0x1000>,
 885                       <0xffc04000 0x2000>,
 886                       <0xffc06000 0x2000>;
 887                 interrupts = <GIC_PPI 9 0xf04>;
 888         };
 889
 890         usbphy: phy {
 891                 compatible = "rockchip,rk3288-usb-phy";
 892                 rockchip,grf = <&grf>;
 893                 #address-cells = <1>;
 894                 #size-cells = <0>;
 895                 status = "disabled";
 896
 897                 usbphy0: usb-phy0 {
 898                         #phy-cells = <0>;
 899                         reg = <0x320>;
 900                         clocks = <&cru SCLK_OTGPHY0>;
 901                         clock-names = "phyclk";
 902                 };
 903
 904                 usbphy1: usb-phy1 {
 905                         #phy-cells = <0>;
 906                         reg = <0x334>;
 907                         clocks = <&cru SCLK_OTGPHY1>;
 908                         clock-names = "phyclk";
 909                 };
 910
 911                 usbphy2: usb-phy2 {
 912                         #phy-cells = <0>;
 913                         reg = <0x348>;
 914                         clocks = <&cru SCLK_OTGPHY2>;
 915                         clock-names = "phyclk";
 916                 };
 917         };
 918
 919         pinctrl: pinctrl {
 920                 compatible = "rockchip,rk3288-pinctrl";
 921                 rockchip,grf = <&grf>;
 922                 rockchip,pmu = <&pmu>;
 923                 #address-cells = <1>;
 924                 #size-cells = <1>;
 925                 ranges;
 926
 927                 gpio0: gpio0@ff750000 {
 928                         compatible = "rockchip,gpio-bank";
 929                         reg =   <0xff750000 0x100>;
 930                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 931                         clocks = <&cru PCLK_GPIO0>;
 932
 933                         gpio-controller;
 934                         #gpio-cells = <2>;
 935
 936                         interrupt-controller;
 937                         #interrupt-cells = <2>;
 938                 };
 939
 940                 gpio1: gpio1@ff780000 {
 941                         compatible = "rockchip,gpio-bank";
 942                         reg = <0xff780000 0x100>;
 943                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 944                         clocks = <&cru PCLK_GPIO1>;
 945
 946                         gpio-controller;
 947                         #gpio-cells = <2>;
 948
 949                         interrupt-controller;
 950                         #interrupt-cells = <2>;
 951                 };
 952
 953                 gpio2: gpio2@ff790000 {
 954                         compatible = "rockchip,gpio-bank";
 955                         reg = <0xff790000 0x100>;
 956                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 957                         clocks = <&cru PCLK_GPIO2>;
 958
 959                         gpio-controller;
 960                         #gpio-cells = <2>;
 961
 962                         interrupt-controller;
 963                         #interrupt-cells = <2>;
 964                 };
 965
 966                 gpio3: gpio3@ff7a0000 {
 967                         compatible = "rockchip,gpio-bank";
 968                         reg = <0xff7a0000 0x100>;
 969                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 970                         clocks = <&cru PCLK_GPIO3>;
 971
 972                         gpio-controller;
 973                         #gpio-cells = <2>;
 974
 975                         interrupt-controller;
 976                         #interrupt-cells = <2>;
 977                 };
 978
 979                 gpio4: gpio4@ff7b0000 {
 980                         compatible = "rockchip,gpio-bank";
 981                         reg = <0xff7b0000 0x100>;
 982                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 983                         clocks = <&cru PCLK_GPIO4>;
 984
 985                         gpio-controller;
 986                         #gpio-cells = <2>;
 987
 988                         interrupt-controller;
 989                         #interrupt-cells = <2>;
 990                 };
 991
 992                 gpio5: gpio5@ff7c0000 {
 993                         compatible = "rockchip,gpio-bank";
 994                         reg = <0xff7c0000 0x100>;
 995                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 996                         clocks = <&cru PCLK_GPIO5>;
 997
 998                         gpio-controller;
 999                         #gpio-cells = <2>;
1000
1001                         interrupt-controller;
1002                         #interrupt-cells = <2>;
1003                 };
1004
1005                 gpio6: gpio6@ff7d0000 {
1006                         compatible = "rockchip,gpio-bank";
1007                         reg = <0xff7d0000 0x100>;
1008                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1009                         clocks = <&cru PCLK_GPIO6>;
1010
1011                         gpio-controller;
1012                         #gpio-cells = <2>;
1013
1014                         interrupt-controller;
1015                         #interrupt-cells = <2>;
1016                 };
1017
1018                 gpio7: gpio7@ff7e0000 {
1019                         compatible = "rockchip,gpio-bank";
1020                         reg = <0xff7e0000 0x100>;
1021                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1022                         clocks = <&cru PCLK_GPIO7>;
1023
1024                         gpio-controller;
1025                         #gpio-cells = <2>;
1026
1027                         interrupt-controller;
1028                         #interrupt-cells = <2>;
1029                 };
1030
1031                 gpio8: gpio8@ff7f0000 {
1032                         compatible = "rockchip,gpio-bank";
1033                         reg = <0xff7f0000 0x100>;
1034                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1035                         clocks = <&cru PCLK_GPIO8>;
1036
1037                         gpio-controller;
1038                         #gpio-cells = <2>;
1039
1040                         interrupt-controller;
1041                         #interrupt-cells = <2>;
1042                 };
1043
1044                 hdmi {
1045                         hdmi_ddc: hdmi-ddc {
1046                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1047                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1048                         };
1049                 };
1050
1051                 pcfg_pull_up: pcfg-pull-up {
1052                         bias-pull-up;
1053                 };
1054
1055                 pcfg_pull_down: pcfg-pull-down {
1056                         bias-pull-down;
1057                 };
1058
1059                 pcfg_pull_none: pcfg-pull-none {
1060                         bias-disable;
1061                 };
1062
1063                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1064                         bias-disable;
1065                         drive-strength = <12>;
1066                 };
1067
1068                 sleep {
1069                         global_pwroff: global-pwroff {
1070                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1071                         };
1072
1073                         ddrio_pwroff: ddrio-pwroff {
1074                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1075                         };
1076
1077                         ddr0_retention: ddr0-retention {
1078                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1079                         };
1080
1081                         ddr1_retention: ddr1-retention {
1082                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1083                         };
1084                 };
1085
1086                 i2c0 {
1087                         i2c0_xfer: i2c0-xfer {
1088                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1089                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1090                         };
1091                 };
1092
1093                 i2c1 {
1094                         i2c1_xfer: i2c1-xfer {
1095                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1096                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1097                         };
1098                 };
1099
1100                 i2c2 {
1101                         i2c2_xfer: i2c2-xfer {
1102                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1103                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1104                         };
1105                 };
1106
1107                 i2c3 {
1108                         i2c3_xfer: i2c3-xfer {
1109                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1110                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1111                         };
1112                 };
1113
1114                 i2c4 {
1115                         i2c4_xfer: i2c4-xfer {
1116                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1117                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1118                         };
1119                 };
1120
1121                 i2c5 {
1122                         i2c5_xfer: i2c5-xfer {
1123                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1124                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1125                         };
1126                 };
1127
1128                 i2s0 {
1129                         i2s0_bus: i2s0-bus {
1130                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1131                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1132                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1133                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1134                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1135                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1136                         };
1137                 };
1138
1139                 sdmmc {
1140                         sdmmc_clk: sdmmc-clk {
1141                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1142                         };
1143
1144                         sdmmc_cmd: sdmmc-cmd {
1145                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1146                         };
1147
1148                         sdmmc_cd: sdmcc-cd {
1149                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1150                         };
1151
1152                         sdmmc_bus1: sdmmc-bus1 {
1153                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1154                         };
1155
1156                         sdmmc_bus4: sdmmc-bus4 {
1157                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1158                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1159                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1160                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1161                         };
1162                 };
1163
1164                 sdio0 {
1165                         sdio0_bus1: sdio0-bus1 {
1166                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1167                         };
1168
1169                         sdio0_bus4: sdio0-bus4 {
1170                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1171                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1172                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1173                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1174                         };
1175
1176                         sdio0_cmd: sdio0-cmd {
1177                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1178                         };
1179
1180                         sdio0_clk: sdio0-clk {
1181                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1182                         };
1183
1184                         sdio0_cd: sdio0-cd {
1185                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1186                         };
1187
1188                         sdio0_wp: sdio0-wp {
1189                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1190                         };
1191
1192                         sdio0_pwr: sdio0-pwr {
1193                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1194                         };
1195
1196                         sdio0_bkpwr: sdio0-bkpwr {
1197                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1198                         };
1199
1200                         sdio0_int: sdio0-int {
1201                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1202                         };
1203                 };
1204
1205                 sdio1 {
1206                         sdio1_bus1: sdio1-bus1 {
1207                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1208                         };
1209
1210                         sdio1_bus4: sdio1-bus4 {
1211                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1212                                                 <3 25 4 &pcfg_pull_up>,
1213                                                 <3 26 4 &pcfg_pull_up>,
1214                                                 <3 27 4 &pcfg_pull_up>;
1215                         };
1216
1217                         sdio1_cd: sdio1-cd {
1218                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1219                         };
1220
1221                         sdio1_wp: sdio1-wp {
1222                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1223                         };
1224
1225                         sdio1_bkpwr: sdio1-bkpwr {
1226                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1227                         };
1228
1229                         sdio1_int: sdio1-int {
1230                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1231                         };
1232
1233                         sdio1_cmd: sdio1-cmd {
1234                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1235                         };
1236
1237                         sdio1_clk: sdio1-clk {
1238                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1239                         };
1240
1241                         sdio1_pwr: sdio1-pwr {
1242                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1243                         };
1244                 };
1245
1246                 emmc {
1247                         emmc_clk: emmc-clk {
1248                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1249                         };
1250
1251                         emmc_cmd: emmc-cmd {
1252                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1253                         };
1254
1255                         emmc_pwr: emmc-pwr {
1256                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1257                         };
1258
1259                         emmc_bus1: emmc-bus1 {
1260                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1261                         };
1262
1263                         emmc_bus4: emmc-bus4 {
1264                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1265                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1266                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1267                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1268                         };
1269
1270                         emmc_bus8: emmc-bus8 {
1271                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1272                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1273                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1274                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1275                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1276                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1277                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1278                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1279                         };
1280                 };
1281
1282                 spi0 {
1283                         spi0_clk: spi0-clk {
1284                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1285                         };
1286                         spi0_cs0: spi0-cs0 {
1287                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1288                         };
1289                         spi0_tx: spi0-tx {
1290                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1291                         };
1292                         spi0_rx: spi0-rx {
1293                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1294                         };
1295                         spi0_cs1: spi0-cs1 {
1296                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1297                         };
1298                 };
1299                 spi1 {
1300                         spi1_clk: spi1-clk {
1301                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1302                         };
1303                         spi1_cs0: spi1-cs0 {
1304                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1305                         };
1306                         spi1_rx: spi1-rx {
1307                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1308                         };
1309                         spi1_tx: spi1-tx {
1310                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1311                         };
1312                 };
1313
1314                 spi2 {
1315                         spi2_cs1: spi2-cs1 {
1316                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1317                         };
1318                         spi2_clk: spi2-clk {
1319                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1320                         };
1321                         spi2_cs0: spi2-cs0 {
1322                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1323                         };
1324                         spi2_rx: spi2-rx {
1325                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1326                         };
1327                         spi2_tx: spi2-tx {
1328                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1329                         };
1330                 };
1331
1332                 uart0 {
1333                         uart0_xfer: uart0-xfer {
1334                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1335                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1336                         };
1337
1338                         uart0_cts: uart0-cts {
1339                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1340                         };
1341
1342                         uart0_rts: uart0-rts {
1343                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1344                         };
1345                 };
1346
1347                 uart1 {
1348                         uart1_xfer: uart1-xfer {
1349                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1350                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1351                         };
1352
1353                         uart1_cts: uart1-cts {
1354                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1355                         };
1356
1357                         uart1_rts: uart1-rts {
1358                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1359                         };
1360                 };
1361
1362                 uart2 {
1363                         uart2_xfer: uart2-xfer {
1364                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1365                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1366                         };
1367                         /* no rts / cts for uart2 */
1368                 };
1369
1370                 uart3 {
1371                         uart3_xfer: uart3-xfer {
1372                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1373                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1374                         };
1375
1376                         uart3_cts: uart3-cts {
1377                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1378                         };
1379
1380                         uart3_rts: uart3-rts {
1381                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1382                         };
1383                 };
1384
1385                 uart4 {
1386                         uart4_xfer: uart4-xfer {
1387                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1388                                                 <5 13 3 &pcfg_pull_none>;
1389                         };
1390
1391                         uart4_cts: uart4-cts {
1392                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1393                         };
1394
1395                         uart4_rts: uart4-rts {
1396                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1397                         };
1398                 };
1399
1400                 tsadc {
1401                         otp_gpio: otp-gpio {
1402                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1403                         };
1404
1405                         otp_out: otp-out {
1406                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1407                         };
1408                 };
1409
1410                 pwm0 {
1411                         pwm0_pin: pwm0-pin {
1412                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1413                         };
1414                 };
1415
1416                 pwm1 {
1417                         pwm1_pin: pwm1-pin {
1418                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1419                         };
1420                 };
1421
1422                 pwm2 {
1423                         pwm2_pin: pwm2-pin {
1424                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1425                         };
1426                 };
1427
1428                 pwm3 {
1429                         pwm3_pin: pwm3-pin {
1430                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1431                         };
1432                 };
1433
1434                 gmac {
1435                         rgmii_pins: rgmii-pins {
1436                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1437                                                 <3 31 3 &pcfg_pull_none>,
1438                                                 <3 26 3 &pcfg_pull_none>,
1439                                                 <3 27 3 &pcfg_pull_none>,
1440                                                 <3 28 3 &pcfg_pull_none_12ma>,
1441                                                 <3 29 3 &pcfg_pull_none_12ma>,
1442                                                 <3 24 3 &pcfg_pull_none_12ma>,
1443                                                 <3 25 3 &pcfg_pull_none_12ma>,
1444                                                 <4 0 3 &pcfg_pull_none>,
1445                                                 <4 5 3 &pcfg_pull_none>,
1446                                                 <4 6 3 &pcfg_pull_none>,
1447                                                 <4 9 3 &pcfg_pull_none_12ma>,
1448                                                 <4 4 3 &pcfg_pull_none_12ma>,
1449                                                 <4 1 3 &pcfg_pull_none>,
1450                                                 <4 3 3 &pcfg_pull_none>;
1451                         };
1452
1453                         rmii_pins: rmii-pins {
1454                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1455                                                 <3 31 3 &pcfg_pull_none>,
1456                                                 <3 28 3 &pcfg_pull_none>,
1457                                                 <3 29 3 &pcfg_pull_none>,
1458                                                 <4 0 3 &pcfg_pull_none>,
1459                                                 <4 5 3 &pcfg_pull_none>,
1460                                                 <4 4 3 &pcfg_pull_none>,
1461                                                 <4 1 3 &pcfg_pull_none>,
1462                                                 <4 2 3 &pcfg_pull_none>,
1463                                                 <4 3 3 &pcfg_pull_none>;
1464                         };
1465                 };
1466
1467                 spdif {
1468                         spdif_tx: spdif-tx {
1469                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1470                         };
1471                 };
1472         };
1473 };