arch/arm/boot/dts/rk3xxx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/soc/rockchip,boot-mode.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 ethernet0 = &emac;
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23                 i2c4 = &i2c4;
  24                 mshc0 = &emmc;
  25                 mshc1 = &mmc0;
  26                 mshc2 = &mmc1;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &uart2;
  30                 serial3 = &uart3;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33         };
  34
  35         amba {
  36                 compatible = "simple-bus";
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 ranges;
  40
  41                 dmac1_s: dma-controller@20018000 {
  42                         compatible = "arm,pl330", "arm,primecell";
  43                         reg = <0x20018000 0x4000>;
  44                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  45                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  46                         #dma-cells = <1>;
  47                         arm,pl330-broken-no-flushp;
  48                         clocks = <&cru ACLK_DMA1>;
  49                         clock-names = "apb_pclk";
  50                 };
  51
  52                 dmac1_ns: dma-controller@2001c000 {
  53                         compatible = "arm,pl330", "arm,primecell";
  54                         reg = <0x2001c000 0x4000>;
  55                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  56                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  57                         #dma-cells = <1>;
  58                         arm,pl330-broken-no-flushp;
  59                         clocks = <&cru ACLK_DMA1>;
  60                         clock-names = "apb_pclk";
  61                         status = "disabled";
  62                 };
  63
  64                 dmac2: dma-controller@20078000 {
  65                         compatible = "arm,pl330", "arm,primecell";
  66                         reg = <0x20078000 0x4000>;
  67                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  68                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  69                         #dma-cells = <1>;
  70                         arm,pl330-broken-no-flushp;
  71                         clocks = <&cru ACLK_DMA2>;
  72                         clock-names = "apb_pclk";
  73                 };
  74         };
  75
  76         xin24m: oscillator {
  77                 compatible = "fixed-clock";
  78                 clock-frequency = <24000000>;
  79                 #clock-cells = <0>;
  80                 clock-output-names = "xin24m";
  81         };
  82
  83         gpu: gpu@10090000 {
  84                 compatible = "arm,mali-400";
  85                 reg = <0x10090000 0x10000>;
  86                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
  87                 clock-names = "bus", "core";
  88                 assigned-clocks = <&cru ACLK_GPU>;
  89                 assigned-clock-rates = <100000000>;
  90                 resets = <&cru SRST_GPU>;
  91                 status = "disabled";
  92         };
  93
  94         L2: l2-cache-controller@10138000 {
  95                 compatible = "arm,pl310-cache";
  96                 reg = <0x10138000 0x1000>;
  97                 cache-unified;
  98                 cache-level = <2>;
  99         };
 100
 101         scu@1013c000 {
 102                 compatible = "arm,cortex-a9-scu";
 103                 reg = <0x1013c000 0x100>;
 104         };
 105
 106         global_timer: global-timer@1013c200 {
 107                 compatible = "arm,cortex-a9-global-timer";
 108                 reg = <0x1013c200 0x20>;
 109                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 110                 clocks = <&cru CORE_PERI>;
 111                 status = "disabled";
 112                 /* The clock source and the sched_clock provided by the arm_global_timer
 113                  * on Rockchip rk3066a/rk3188 are quite unstable because their rates
 114                  * depend on the CPU frequency.
 115                  * Keep the arm_global_timer disabled in order to have the
 116                  * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
 117                  */
 118         };
 119
 120         local_timer: local-timer@1013c600 {
 121                 compatible = "arm,cortex-a9-twd-timer";
 122                 reg = <0x1013c600 0x20>;
 123                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 124                 clocks = <&cru CORE_PERI>;
 125         };
 126
 127         gic: interrupt-controller@1013d000 {
 128                 compatible = "arm,cortex-a9-gic";
 129                 interrupt-controller;
 130                 #interrupt-cells = <3>;
 131                 reg = <0x1013d000 0x1000>,
 132                       <0x1013c100 0x0100>;
 133         };
 134
 135         uart0: serial@10124000 {
 136                 compatible = "snps,dw-apb-uart";
 137                 reg = <0x10124000 0x400>;
 138                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 139                 reg-shift = <2>;
 140                 reg-io-width = <1>;
 141                 clock-names = "baudclk", "apb_pclk";
 142                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 143                 status = "disabled";
 144         };
 145
 146         uart1: serial@10126000 {
 147                 compatible = "snps,dw-apb-uart";
 148                 reg = <0x10126000 0x400>;
 149                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 150                 reg-shift = <2>;
 151                 reg-io-width = <1>;
 152                 clock-names = "baudclk", "apb_pclk";
 153                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 154                 status = "disabled";
 155         };
 156
 157         usb_otg: usb@10180000 {
 158                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 159                 reg = <0x10180000 0x40000>;
 160                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 161                 clocks = <&cru HCLK_OTG0>;
 162                 clock-names = "otg";
 163                 dr_mode = "otg";
 164                 g-np-tx-fifo-size = <16>;
 165                 g-rx-fifo-size = <275>;
 166                 g-tx-fifo-size = <256 128 128 64 64 32>;
 167                 phys = <&usbphy0>;
 168                 phy-names = "usb2-phy";
 169                 status = "disabled";
 170         };
 171
 172         usb_host: usb@101c0000 {
 173                 compatible = "snps,dwc2";
 174                 reg = <0x101c0000 0x40000>;
 175                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&cru HCLK_OTG1>;
 177                 clock-names = "otg";
 178                 dr_mode = "host";
 179                 phys = <&usbphy1>;
 180                 phy-names = "usb2-phy";
 181                 status = "disabled";
 182         };
 183
 184         emac: ethernet@10204000 {
 185                 compatible = "snps,arc-emac";
 186                 reg = <0x10204000 0x3c>;
 187                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 188                 #address-cells = <1>;
 189                 #size-cells = <0>;
 190
 191                 rockchip,grf = <&grf>;
 192
 193                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 194                 clock-names = "hclk", "macref";
 195                 max-speed = <100>;
 196                 phy-mode = "rmii";
 197
 198                 status = "disabled";
 199         };
 200
 201         mmc0: dwmmc@10214000 {
 202                 compatible = "rockchip,rk2928-dw-mshc";
 203                 reg = <0x10214000 0x1000>;
 204                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 205                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 206                 clock-names = "biu", "ciu";
 207                 dmas = <&dmac2 1>;
 208                 dma-names = "rx-tx";
 209                 fifo-depth = <256>;
 210                 resets = <&cru SRST_SDMMC>;
 211                 reset-names = "reset";
 212                 status = "disabled";
 213         };
 214
 215         mmc1: dwmmc@10218000 {
 216                 compatible = "rockchip,rk2928-dw-mshc";
 217                 reg = <0x10218000 0x1000>;
 218                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 220                 clock-names = "biu", "ciu";
 221                 dmas = <&dmac2 3>;
 222                 dma-names = "rx-tx";
 223                 fifo-depth = <256>;
 224                 resets = <&cru SRST_SDIO>;
 225                 reset-names = "reset";
 226                 status = "disabled";
 227         };
 228
 229         emmc: dwmmc@1021c000 {
 230                 compatible = "rockchip,rk2928-dw-mshc";
 231                 reg = <0x1021c000 0x1000>;
 232                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 234                 clock-names = "biu", "ciu";
 235                 dmas = <&dmac2 4>;
 236                 dma-names = "rx-tx";
 237                 fifo-depth = <256>;
 238                 resets = <&cru SRST_EMMC>;
 239                 reset-names = "reset";
 240                 status = "disabled";
 241         };
 242
 243         pmu: pmu@20004000 {
 244                 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
 245                 reg = <0x20004000 0x100>;
 246
 247                 reboot-mode {
 248                         compatible = "syscon-reboot-mode";
 249                         offset = <0x40>;
 250                         mode-normal = <BOOT_NORMAL>;
 251                         mode-recovery = <BOOT_RECOVERY>;
 252                         mode-bootloader = <BOOT_FASTBOOT>;
 253                         mode-loader = <BOOT_BL_DOWNLOAD>;
 254                 };
 255         };
 256
 257         grf: grf@20008000 {
 258                 compatible = "syscon";
 259                 reg = <0x20008000 0x200>;
 260         };
 261
 262         i2c0: i2c@2002d000 {
 263                 compatible = "rockchip,rk3066-i2c";
 264                 reg = <0x2002d000 0x1000>;
 265                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 266                 #address-cells = <1>;
 267                 #size-cells = <0>;
 268
 269                 rockchip,grf = <&grf>;
 270
 271                 clock-names = "i2c";
 272                 clocks = <&cru PCLK_I2C0>;
 273
 274                 status = "disabled";
 275         };
 276
 277         i2c1: i2c@2002f000 {
 278                 compatible = "rockchip,rk3066-i2c";
 279                 reg = <0x2002f000 0x1000>;
 280                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283
 284                 rockchip,grf = <&grf>;
 285
 286                 clocks = <&cru PCLK_I2C1>;
 287                 clock-names = "i2c";
 288
 289                 status = "disabled";
 290         };
 291
 292         pwm0: pwm@20030000 {
 293                 compatible = "rockchip,rk2928-pwm";
 294                 reg = <0x20030000 0x10>;
 295                 #pwm-cells = <2>;
 296                 clocks = <&cru PCLK_PWM01>;
 297                 status = "disabled";
 298         };
 299
 300         pwm1: pwm@20030010 {
 301                 compatible = "rockchip,rk2928-pwm";
 302                 reg = <0x20030010 0x10>;
 303                 #pwm-cells = <2>;
 304                 clocks = <&cru PCLK_PWM01>;
 305                 status = "disabled";
 306         };
 307
 308         wdt: watchdog@2004c000 {
 309                 compatible = "snps,dw-wdt";
 310                 reg = <0x2004c000 0x100>;
 311                 clocks = <&cru PCLK_WDT>;
 312                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 313                 status = "disabled";
 314         };
 315
 316         pwm2: pwm@20050020 {
 317                 compatible = "rockchip,rk2928-pwm";
 318                 reg = <0x20050020 0x10>;
 319                 #pwm-cells = <2>;
 320                 clocks = <&cru PCLK_PWM23>;
 321                 status = "disabled";
 322         };
 323
 324         pwm3: pwm@20050030 {
 325                 compatible = "rockchip,rk2928-pwm";
 326                 reg = <0x20050030 0x10>;
 327                 #pwm-cells = <2>;
 328                 clocks = <&cru PCLK_PWM23>;
 329                 status = "disabled";
 330         };
 331
 332         i2c2: i2c@20056000 {
 333                 compatible = "rockchip,rk3066-i2c";
 334                 reg = <0x20056000 0x1000>;
 335                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338
 339                 rockchip,grf = <&grf>;
 340
 341                 clocks = <&cru PCLK_I2C2>;
 342                 clock-names = "i2c";
 343
 344                 status = "disabled";
 345         };
 346
 347         i2c3: i2c@2005a000 {
 348                 compatible = "rockchip,rk3066-i2c";
 349                 reg = <0x2005a000 0x1000>;
 350                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 351                 #address-cells = <1>;
 352                 #size-cells = <0>;
 353
 354                 rockchip,grf = <&grf>;
 355
 356                 clocks = <&cru PCLK_I2C3>;
 357                 clock-names = "i2c";
 358
 359                 status = "disabled";
 360         };
 361
 362         i2c4: i2c@2005e000 {
 363                 compatible = "rockchip,rk3066-i2c";
 364                 reg = <0x2005e000 0x1000>;
 365                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368
 369                 rockchip,grf = <&grf>;
 370
 371                 clocks = <&cru PCLK_I2C4>;
 372                 clock-names = "i2c";
 373
 374                 status = "disabled";
 375         };
 376
 377         uart2: serial@20064000 {
 378                 compatible = "snps,dw-apb-uart";
 379                 reg = <0x20064000 0x400>;
 380                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 381                 reg-shift = <2>;
 382                 reg-io-width = <1>;
 383                 clock-names = "baudclk", "apb_pclk";
 384                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 385                 status = "disabled";
 386         };
 387
 388         uart3: serial@20068000 {
 389                 compatible = "snps,dw-apb-uart";
 390                 reg = <0x20068000 0x400>;
 391                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 392                 reg-shift = <2>;
 393                 reg-io-width = <1>;
 394                 clock-names = "baudclk", "apb_pclk";
 395                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 396                 status = "disabled";
 397         };
 398
 399         saradc: saradc@2006c000 {
 400                 compatible = "rockchip,saradc";
 401                 reg = <0x2006c000 0x100>;
 402                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 403                 #io-channel-cells = <1>;
 404                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 405                 clock-names = "saradc", "apb_pclk";
 406                 resets = <&cru SRST_SARADC>;
 407                 reset-names = "saradc-apb";
 408                 status = "disabled";
 409         };
 410
 411         spi0: spi@20070000 {
 412                 compatible = "rockchip,rk3066-spi";
 413                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 414                 clock-names = "spiclk", "apb_pclk";
 415                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 416                 reg = <0x20070000 0x1000>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 dmas = <&dmac2 10>, <&dmac2 11>;
 420                 dma-names = "tx", "rx";
 421                 status = "disabled";
 422         };
 423
 424         spi1: spi@20074000 {
 425                 compatible = "rockchip,rk3066-spi";
 426                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 427                 clock-names = "spiclk", "apb_pclk";
 428                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 429                 reg = <0x20074000 0x1000>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 dmas = <&dmac2 12>, <&dmac2 13>;
 433                 dma-names = "tx", "rx";
 434                 status = "disabled";
 435         };
 436 };