arch/arm/boot/dts/stih410.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Peter Griffin <peter.griffin@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih410-clock.dtsi"
  10 #include "stih407-family.dtsi"
  11 #include "stih410-pinctrl.dtsi"
  12 #include <dt-bindings/gpio/gpio.h>
  13 / {
  14         aliases {
  15                 bdisp0 = &bdisp0;
  16         };
  17
  18         soc {
  19                 usb2_picophy1: phy2 {
  20                         compatible = "st,stih407-usb2-phy";
  21                         #phy-cells = <0>;
  22                         st,syscfg = <&syscfg_core 0xf8 0xf4>;
  23                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
  24                                  <&picophyreset STIH407_PICOPHY0_RESET>;
  25                         reset-names = "global", "port";
  26
  27                         status = "disabled";
  28                 };
  29
  30                 usb2_picophy2: phy3 {
  31                         compatible = "st,stih407-usb2-phy";
  32                         #phy-cells = <0>;
  33                         st,syscfg = <&syscfg_core 0xfc 0xf4>;
  34                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
  35                                  <&picophyreset STIH407_PICOPHY1_RESET>;
  36                         reset-names = "global", "port";
  37
  38                         status = "disabled";
  39                 };
  40
  41                 ohci0: usb@9a03c00 {
  42                         compatible = "st,st-ohci-300x";
  43                         reg = <0x9a03c00 0x100>;
  44                         interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
  45                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  46                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  47                         resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
  48                                  <&softreset STIH407_USB2_PORT0_SOFTRESET>;
  49                         reset-names = "power", "softreset";
  50                         phys = <&usb2_picophy1>;
  51                         phy-names = "usb";
  52
  53                         status = "disabled";
  54                 };
  55
  56                 ehci0: usb@9a03e00 {
  57                         compatible = "st,st-ehci-300x";
  58                         reg = <0x9a03e00 0x100>;
  59                         interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
  60                         pinctrl-names = "default";
  61                         pinctrl-0 = <&pinctrl_usb0>;
  62                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  63                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  64                         resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
  65                                  <&softreset STIH407_USB2_PORT0_SOFTRESET>;
  66                         reset-names = "power", "softreset";
  67                         phys = <&usb2_picophy1>;
  68                         phy-names = "usb";
  69
  70                         status = "disabled";
  71                 };
  72
  73                 ohci1: usb@9a83c00 {
  74                         compatible = "st,st-ohci-300x";
  75                         reg = <0x9a83c00 0x100>;
  76                         interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
  77                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  78                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  79                         resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
  80                                  <&softreset STIH407_USB2_PORT1_SOFTRESET>;
  81                         reset-names = "power", "softreset";
  82                         phys = <&usb2_picophy2>;
  83                         phy-names = "usb";
  84
  85                         status = "disabled";
  86                 };
  87
  88                 ehci1: usb@9a83e00 {
  89                         compatible = "st,st-ehci-300x";
  90                         reg = <0x9a83e00 0x100>;
  91                         interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
  92                         pinctrl-names = "default";
  93                         pinctrl-0 = <&pinctrl_usb1>;
  94                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  95                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  96                         resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
  97                                  <&softreset STIH407_USB2_PORT1_SOFTRESET>;
  98                         reset-names = "power", "softreset";
  99                         phys = <&usb2_picophy2>;
 100                         phy-names = "usb";
 101
 102                         status = "disabled";
 103                 };
 104
 105                 sti-display-subsystem {
 106                         compatible = "st,sti-display-subsystem";
 107                         #address-cells = <1>;
 108                         #size-cells = <1>;
 109
 110                         assigned-clocks = <&clk_s_d2_quadfs 0>,
 111                                           <&clk_s_d2_quadfs 1>,
 112                                           <&clk_s_c0_pll1 0>,
 113                                           <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 114                                           <&clk_s_c0_flexgen CLK_MAIN_DISP>,
 115                                           <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 116                                           <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 117                                           <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 118                                           <&clk_s_d2_flexgen CLK_PIX_GDP2>,
 119                                           <&clk_s_d2_flexgen CLK_PIX_GDP3>,
 120                                           <&clk_s_d2_flexgen CLK_PIX_GDP4>;
 121
 122                         assigned-clock-parents = <0>,
 123                                                  <0>,
 124                                                  <0>,
 125                                                  <&clk_s_c0_pll1 0>,
 126                                                  <&clk_s_c0_pll1 0>,
 127                                                  <&clk_s_d2_quadfs 0>,
 128                                                  <&clk_s_d2_quadfs 1>,
 129                                                  <&clk_s_d2_quadfs 0>,
 130                                                  <&clk_s_d2_quadfs 0>,
 131                                                  <&clk_s_d2_quadfs 0>,
 132                                                  <&clk_s_d2_quadfs 0>;
 133
 134                         assigned-clock-rates = <297000000>,
 135                                                <297000000>,
 136                                                <0>,
 137                                                <400000000>,
 138                                                <400000000>;
 139
 140                         ranges;
 141
 142                         sti-compositor@9d11000 {
 143                                 compatible = "st,stih407-compositor";
 144                                 reg = <0x9d11000 0x1000>;
 145
 146                                 clock-names = "compo_main",
 147                                               "compo_aux",
 148                                               "pix_main",
 149                                               "pix_aux",
 150                                               "pix_gdp1",
 151                                               "pix_gdp2",
 152                                               "pix_gdp3",
 153                                               "pix_gdp4",
 154                                               "main_parent",
 155                                               "aux_parent";
 156
 157                                 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 158                                          <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 159                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 160                                          <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 161                                          <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 162                                          <&clk_s_d2_flexgen CLK_PIX_GDP2>,
 163                                          <&clk_s_d2_flexgen CLK_PIX_GDP3>,
 164                                          <&clk_s_d2_flexgen CLK_PIX_GDP4>,
 165                                          <&clk_s_d2_quadfs 0>,
 166                                          <&clk_s_d2_quadfs 1>;
 167
 168                                 reset-names = "compo-main", "compo-aux";
 169                                 resets = <&softreset STIH407_COMPO_SOFTRESET>,
 170                                          <&softreset STIH407_COMPO_SOFTRESET>;
 171                                 st,vtg = <&vtg_main>, <&vtg_aux>;
 172                         };
 173
 174                         sti-tvout@8d08000 {
 175                                 compatible = "st,stih407-tvout";
 176                                 reg = <0x8d08000 0x1000>;
 177                                 reg-names = "tvout-reg";
 178                                 reset-names = "tvout";
 179                                 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
 180                                 #address-cells = <1>;
 181                                 #size-cells = <1>;
 182                                 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 183                                                   <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 184                                                   <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 185                                                   <&clk_s_d0_flexgen CLK_PCM_0>,
 186                                                   <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 187                                                   <&clk_s_d2_flexgen CLK_HDDAC>;
 188
 189                                 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
 190                                                          <&clk_tmdsout_hdmi>,
 191                                                          <&clk_s_d2_quadfs 0>,
 192                                                          <&clk_s_d0_quadfs 0>,
 193                                                          <&clk_s_d2_quadfs 0>,
 194                                                          <&clk_s_d2_quadfs 0>;
 195                         };
 196
 197                         sti-hdmi@8d04000 {
 198                                 compatible = "st,stih407-hdmi";
 199                                 reg = <0x8d04000 0x1000>;
 200                                 reg-names = "hdmi-reg";
 201                                 interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
 202                                 interrupt-names = "irq";
 203                                 clock-names = "pix",
 204                                               "tmds",
 205                                               "phy",
 206                                               "audio",
 207                                               "main_parent",
 208                                               "aux_parent";
 209
 210                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 211                                          <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 212                                          <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 213                                          <&clk_s_d0_flexgen CLK_PCM_0>,
 214                                          <&clk_s_d2_quadfs 0>,
 215                                          <&clk_s_d2_quadfs 1>;
 216
 217                                 hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
 218                                 reset-names = "hdmi";
 219                                 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
 220                                 ddc = <&hdmiddc>;
 221                         };
 222
 223                         sti-hda@8d02000 {
 224                                 compatible = "st,stih407-hda";
 225                                 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
 226                                 reg-names = "hda-reg", "video-dacs-ctrl";
 227                                 clock-names = "pix",
 228                                               "hddac",
 229                                               "main_parent",
 230                                               "aux_parent";
 231                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 232                                          <&clk_s_d2_flexgen CLK_HDDAC>,
 233                                          <&clk_s_d2_quadfs 0>,
 234                                          <&clk_s_d2_quadfs 1>;
 235                         };
 236                 };
 237
 238                 bdisp0:bdisp@9f10000 {
 239                         compatible = "st,stih407-bdisp";
 240                         reg = <0x9f10000 0x1000>;
 241                         interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
 242                         clock-names = "bdisp";
 243                         clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
 244                 };
 245
 246                 hva@8c85000 {
 247                         compatible = "st,st-hva";
 248                         reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
 249                         reg-names = "hva_registers", "hva_esram";
 250                         interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
 251                                      <GIC_SPI 59 IRQ_TYPE_NONE>;
 252                         clock-names = "clk_hva";
 253                         clocks = <&clk_s_c0_flexgen CLK_HVA>;
 254                 };
 255
 256                 thermal@91a0000 {
 257                         compatible = "st,stih407-thermal";
 258                         reg = <0x91a0000 0x28>;
 259                         clock-names = "thermal";
 260                         clocks = <&clk_sysin>;
 261                         interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
 262                 };
 263         };
 264 };