GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / stm32mp157-pinctrl.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5  */
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8 / {
9         soc {
10                 pinctrl: pin-controller@50002000 {
11                         #address-cells = <1>;
12                         #size-cells = <1>;
13                         compatible = "st,stm32mp157-pinctrl";
14                         ranges = <0 0x50002000 0xa400>;
15                         interrupt-parent = <&exti>;
16                         st,syscfg = <&exti 0x60 0xff>;
17                         pins-are-numbered;
18
19                         gpioa: gpio@50002000 {
20                                 gpio-controller;
21                                 #gpio-cells = <2>;
22                                 interrupt-controller;
23                                 #interrupt-cells = <2>;
24                                 reg = <0x0 0x400>;
25                                 clocks = <&rcc GPIOA>;
26                                 st,bank-name = "GPIOA";
27                                 ngpios = <16>;
28                                 gpio-ranges = <&pinctrl 0 0 16>;
29                         };
30
31                         gpiob: gpio@50003000 {
32                                 gpio-controller;
33                                 #gpio-cells = <2>;
34                                 interrupt-controller;
35                                 #interrupt-cells = <2>;
36                                 reg = <0x1000 0x400>;
37                                 clocks = <&rcc GPIOB>;
38                                 st,bank-name = "GPIOB";
39                                 ngpios = <16>;
40                                 gpio-ranges = <&pinctrl 0 16 16>;
41                         };
42
43                         gpioc: gpio@50004000 {
44                                 gpio-controller;
45                                 #gpio-cells = <2>;
46                                 interrupt-controller;
47                                 #interrupt-cells = <2>;
48                                 reg = <0x2000 0x400>;
49                                 clocks = <&rcc GPIOC>;
50                                 st,bank-name = "GPIOC";
51                                 ngpios = <16>;
52                                 gpio-ranges = <&pinctrl 0 32 16>;
53                         };
54
55                         gpiod: gpio@50005000 {
56                                 gpio-controller;
57                                 #gpio-cells = <2>;
58                                 interrupt-controller;
59                                 #interrupt-cells = <2>;
60                                 reg = <0x3000 0x400>;
61                                 clocks = <&rcc GPIOD>;
62                                 st,bank-name = "GPIOD";
63                                 ngpios = <16>;
64                                 gpio-ranges = <&pinctrl 0 48 16>;
65                         };
66
67                         gpioe: gpio@50006000 {
68                                 gpio-controller;
69                                 #gpio-cells = <2>;
70                                 interrupt-controller;
71                                 #interrupt-cells = <2>;
72                                 reg = <0x4000 0x400>;
73                                 clocks = <&rcc GPIOE>;
74                                 st,bank-name = "GPIOE";
75                                 ngpios = <16>;
76                                 gpio-ranges = <&pinctrl 0 64 16>;
77                         };
78
79                         gpiof: gpio@50007000 {
80                                 gpio-controller;
81                                 #gpio-cells = <2>;
82                                 interrupt-controller;
83                                 #interrupt-cells = <2>;
84                                 reg = <0x5000 0x400>;
85                                 clocks = <&rcc GPIOF>;
86                                 st,bank-name = "GPIOF";
87                                 ngpios = <16>;
88                                 gpio-ranges = <&pinctrl 0 80 16>;
89                         };
90
91                         gpiog: gpio@50008000 {
92                                 gpio-controller;
93                                 #gpio-cells = <2>;
94                                 interrupt-controller;
95                                 #interrupt-cells = <2>;
96                                 reg = <0x6000 0x400>;
97                                 clocks = <&rcc GPIOG>;
98                                 st,bank-name = "GPIOG";
99                                 ngpios = <16>;
100                                 gpio-ranges = <&pinctrl 0 96 16>;
101                         };
102
103                         gpioh: gpio@50009000 {
104                                 gpio-controller;
105                                 #gpio-cells = <2>;
106                                 interrupt-controller;
107                                 #interrupt-cells = <2>;
108                                 reg = <0x7000 0x400>;
109                                 clocks = <&rcc GPIOH>;
110                                 st,bank-name = "GPIOH";
111                                 ngpios = <16>;
112                                 gpio-ranges = <&pinctrl 0 112 16>;
113                         };
114
115                         gpioi: gpio@5000a000 {
116                                 gpio-controller;
117                                 #gpio-cells = <2>;
118                                 interrupt-controller;
119                                 #interrupt-cells = <2>;
120                                 reg = <0x8000 0x400>;
121                                 clocks = <&rcc GPIOI>;
122                                 st,bank-name = "GPIOI";
123                                 ngpios = <16>;
124                                 gpio-ranges = <&pinctrl 0 128 16>;
125                         };
126
127                         gpioj: gpio@5000b000 {
128                                 gpio-controller;
129                                 #gpio-cells = <2>;
130                                 interrupt-controller;
131                                 #interrupt-cells = <2>;
132                                 reg = <0x9000 0x400>;
133                                 clocks = <&rcc GPIOJ>;
134                                 st,bank-name = "GPIOJ";
135                                 ngpios = <16>;
136                                 gpio-ranges = <&pinctrl 0 144 16>;
137                         };
138
139                         gpiok: gpio@5000c000 {
140                                 gpio-controller;
141                                 #gpio-cells = <2>;
142                                 interrupt-controller;
143                                 #interrupt-cells = <2>;
144                                 reg = <0xa000 0x400>;
145                                 clocks = <&rcc GPIOK>;
146                                 st,bank-name = "GPIOK";
147                                 ngpios = <8>;
148                                 gpio-ranges = <&pinctrl 0 160 8>;
149                         };
150
151                         cec_pins_a: cec-0 {
152                                 pins {
153                                         pinmux = <STM32_PINMUX('A', 15, AF4)>;
154                                         bias-disable;
155                                         drive-open-drain;
156                                         slew-rate = <0>;
157                                 };
158                         };
159
160                         ethernet0_rgmii_pins_a: rgmii-0 {
161                                 pins1 {
162                                         pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
163                                                  <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
164                                                  <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
165                                                  <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
166                                                  <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
167                                                  <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
168                                                  <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
169                                                  <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
170                                                  <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
171                                         bias-disable;
172                                         drive-push-pull;
173                                         slew-rate = <3>;
174                                 };
175                                 pins2 {
176                                         pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
177                                                  <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
178                                                  <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
179                                                  <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
180                                                  <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
181                                                  <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
182                                         bias-disable;
183                                 };
184                         };
185
186                         ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
187                                 pins1 {
188                                         pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
189                                                  <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
190                                                  <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
191                                                  <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
192                                                  <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
193                                                  <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
194                                                  <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
195                                                  <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
196                                                  <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
197                                                  <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
198                                                  <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
199                                                  <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
200                                                  <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
201                                                  <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
202                                                  <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
203                                 };
204                         };
205
206                         i2c1_pins_a: i2c1-0 {
207                                 pins {
208                                         pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
209                                                  <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
210                                         bias-disable;
211                                         drive-open-drain;
212                                         slew-rate = <0>;
213                                 };
214                         };
215
216                         i2c2_pins_a: i2c2-0 {
217                                 pins {
218                                         pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
219                                                  <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
220                                         bias-disable;
221                                         drive-open-drain;
222                                         slew-rate = <0>;
223                                 };
224                         };
225
226                         i2c5_pins_a: i2c5-0 {
227                                 pins {
228                                         pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
229                                                  <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
230                                         bias-disable;
231                                         drive-open-drain;
232                                         slew-rate = <0>;
233                                 };
234                         };
235
236                         m_can1_pins_a: m-can1-0 {
237                                 pins1 {
238                                         pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
239                                         slew-rate = <1>;
240                                         drive-push-pull;
241                                         bias-disable;
242                                 };
243                                 pins2 {
244                                         pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
245                                         bias-disable;
246                                 };
247                         };
248
249                         pwm2_pins_a: pwm2-0 {
250                                 pins {
251                                         pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
252                                         bias-pull-down;
253                                         drive-push-pull;
254                                         slew-rate = <0>;
255                                 };
256                         };
257
258                         pwm8_pins_a: pwm8-0 {
259                                 pins {
260                                         pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
261                                         bias-pull-down;
262                                         drive-push-pull;
263                                         slew-rate = <0>;
264                                 };
265                         };
266
267                         pwm12_pins_a: pwm12-0 {
268                                 pins {
269                                         pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
270                                         bias-pull-down;
271                                         drive-push-pull;
272                                         slew-rate = <0>;
273                                 };
274                         };
275
276                         qspi_clk_pins_a: qspi-clk-0 {
277                                 pins {
278                                         pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
279                                         bias-disable;
280                                         drive-push-pull;
281                                         slew-rate = <3>;
282                                 };
283                         };
284
285                         qspi_bk1_pins_a: qspi-bk1-0 {
286                                 pins1 {
287                                         pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
288                                                  <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
289                                                  <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
290                                                  <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
291                                         bias-disable;
292                                         drive-push-pull;
293                                         slew-rate = <3>;
294                                 };
295                                 pins2 {
296                                         pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
297                                         bias-pull-up;
298                                         drive-push-pull;
299                                         slew-rate = <3>;
300                                 };
301                         };
302
303                         qspi_bk2_pins_a: qspi-bk2-0 {
304                                 pins1 {
305                                         pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
306                                                  <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
307                                                  <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
308                                                  <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
309                                         bias-disable;
310                                         drive-push-pull;
311                                         slew-rate = <3>;
312                                 };
313                                 pins2 {
314                                         pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
315                                         bias-pull-up;
316                                         drive-push-pull;
317                                         slew-rate = <3>;
318                                 };
319                         };
320
321                         uart4_pins_a: uart4-0 {
322                                 pins1 {
323                                         pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
324                                         bias-disable;
325                                         drive-push-pull;
326                                         slew-rate = <0>;
327                                 };
328                                 pins2 {
329                                         pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
330                                         bias-disable;
331                                 };
332                         };
333                 };
334
335                 pinctrl_z: pin-controller-z@54004000 {
336                         #address-cells = <1>;
337                         #size-cells = <1>;
338                         compatible = "st,stm32mp157-z-pinctrl";
339                         ranges = <0 0x54004000 0x400>;
340                         pins-are-numbered;
341                         interrupt-parent = <&exti>;
342                         st,syscfg = <&exti 0x60 0xff>;
343
344                         gpioz: gpio@54004000 {
345                                 gpio-controller;
346                                 #gpio-cells = <2>;
347                                 interrupt-controller;
348                                 #interrupt-cells = <2>;
349                                 reg = <0 0x400>;
350                                 clocks = <&rcc GPIOZ>;
351                                 st,bank-name = "GPIOZ";
352                                 st,bank-ioport = <11>;
353                                 ngpios = <8>;
354                                 gpio-ranges = <&pinctrl_z 0 400 8>;
355                         };
356
357                         i2c4_pins_a: i2c4-0 {
358                                 pins {
359                                         pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
360                                                  <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
361                                         bias-disable;
362                                         drive-open-drain;
363                                         slew-rate = <0>;
364                                 };
365                         };
366
367                         spi1_pins_a: spi1-0 {
368                                 pins1 {
369                                         pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
370                                                  <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
371                                         bias-disable;
372                                         drive-push-pull;
373                                         slew-rate = <1>;
374                                 };
375
376                                 pins2 {
377                                         pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
378                                         bias-disable;
379                                 };
380                         };
381                 };
382         };
383 };