GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / sun5i.dtsi
1 /*
2  * Copyright 2012-2015 Maxime Ripard
3  *
4  * Maxime Ripard <maxime.ripard@free-electrons.com>
5  *
6  * This file is dual-licensed: you can use it either under the terms
7  * of the GPL or the X11 license, at your option. Note that this dual
8  * licensing only applies to this file, and not this project as a
9  * whole.
10  *
11  *  a) This library is free software; you can redistribute it and/or
12  *     modify it under the terms of the GNU General Public License as
13  *     published by the Free Software Foundation; either version 2 of the
14  *     License, or (at your option) any later version.
15  *
16  *     This library is distributed in the hope that it will be useful,
17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  *     GNU General Public License for more details.
20  *
21  * Or, alternatively,
22  *
23  *  b) Permission is hereby granted, free of charge, to any person
24  *     obtaining a copy of this software and associated documentation
25  *     files (the "Software"), to deal in the Software without
26  *     restriction, including without limitation the rights to use,
27  *     copy, modify, merge, publish, distribute, sublicense, and/or
28  *     sell copies of the Software, and to permit persons to whom the
29  *     Software is furnished to do so, subject to the following
30  *     conditions:
31  *
32  *     The above copyright notice and this permission notice shall be
33  *     included in all copies or substantial portions of the Software.
34  *
35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42  *     OTHER DEALINGS IN THE SOFTWARE.
43  */
44
45 #include "skeleton.dtsi"
46
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/reset/sun5i-ccu.h>
50
51 / {
52         interrupt-parent = <&intc>;
53
54         cpus {
55                 #address-cells = <1>;
56                 #size-cells = <0>;
57
58                 cpu0: cpu@0 {
59                         device_type = "cpu";
60                         compatible = "arm,cortex-a8";
61                         reg = <0x0>;
62                         clocks = <&ccu CLK_CPU>;
63                 };
64         };
65
66         chosen {
67                 #address-cells = <1>;
68                 #size-cells = <1>;
69                 ranges;
70
71                 framebuffer@0 {
72                         compatible = "allwinner,simple-framebuffer",
73                                      "simple-framebuffer";
74                         allwinner,pipeline = "de_be0-lcd0";
75                         clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
76                                  <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
77                         status = "disabled";
78                 };
79
80                 framebuffer@1 {
81                         compatible = "allwinner,simple-framebuffer",
82                                      "simple-framebuffer";
83                         allwinner,pipeline = "de_be0-lcd0-tve0";
84                         clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
85                                  <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
86                                  <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
87                         status = "disabled";
88                 };
89         };
90
91         clocks {
92                 #address-cells = <1>;
93                 #size-cells = <1>;
94                 ranges;
95
96                 osc24M: clk@1c20050 {
97                         #clock-cells = <0>;
98                         compatible = "fixed-clock";
99                         clock-frequency = <24000000>;
100                         clock-output-names = "osc24M";
101                 };
102
103                 osc32k: clk@0 {
104                         #clock-cells = <0>;
105                         compatible = "fixed-clock";
106                         clock-frequency = <32768>;
107                         clock-output-names = "osc32k";
108                 };
109         };
110
111         soc@1c00000 {
112                 compatible = "simple-bus";
113                 #address-cells = <1>;
114                 #size-cells = <1>;
115                 ranges;
116
117                 system-control@1c00000 {
118                         compatible = "allwinner,sun5i-a13-system-control";
119                         reg = <0x01c00000 0x30>;
120                         #address-cells = <1>;
121                         #size-cells = <1>;
122                         ranges;
123
124                         sram_a: sram@0 {
125                                 compatible = "mmio-sram";
126                                 reg = <0x00000000 0xc000>;
127                                 #address-cells = <1>;
128                                 #size-cells = <1>;
129                                 ranges = <0 0x00000000 0xc000>;
130
131                                 emac_sram: sram-section@8000 {
132                                         compatible = "allwinner,sun5i-a13-sram-a3-a4",
133                                                      "allwinner,sun4i-a10-sram-a3-a4";
134                                         reg = <0x8000 0x4000>;
135                                         status = "disabled";
136                                 };
137                         };
138
139                         sram_d: sram@10000 {
140                                 compatible = "mmio-sram";
141                                 reg = <0x00010000 0x1000>;
142                                 #address-cells = <1>;
143                                 #size-cells = <1>;
144                                 ranges = <0 0x00010000 0x1000>;
145
146                                 otg_sram: sram-section@0 {
147                                         compatible = "allwinner,sun5i-a13-sram-d",
148                                                      "allwinner,sun4i-a10-sram-d";
149                                         reg = <0x0000 0x1000>;
150                                         status = "disabled";
151                                 };
152                         };
153
154                         sram_c: sram@1d00000 {
155                                 compatible = "mmio-sram";
156                                 reg = <0x01d00000 0xd0000>;
157                                 #address-cells = <1>;
158                                 #size-cells = <1>;
159                                 ranges = <0 0x01d00000 0xd0000>;
160
161                                 ve_sram: sram-section@0 {
162                                         compatible = "allwinner,sun5i-a13-sram-c1",
163                                                      "allwinner,sun4i-a10-sram-c1";
164                                         reg = <0x000000 0x80000>;
165                                 };
166                         };
167                 };
168
169                 dma: dma-controller@1c02000 {
170                         compatible = "allwinner,sun4i-a10-dma";
171                         reg = <0x01c02000 0x1000>;
172                         interrupts = <27>;
173                         clocks = <&ccu CLK_AHB_DMA>;
174                         #dma-cells = <2>;
175                 };
176
177                 nfc: nand@1c03000 {
178                         compatible = "allwinner,sun4i-a10-nand";
179                         reg = <0x01c03000 0x1000>;
180                         interrupts = <37>;
181                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
182                         clock-names = "ahb", "mod";
183                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
184                         dma-names = "rxtx";
185                         status = "disabled";
186                         #address-cells = <1>;
187                         #size-cells = <0>;
188                 };
189
190                 spi0: spi@1c05000 {
191                         compatible = "allwinner,sun4i-a10-spi";
192                         reg = <0x01c05000 0x1000>;
193                         interrupts = <10>;
194                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
195                         clock-names = "ahb", "mod";
196                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
197                                <&dma SUN4I_DMA_DEDICATED 26>;
198                         dma-names = "rx", "tx";
199                         status = "disabled";
200                         #address-cells = <1>;
201                         #size-cells = <0>;
202                 };
203
204                 spi1: spi@1c06000 {
205                         compatible = "allwinner,sun4i-a10-spi";
206                         reg = <0x01c06000 0x1000>;
207                         interrupts = <11>;
208                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
209                         clock-names = "ahb", "mod";
210                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
211                                <&dma SUN4I_DMA_DEDICATED 8>;
212                         dma-names = "rx", "tx";
213                         status = "disabled";
214                         #address-cells = <1>;
215                         #size-cells = <0>;
216                 };
217
218                 tve0: tv-encoder@1c0a000 {
219                         compatible = "allwinner,sun4i-a10-tv-encoder";
220                         reg = <0x01c0a000 0x1000>;
221                         clocks = <&ccu CLK_AHB_TVE>;
222                         resets = <&ccu RST_TVE>;
223                         status = "disabled";
224
225                         port {
226                                 #address-cells = <1>;
227                                 #size-cells = <0>;
228
229                                 tve0_in_tcon0: endpoint@0 {
230                                         reg = <0>;
231                                         remote-endpoint = <&tcon0_out_tve0>;
232                                 };
233                         };
234                 };
235
236                 emac: ethernet@1c0b000 {
237                         compatible = "allwinner,sun4i-a10-emac";
238                         reg = <0x01c0b000 0x1000>;
239                         interrupts = <55>;
240                         clocks = <&ccu CLK_AHB_EMAC>;
241                         allwinner,sram = <&emac_sram 1>;
242                         status = "disabled";
243                 };
244
245                 mdio: mdio@1c0b080 {
246                         compatible = "allwinner,sun4i-a10-mdio";
247                         reg = <0x01c0b080 0x14>;
248                         status = "disabled";
249                         #address-cells = <1>;
250                         #size-cells = <0>;
251                 };
252
253                 tcon0: lcd-controller@1c0c000 {
254                         compatible = "allwinner,sun5i-a13-tcon";
255                         reg = <0x01c0c000 0x1000>;
256                         interrupts = <44>;
257                         resets = <&ccu RST_LCD>;
258                         reset-names = "lcd";
259                         clocks = <&ccu CLK_AHB_LCD>,
260                                  <&ccu CLK_TCON_CH0>,
261                                  <&ccu CLK_TCON_CH1>;
262                         clock-names = "ahb",
263                                       "tcon-ch0",
264                                       "tcon-ch1";
265                         clock-output-names = "tcon-pixel-clock";
266                         status = "disabled";
267
268                         ports {
269                                 #address-cells = <1>;
270                                 #size-cells = <0>;
271
272                                 tcon0_in: port@0 {
273                                         #address-cells = <1>;
274                                         #size-cells = <0>;
275                                         reg = <0>;
276
277                                         tcon0_in_be0: endpoint@0 {
278                                                 reg = <0>;
279                                                 remote-endpoint = <&be0_out_tcon0>;
280                                         };
281                                 };
282
283                                 tcon0_out: port@1 {
284                                         #address-cells = <1>;
285                                         #size-cells = <0>;
286                                         reg = <1>;
287
288                                         tcon0_out_tve0: endpoint@1 {
289                                                 reg = <1>;
290                                                 remote-endpoint = <&tve0_in_tcon0>;
291                                                 allwinner,tcon-channel = <1>;
292                                         };
293                                 };
294                         };
295                 };
296
297                 mmc0: mmc@1c0f000 {
298                         compatible = "allwinner,sun5i-a13-mmc";
299                         reg = <0x01c0f000 0x1000>;
300                         clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
301                         clock-names = "ahb", "mmc";
302                         interrupts = <32>;
303                         status = "disabled";
304                         #address-cells = <1>;
305                         #size-cells = <0>;
306                 };
307
308                 mmc1: mmc@1c10000 {
309                         compatible = "allwinner,sun5i-a13-mmc";
310                         reg = <0x01c10000 0x1000>;
311                         clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
312                         clock-names = "ahb", "mmc";
313                         interrupts = <33>;
314                         status = "disabled";
315                         #address-cells = <1>;
316                         #size-cells = <0>;
317                 };
318
319                 mmc2: mmc@1c11000 {
320                         compatible = "allwinner,sun5i-a13-mmc";
321                         reg = <0x01c11000 0x1000>;
322                         clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
323                         clock-names = "ahb", "mmc";
324                         interrupts = <34>;
325                         status = "disabled";
326                         #address-cells = <1>;
327                         #size-cells = <0>;
328                 };
329
330                 usb_otg: usb@1c13000 {
331                         compatible = "allwinner,sun4i-a10-musb";
332                         reg = <0x01c13000 0x0400>;
333                         clocks = <&ccu CLK_AHB_OTG>;
334                         interrupts = <38>;
335                         interrupt-names = "mc";
336                         phys = <&usbphy 0>;
337                         phy-names = "usb";
338                         extcon = <&usbphy 0>;
339                         allwinner,sram = <&otg_sram 1>;
340                         status = "disabled";
341                 };
342
343                 usbphy: phy@1c13400 {
344                         #phy-cells = <1>;
345                         compatible = "allwinner,sun5i-a13-usb-phy";
346                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
347                         reg-names = "phy_ctrl", "pmu1";
348                         clocks = <&ccu CLK_USB_PHY0>;
349                         clock-names = "usb_phy";
350                         resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
351                         reset-names = "usb0_reset", "usb1_reset";
352                         status = "disabled";
353                 };
354
355                 ehci0: usb@1c14000 {
356                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
357                         reg = <0x01c14000 0x100>;
358                         interrupts = <39>;
359                         clocks = <&ccu CLK_AHB_EHCI>;
360                         phys = <&usbphy 1>;
361                         phy-names = "usb";
362                         status = "disabled";
363                 };
364
365                 ohci0: usb@1c14400 {
366                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
367                         reg = <0x01c14400 0x100>;
368                         interrupts = <40>;
369                         clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
370                         phys = <&usbphy 1>;
371                         phy-names = "usb";
372                         status = "disabled";
373                 };
374
375                 crypto: crypto-engine@1c15000 {
376                         compatible = "allwinner,sun5i-a13-crypto",
377                                      "allwinner,sun4i-a10-crypto";
378                         reg = <0x01c15000 0x1000>;
379                         interrupts = <54>;
380                         clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
381                         clock-names = "ahb", "mod";
382                 };
383
384                 spi2: spi@1c17000 {
385                         compatible = "allwinner,sun4i-a10-spi";
386                         reg = <0x01c17000 0x1000>;
387                         interrupts = <12>;
388                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
389                         clock-names = "ahb", "mod";
390                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
391                                <&dma SUN4I_DMA_DEDICATED 28>;
392                         dma-names = "rx", "tx";
393                         status = "disabled";
394                         #address-cells = <1>;
395                         #size-cells = <0>;
396                 };
397
398                 ccu: clock@1c20000 {
399                         reg = <0x01c20000 0x400>;
400                         clocks = <&osc24M>, <&osc32k>;
401                         clock-names = "hosc", "losc";
402                         #clock-cells = <1>;
403                         #reset-cells = <1>;
404                 };
405
406                 intc: interrupt-controller@1c20400 {
407                         compatible = "allwinner,sun4i-a10-ic";
408                         reg = <0x01c20400 0x400>;
409                         interrupt-controller;
410                         #interrupt-cells = <1>;
411                 };
412
413                 pio: pinctrl@1c20800 {
414                         reg = <0x01c20800 0x400>;
415                         interrupts = <28>;
416                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
417                         clock-names = "apb", "hosc", "losc";
418                         gpio-controller;
419                         interrupt-controller;
420                         #interrupt-cells = <3>;
421                         #gpio-cells = <3>;
422
423                         emac_pins_a: emac0@0 {
424                                 pins = "PD6", "PD7", "PD10",
425                                        "PD11", "PD12", "PD13", "PD14",
426                                        "PD15", "PD18", "PD19", "PD20",
427                                        "PD21", "PD22", "PD23", "PD24",
428                                        "PD25", "PD26", "PD27";
429                                 function = "emac";
430                         };
431
432                         i2c0_pins_a: i2c0@0 {
433                                 pins = "PB0", "PB1";
434                                 function = "i2c0";
435                         };
436
437                         i2c1_pins_a: i2c1@0 {
438                                 pins = "PB15", "PB16";
439                                 function = "i2c1";
440                         };
441
442                         i2c2_pins_a: i2c2@0 {
443                                 pins = "PB17", "PB18";
444                                 function = "i2c2";
445                         };
446
447                         ir0_rx_pins_a: ir0@0 {
448                                 pins = "PB4";
449                                 function = "ir0";
450                         };
451
452                         lcd_rgb565_pins: lcd_rgb565@0 {
453                                 pins = "PD3", "PD4", "PD5", "PD6", "PD7",
454                                                  "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
455                                                  "PD19", "PD20", "PD21", "PD22", "PD23",
456                                                  "PD24", "PD25", "PD26", "PD27";
457                                 function = "lcd0";
458                         };
459
460                         lcd_rgb666_pins: lcd_rgb666@0 {
461                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
462                                        "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
463                                        "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
464                                        "PD24", "PD25", "PD26", "PD27";
465                                 function = "lcd0";
466                         };
467
468                         mmc0_pins_a: mmc0@0 {
469                                 pins = "PF0", "PF1", "PF2", "PF3",
470                                        "PF4", "PF5";
471                                 function = "mmc0";
472                                 drive-strength = <30>;
473                                 bias-pull-up;
474                         };
475
476                         mmc2_pins_a: mmc2@0 {
477                                 pins = "PC6", "PC7", "PC8", "PC9",
478                                        "PC10", "PC11", "PC12", "PC13",
479                                        "PC14", "PC15";
480                                 function = "mmc2";
481                                 drive-strength = <30>;
482                                 bias-pull-up;
483                         };
484
485                         mmc2_4bit_pins_a: mmc2-4bit@0 {
486                                 pins = "PC6", "PC7", "PC8", "PC9",
487                                        "PC10", "PC11";
488                                 function = "mmc2";
489                                 drive-strength = <30>;
490                                 bias-pull-up;
491                         };
492
493                         nand_pins_a: nand-base0@0 {
494                                 pins = "PC0", "PC1", "PC2",
495                                        "PC5", "PC8", "PC9", "PC10",
496                                        "PC11", "PC12", "PC13", "PC14",
497                                        "PC15";
498                                 function = "nand0";
499                         };
500
501                         nand_cs0_pins_a: nand-cs@0 {
502                                 pins = "PC4";
503                                 function = "nand0";
504                         };
505
506                         nand_rb0_pins_a: nand-rb@0 {
507                                 pins = "PC6";
508                                 function = "nand0";
509                         };
510
511                         spi2_pins_a: spi2@0 {
512                                 pins = "PE1", "PE2", "PE3";
513                                 function = "spi2";
514                         };
515
516                         spi2_cs0_pins_a: spi2-cs0@0 {
517                                 pins = "PE0";
518                                 function = "spi2";
519                         };
520
521                         uart1_pins_a: uart1@0 {
522                                 pins = "PE10", "PE11";
523                                 function = "uart1";
524                         };
525
526                         uart1_pins_b: uart1@1 {
527                                 pins = "PG3", "PG4";
528                                 function = "uart1";
529                         };
530
531                         uart2_pins_a: uart2@0 {
532                                 pins = "PD2", "PD3";
533                                 function = "uart2";
534                         };
535
536                         uart2_cts_rts_pins_a: uart2-cts-rts@0 {
537                                 pins = "PD4", "PD5";
538                                 function = "uart2";
539                         };
540
541                         uart3_pins_a: uart3@0 {
542                                 pins = "PG9", "PG10";
543                                 function = "uart3";
544                         };
545
546                         uart3_cts_rts_pins_a: uart3-cts-rts@0 {
547                                 pins = "PG11", "PG12";
548                                 function = "uart3";
549                         };
550
551                         pwm0_pins: pwm0 {
552                                 pins = "PB2";
553                                 function = "pwm";
554                         };
555                 };
556
557                 timer@1c20c00 {
558                         compatible = "allwinner,sun4i-a10-timer";
559                         reg = <0x01c20c00 0x90>;
560                         interrupts = <22>;
561                         clocks = <&ccu CLK_HOSC>;
562                 };
563
564                 wdt: watchdog@1c20c90 {
565                         compatible = "allwinner,sun4i-a10-wdt";
566                         reg = <0x01c20c90 0x10>;
567                 };
568
569                 ir0: ir@1c21800 {
570                         compatible = "allwinner,sun4i-a10-ir";
571                         clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
572                         clock-names = "apb", "ir";
573                         interrupts = <5>;
574                         reg = <0x01c21800 0x40>;
575                         status = "disabled";
576                 };
577
578                 lradc: lradc@1c22800 {
579                         compatible = "allwinner,sun4i-a10-lradc-keys";
580                         reg = <0x01c22800 0x100>;
581                         interrupts = <31>;
582                         status = "disabled";
583                 };
584
585                 codec: codec@1c22c00 {
586                         #sound-dai-cells = <0>;
587                         compatible = "allwinner,sun4i-a10-codec";
588                         reg = <0x01c22c00 0x40>;
589                         interrupts = <30>;
590                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
591                         clock-names = "apb", "codec";
592                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
593                                <&dma SUN4I_DMA_NORMAL 19>;
594                         dma-names = "rx", "tx";
595                         status = "disabled";
596                 };
597
598                 sid: eeprom@1c23800 {
599                         compatible = "allwinner,sun4i-a10-sid";
600                         reg = <0x01c23800 0x10>;
601                 };
602
603                 rtp: rtp@1c25000 {
604                         compatible = "allwinner,sun5i-a13-ts";
605                         reg = <0x01c25000 0x100>;
606                         interrupts = <29>;
607                         #thermal-sensor-cells = <0>;
608                 };
609
610                 uart0: serial@1c28000 {
611                         compatible = "snps,dw-apb-uart";
612                         reg = <0x01c28000 0x400>;
613                         interrupts = <1>;
614                         reg-shift = <2>;
615                         reg-io-width = <4>;
616                         clocks = <&ccu CLK_APB1_UART0>;
617                         status = "disabled";
618                 };
619
620                 uart1: serial@1c28400 {
621                         compatible = "snps,dw-apb-uart";
622                         reg = <0x01c28400 0x400>;
623                         interrupts = <2>;
624                         reg-shift = <2>;
625                         reg-io-width = <4>;
626                         clocks = <&ccu CLK_APB1_UART1>;
627                         status = "disabled";
628                 };
629
630                 uart2: serial@1c28800 {
631                         compatible = "snps,dw-apb-uart";
632                         reg = <0x01c28800 0x400>;
633                         interrupts = <3>;
634                         reg-shift = <2>;
635                         reg-io-width = <4>;
636                         clocks = <&ccu CLK_APB1_UART2>;
637                         status = "disabled";
638                 };
639
640                 uart3: serial@1c28c00 {
641                         compatible = "snps,dw-apb-uart";
642                         reg = <0x01c28c00 0x400>;
643                         interrupts = <4>;
644                         reg-shift = <2>;
645                         reg-io-width = <4>;
646                         clocks = <&ccu CLK_APB1_UART3>;
647                         status = "disabled";
648                 };
649
650                 i2c0: i2c@1c2ac00 {
651                         compatible = "allwinner,sun4i-a10-i2c";
652                         reg = <0x01c2ac00 0x400>;
653                         interrupts = <7>;
654                         clocks = <&ccu CLK_APB1_I2C0>;
655                         status = "disabled";
656                         #address-cells = <1>;
657                         #size-cells = <0>;
658                 };
659
660                 i2c1: i2c@1c2b000 {
661                         compatible = "allwinner,sun4i-a10-i2c";
662                         reg = <0x01c2b000 0x400>;
663                         interrupts = <8>;
664                         clocks = <&ccu CLK_APB1_I2C1>;
665                         status = "disabled";
666                         #address-cells = <1>;
667                         #size-cells = <0>;
668                 };
669
670                 i2c2: i2c@1c2b400 {
671                         compatible = "allwinner,sun4i-a10-i2c";
672                         reg = <0x01c2b400 0x400>;
673                         interrupts = <9>;
674                         clocks = <&ccu CLK_APB1_I2C2>;
675                         status = "disabled";
676                         #address-cells = <1>;
677                         #size-cells = <0>;
678                 };
679
680                 timer@1c60000 {
681                         compatible = "allwinner,sun5i-a13-hstimer";
682                         reg = <0x01c60000 0x1000>;
683                         interrupts = <82>, <83>;
684                         clocks = <&ccu CLK_AHB_HSTIMER>;
685                 };
686
687                 fe0: display-frontend@1e00000 {
688                         compatible = "allwinner,sun5i-a13-display-frontend";
689                         reg = <0x01e00000 0x20000>;
690                         interrupts = <47>;
691                         clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
692                                  <&ccu CLK_DRAM_DE_FE>;
693                         clock-names = "ahb", "mod",
694                                       "ram";
695                         resets = <&ccu RST_DE_FE>;
696                         status = "disabled";
697
698                         ports {
699                                 #address-cells = <1>;
700                                 #size-cells = <0>;
701
702                                 fe0_out: port@1 {
703                                         #address-cells = <1>;
704                                         #size-cells = <0>;
705                                         reg = <1>;
706
707                                         fe0_out_be0: endpoint@0 {
708                                                 reg = <0>;
709                                                 remote-endpoint = <&be0_in_fe0>;
710                                         };
711                                 };
712                         };
713                 };
714
715                 be0: display-backend@1e60000 {
716                         compatible = "allwinner,sun5i-a13-display-backend";
717                         reg = <0x01e60000 0x10000>;
718                         interrupts = <47>;
719                         clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
720                                  <&ccu CLK_DRAM_DE_BE>;
721                         clock-names = "ahb", "mod",
722                                       "ram";
723                         resets = <&ccu RST_DE_BE>;
724                         status = "disabled";
725
726                         assigned-clocks = <&ccu CLK_DE_BE>;
727                         assigned-clock-rates = <300000000>;
728
729                         ports {
730                                 #address-cells = <1>;
731                                 #size-cells = <0>;
732
733                                 be0_in: port@0 {
734                                         #address-cells = <1>;
735                                         #size-cells = <0>;
736                                         reg = <0>;
737
738                                         be0_in_fe0: endpoint@0 {
739                                                 reg = <0>;
740                                                 remote-endpoint = <&fe0_out_be0>;
741                                         };
742                                 };
743
744                                 be0_out: port@1 {
745                                         #address-cells = <1>;
746                                         #size-cells = <0>;
747                                         reg = <1>;
748
749                                         be0_out_tcon0: endpoint@0 {
750                                                 reg = <0>;
751                                                 remote-endpoint = <&tcon0_in_be0>;
752                                         };
753                                 };
754                         };
755                 };
756         };
757 };