arch/arm/boot/dts/sun8i-a33.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "sun8i-a23-a33.dtsi"
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 / {
  49         cpu0_opp_table: opp_table0 {
  50                 compatible = "operating-points-v2";
  51                 opp-shared;
  52
  53                 opp-120000000 {
  54                         opp-hz = /bits/ 64 <120000000>;
  55                         opp-microvolt = <1040000>;
  56                         clock-latency-ns = <244144>; /* 8 32k periods */
  57                 };
  58
  59                 opp-240000000 {
  60                         opp-hz = /bits/ 64 <240000000>;
  61                         opp-microvolt = <1040000>;
  62                         clock-latency-ns = <244144>; /* 8 32k periods */
  63                 };
  64
  65                 opp-312000000 {
  66                         opp-hz = /bits/ 64 <312000000>;
  67                         opp-microvolt = <1040000>;
  68                         clock-latency-ns = <244144>; /* 8 32k periods */
  69                 };
  70
  71                 opp-408000000 {
  72                         opp-hz = /bits/ 64 <408000000>;
  73                         opp-microvolt = <1040000>;
  74                         clock-latency-ns = <244144>; /* 8 32k periods */
  75                 };
  76
  77                 opp-480000000 {
  78                         opp-hz = /bits/ 64 <480000000>;
  79                         opp-microvolt = <1040000>;
  80                         clock-latency-ns = <244144>; /* 8 32k periods */
  81                 };
  82
  83                 opp-504000000 {
  84                         opp-hz = /bits/ 64 <504000000>;
  85                         opp-microvolt = <1040000>;
  86                         clock-latency-ns = <244144>; /* 8 32k periods */
  87                 };
  88
  89                 opp-600000000 {
  90                         opp-hz = /bits/ 64 <600000000>;
  91                         opp-microvolt = <1040000>;
  92                         clock-latency-ns = <244144>; /* 8 32k periods */
  93                 };
  94
  95                 opp-648000000 {
  96                         opp-hz = /bits/ 64 <648000000>;
  97                         opp-microvolt = <1040000>;
  98                         clock-latency-ns = <244144>; /* 8 32k periods */
  99                 };
 100
 101                 opp-720000000 {
 102                         opp-hz = /bits/ 64 <720000000>;
 103                         opp-microvolt = <1100000>;
 104                         clock-latency-ns = <244144>; /* 8 32k periods */
 105                 };
 106
 107                 opp-816000000 {
 108                         opp-hz = /bits/ 64 <816000000>;
 109                         opp-microvolt = <1100000>;
 110                         clock-latency-ns = <244144>; /* 8 32k periods */
 111                 };
 112
 113                 opp-912000000 {
 114                         opp-hz = /bits/ 64 <912000000>;
 115                         opp-microvolt = <1200000>;
 116                         clock-latency-ns = <244144>; /* 8 32k periods */
 117                 };
 118
 119                 opp-1008000000 {
 120                         opp-hz = /bits/ 64 <1008000000>;
 121                         opp-microvolt = <1200000>;
 122                         clock-latency-ns = <244144>; /* 8 32k periods */
 123                 };
 124         };
 125
 126         cpus {
 127                 cpu@0 {
 128                         clocks = <&ccu CLK_CPUX>;
 129                         clock-names = "cpu";
 130                         operating-points-v2 = <&cpu0_opp_table>;
 131                         #cooling-cells = <2>;
 132                 };
 133
 134                 cpu@1 {
 135                         clocks = <&ccu CLK_CPUX>;
 136                         clock-names = "cpu";
 137                         operating-points-v2 = <&cpu0_opp_table>;
 138                         #cooling-cells = <2>;
 139                 };
 140
 141                 cpu@2 {
 142                         compatible = "arm,cortex-a7";
 143                         device_type = "cpu";
 144                         reg = <2>;
 145                         clocks = <&ccu CLK_CPUX>;
 146                         clock-names = "cpu";
 147                         operating-points-v2 = <&cpu0_opp_table>;
 148                         #cooling-cells = <2>;
 149                 };
 150
 151                 cpu@3 {
 152                         compatible = "arm,cortex-a7";
 153                         device_type = "cpu";
 154                         reg = <3>;
 155                         clocks = <&ccu CLK_CPUX>;
 156                         clock-names = "cpu";
 157                         operating-points-v2 = <&cpu0_opp_table>;
 158                         #cooling-cells = <2>;
 159                 };
 160         };
 161
 162         de: display-engine {
 163                 compatible = "allwinner,sun8i-a33-display-engine";
 164                 allwinner,pipelines = <&fe0>;
 165                 status = "disabled";
 166         };
 167
 168         iio-hwmon {
 169                 compatible = "iio-hwmon";
 170                 io-channels = <&ths>;
 171         };
 172
 173         mali_opp_table: gpu-opp-table {
 174                 compatible = "operating-points-v2";
 175
 176                 opp-144000000 {
 177                         opp-hz = /bits/ 64 <144000000>;
 178                 };
 179
 180                 opp-240000000 {
 181                         opp-hz = /bits/ 64 <240000000>;
 182                 };
 183
 184                 opp-384000000 {
 185                         opp-hz = /bits/ 64 <384000000>;
 186                 };
 187         };
 188
 189         memory {
 190                 reg = <0x40000000 0x80000000>;
 191         };
 192
 193         sound: sound {
 194                 compatible = "simple-audio-card";
 195                 simple-audio-card,name = "sun8i-a33-audio";
 196                 simple-audio-card,format = "i2s";
 197                 simple-audio-card,frame-master = <&link_codec>;
 198                 simple-audio-card,bitclock-master = <&link_codec>;
 199                 simple-audio-card,mclk-fs = <512>;
 200                 simple-audio-card,aux-devs = <&codec_analog>;
 201                 simple-audio-card,routing =
 202                         "Left DAC", "AIF1 Slot 0 Left",
 203                         "Right DAC", "AIF1 Slot 0 Right";
 204                 status = "disabled";
 205
 206                 simple-audio-card,cpu {
 207                         sound-dai = <&dai>;
 208                 };
 209
 210                 link_codec: simple-audio-card,codec {
 211                         sound-dai = <&codec>;
 212                 };
 213         };
 214
 215         soc@1c00000 {
 216                 tcon0: lcd-controller@1c0c000 {
 217                         compatible = "allwinner,sun8i-a33-tcon";
 218                         reg = <0x01c0c000 0x1000>;
 219                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 220                         clocks = <&ccu CLK_BUS_LCD>,
 221                                  <&ccu CLK_LCD_CH0>;
 222                         clock-names = "ahb",
 223                                       "tcon-ch0";
 224                         clock-output-names = "tcon-pixel-clock";
 225                         resets = <&ccu RST_BUS_LCD>;
 226                         reset-names = "lcd";
 227                         status = "disabled";
 228
 229                         ports {
 230                                 #address-cells = <1>;
 231                                 #size-cells = <0>;
 232
 233                                 tcon0_in: port@0 {
 234                                         #address-cells = <1>;
 235                                         #size-cells = <0>;
 236                                         reg = <0>;
 237
 238                                         tcon0_in_drc0: endpoint@0 {
 239                                                 reg = <0>;
 240                                                 remote-endpoint = <&drc0_out_tcon0>;
 241                                         };
 242                                 };
 243
 244                                 tcon0_out: port@1 {
 245                                         #address-cells = <1>;
 246                                         #size-cells = <0>;
 247                                         reg = <1>;
 248
 249                                         tcon0_out_dsi: endpoint@1 {
 250                                                 reg = <1>;
 251                                                 remote-endpoint = <&dsi_in_tcon0>;
 252                                         };
 253                                 };
 254                         };
 255                 };
 256
 257                 crypto: crypto-engine@1c15000 {
 258                         compatible = "allwinner,sun4i-a10-crypto";
 259                         reg = <0x01c15000 0x1000>;
 260                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 261                         clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
 262                         clock-names = "ahb", "mod";
 263                         resets = <&ccu RST_BUS_SS>;
 264                         reset-names = "ahb";
 265                 };
 266
 267                 dai: dai@1c22c00 {
 268                         #sound-dai-cells = <0>;
 269                         compatible = "allwinner,sun6i-a31-i2s";
 270                         reg = <0x01c22c00 0x200>;
 271                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 272                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 273                         clock-names = "apb", "mod";
 274                         resets = <&ccu RST_BUS_CODEC>;
 275                         dmas = <&dma 15>, <&dma 15>;
 276                         dma-names = "rx", "tx";
 277                         status = "disabled";
 278                 };
 279
 280                 codec: codec@1c22e00 {
 281                         #sound-dai-cells = <0>;
 282                         compatible = "allwinner,sun8i-a33-codec";
 283                         reg = <0x01c22e00 0x400>;
 284                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 285                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 286                         clock-names = "bus", "mod";
 287                         status = "disabled";
 288                 };
 289
 290                 ths: ths@1c25000 {
 291                         compatible = "allwinner,sun8i-a33-ths";
 292                         reg = <0x01c25000 0x100>;
 293                         #thermal-sensor-cells = <0>;
 294                         #io-channel-cells = <0>;
 295                 };
 296
 297                 dsi: dsi@1ca0000 {
 298                         compatible = "allwinner,sun6i-a31-mipi-dsi";
 299                         reg = <0x01ca0000 0x1000>;
 300                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 301                         clocks = <&ccu CLK_BUS_MIPI_DSI>,
 302                                  <&ccu CLK_DSI_SCLK>;
 303                         clock-names = "bus", "mod";
 304                         resets = <&ccu RST_BUS_MIPI_DSI>;
 305                         phys = <&dphy>;
 306                         phy-names = "dphy";
 307                         status = "disabled";
 308
 309                         ports {
 310                                 #address-cells = <1>;
 311                                 #size-cells = <0>;
 312
 313                                 port@0 {
 314                                         #address-cells = <1>;
 315                                         #size-cells = <0>;
 316                                         reg = <0>;
 317
 318                                         dsi_in_tcon0: endpoint {
 319                                                 remote-endpoint = <&tcon0_out_dsi>;
 320                                         };
 321                                 };
 322                         };
 323                 };
 324
 325                 dphy: d-phy@1ca1000 {
 326                         compatible = "allwinner,sun6i-a31-mipi-dphy";
 327                         reg = <0x01ca1000 0x1000>;
 328                         clocks = <&ccu CLK_BUS_MIPI_DSI>,
 329                                  <&ccu CLK_DSI_DPHY>;
 330                         clock-names = "bus", "mod";
 331                         resets = <&ccu RST_BUS_MIPI_DSI>;
 332                         status = "disabled";
 333                         #phy-cells = <0>;
 334                 };
 335
 336                 fe0: display-frontend@1e00000 {
 337                         compatible = "allwinner,sun8i-a33-display-frontend";
 338                         reg = <0x01e00000 0x20000>;
 339                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 340                         clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
 341                                  <&ccu CLK_DRAM_DE_FE>;
 342                         clock-names = "ahb", "mod",
 343                                       "ram";
 344                         resets = <&ccu RST_BUS_DE_FE>;
 345
 346                         ports {
 347                                 #address-cells = <1>;
 348                                 #size-cells = <0>;
 349
 350                                 fe0_out: port@1 {
 351                                         #address-cells = <1>;
 352                                         #size-cells = <0>;
 353                                         reg = <1>;
 354
 355                                         fe0_out_be0: endpoint@0 {
 356                                                 reg = <0>;
 357                                                 remote-endpoint = <&be0_in_fe0>;
 358                                         };
 359                                 };
 360                         };
 361                 };
 362
 363                 be0: display-backend@1e60000 {
 364                         compatible = "allwinner,sun8i-a33-display-backend";
 365                         reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
 366                         reg-names = "be", "sat";
 367                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 368                         clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
 369                                  <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
 370                         clock-names = "ahb", "mod",
 371                                       "ram", "sat";
 372                         resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
 373                         reset-names = "be", "sat";
 374                         assigned-clocks = <&ccu CLK_DE_BE>;
 375                         assigned-clock-rates = <300000000>;
 376
 377                         ports {
 378                                 #address-cells = <1>;
 379                                 #size-cells = <0>;
 380
 381                                 be0_in: port@0 {
 382                                         #address-cells = <1>;
 383                                         #size-cells = <0>;
 384                                         reg = <0>;
 385
 386                                         be0_in_fe0: endpoint@0 {
 387                                                 reg = <0>;
 388                                                 remote-endpoint = <&fe0_out_be0>;
 389                                         };
 390                                 };
 391
 392                                 be0_out: port@1 {
 393                                         #address-cells = <1>;
 394                                         #size-cells = <0>;
 395                                         reg = <1>;
 396
 397                                         be0_out_drc0: endpoint@0 {
 398                                                 reg = <0>;
 399                                                 remote-endpoint = <&drc0_in_be0>;
 400                                         };
 401                                 };
 402                         };
 403                 };
 404
 405                 drc0: drc@1e70000 {
 406                         compatible = "allwinner,sun8i-a33-drc";
 407                         reg = <0x01e70000 0x10000>;
 408                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 409                         clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
 410                                  <&ccu CLK_DRAM_DRC>;
 411                         clock-names = "ahb", "mod", "ram";
 412                         resets = <&ccu RST_BUS_DRC>;
 413
 414                         assigned-clocks = <&ccu CLK_DRC>;
 415                         assigned-clock-rates = <300000000>;
 416
 417                         ports {
 418                                 #address-cells = <1>;
 419                                 #size-cells = <0>;
 420
 421                                 drc0_in: port@0 {
 422                                         #address-cells = <1>;
 423                                         #size-cells = <0>;
 424                                         reg = <0>;
 425
 426                                         drc0_in_be0: endpoint@0 {
 427                                                 reg = <0>;
 428                                                 remote-endpoint = <&be0_out_drc0>;
 429                                         };
 430                                 };
 431
 432                                 drc0_out: port@1 {
 433                                         #address-cells = <1>;
 434                                         #size-cells = <0>;
 435                                         reg = <1>;
 436
 437                                         drc0_out_tcon0: endpoint@0 {
 438                                                 reg = <0>;
 439                                                 remote-endpoint = <&tcon0_in_drc0>;
 440                                         };
 441                                 };
 442                         };
 443                 };
 444         };
 445
 446         thermal-zones {
 447                 cpu_thermal {
 448                         /* milliseconds */
 449                         polling-delay-passive = <250>;
 450                         polling-delay = <1000>;
 451                         thermal-sensors = <&ths>;
 452
 453                         cooling-maps {
 454                                 map0 {
 455                                         trip = <&cpu_alert0>;
 456                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 457                                 };
 458                                 map1 {
 459                                         trip = <&cpu_alert1>;
 460                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 461                                 };
 462
 463                                 map2 {
 464                                         trip = <&gpu_alert0>;
 465                                         cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
 466                                 };
 467
 468                                 map3 {
 469                                         trip = <&gpu_alert1>;
 470                                         cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
 471                                 };
 472                         };
 473
 474                         trips {
 475                                 cpu_alert0: cpu_alert0 {
 476                                         /* milliCelsius */
 477                                         temperature = <75000>;
 478                                         hysteresis = <2000>;
 479                                         type = "passive";
 480                                 };
 481
 482                                 gpu_alert0: gpu_alert0 {
 483                                         /* milliCelsius */
 484                                         temperature = <85000>;
 485                                         hysteresis = <2000>;
 486                                         type = "passive";
 487                                 };
 488
 489                                 cpu_alert1: cpu_alert1 {
 490                                         /* milliCelsius */
 491                                         temperature = <90000>;
 492                                         hysteresis = <2000>;
 493                                         type = "hot";
 494                                 };
 495
 496                                 gpu_alert1: gpu_alert1 {
 497                                         /* milliCelsius */
 498                                         temperature = <95000>;
 499                                         hysteresis = <2000>;
 500                                         type = "hot";
 501                                 };
 502
 503                                 cpu_crit: cpu_crit {
 504                                         /* milliCelsius */
 505                                         temperature = <110000>;
 506                                         hysteresis = <2000>;
 507                                         type = "critical";
 508                                 };
 509                         };
 510                 };
 511         };
 512 };
 513
 514 &ccu {
 515         compatible = "allwinner,sun8i-a33-ccu";
 516 };
 517
 518 &mali {
 519         operating-points-v2 = <&mali_opp_table>;
 520 };
 521
 522 &pio {
 523         compatible = "allwinner,sun8i-a33-pinctrl";
 524         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 525                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 526
 527         uart0_pins_b: uart0@1 {
 528                 pins = "PB0", "PB1";
 529                 function = "uart0";
 530         };
 531
 532 };
 533
 534 &usb_otg {
 535         compatible = "allwinner,sun8i-a33-musb";
 536 };
 537
 538 &usbphy {
 539         compatible = "allwinner,sun8i-a33-usb-phy";
 540         reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
 541         reg-names = "phy_ctrl", "pmu1";
 542 };