GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / uniphier-pro4.dtsi
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Device Tree Source for UniPhier Pro4 SoC
4 //
5 // Copyright (C) 2015-2016 Socionext Inc.
6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9
10 / {
11         compatible = "socionext,uniphier-pro4";
12         #address-cells = <1>;
13         #size-cells = <1>;
14
15         cpus {
16                 #address-cells = <1>;
17                 #size-cells = <0>;
18
19                 cpu@0 {
20                         device_type = "cpu";
21                         compatible = "arm,cortex-a9";
22                         reg = <0>;
23                         enable-method = "psci";
24                         next-level-cache = <&l2>;
25                 };
26
27                 cpu@1 {
28                         device_type = "cpu";
29                         compatible = "arm,cortex-a9";
30                         reg = <1>;
31                         enable-method = "psci";
32                         next-level-cache = <&l2>;
33                 };
34         };
35
36         psci {
37                 compatible = "arm,psci-0.2";
38                 method = "smc";
39         };
40
41         clocks {
42                 refclk: ref {
43                         compatible = "fixed-clock";
44                         #clock-cells = <0>;
45                         clock-frequency = <25000000>;
46                 };
47
48                 arm_timer_clk: arm-timer {
49                         #clock-cells = <0>;
50                         compatible = "fixed-clock";
51                         clock-frequency = <50000000>;
52                 };
53         };
54
55         soc {
56                 compatible = "simple-bus";
57                 #address-cells = <1>;
58                 #size-cells = <1>;
59                 ranges;
60                 interrupt-parent = <&intc>;
61
62                 l2: l2-cache@500c0000 {
63                         compatible = "socionext,uniphier-system-cache";
64                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65                               <0x506c0000 0x400>;
66                         interrupts = <0 174 4>, <0 175 4>;
67                         cache-unified;
68                         cache-size = <(768 * 1024)>;
69                         cache-sets = <256>;
70                         cache-line-size = <128>;
71                         cache-level = <2>;
72                 };
73
74                 serial0: serial@54006800 {
75                         compatible = "socionext,uniphier-uart";
76                         status = "disabled";
77                         reg = <0x54006800 0x40>;
78                         interrupts = <0 33 4>;
79                         pinctrl-names = "default";
80                         pinctrl-0 = <&pinctrl_uart0>;
81                         clocks = <&peri_clk 0>;
82                         resets = <&peri_rst 0>;
83                 };
84
85                 serial1: serial@54006900 {
86                         compatible = "socionext,uniphier-uart";
87                         status = "disabled";
88                         reg = <0x54006900 0x40>;
89                         interrupts = <0 35 4>;
90                         pinctrl-names = "default";
91                         pinctrl-0 = <&pinctrl_uart1>;
92                         clocks = <&peri_clk 1>;
93                         resets = <&peri_rst 1>;
94                 };
95
96                 serial2: serial@54006a00 {
97                         compatible = "socionext,uniphier-uart";
98                         status = "disabled";
99                         reg = <0x54006a00 0x40>;
100                         interrupts = <0 37 4>;
101                         pinctrl-names = "default";
102                         pinctrl-0 = <&pinctrl_uart2>;
103                         clocks = <&peri_clk 2>;
104                         resets = <&peri_rst 2>;
105                 };
106
107                 serial3: serial@54006b00 {
108                         compatible = "socionext,uniphier-uart";
109                         status = "disabled";
110                         reg = <0x54006b00 0x40>;
111                         interrupts = <0 177 4>;
112                         pinctrl-names = "default";
113                         pinctrl-0 = <&pinctrl_uart3>;
114                         clocks = <&peri_clk 3>;
115                         resets = <&peri_rst 3>;
116                 };
117
118                 gpio: gpio@55000000 {
119                         compatible = "socionext,uniphier-gpio";
120                         reg = <0x55000000 0x200>;
121                         interrupt-parent = <&aidet>;
122                         interrupt-controller;
123                         #interrupt-cells = <2>;
124                         gpio-controller;
125                         #gpio-cells = <2>;
126                         gpio-ranges = <&pinctrl 0 0 0>;
127                         gpio-ranges-group-names = "gpio_range";
128                         ngpios = <248>;
129                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
130                 };
131
132                 i2c0: i2c@58780000 {
133                         compatible = "socionext,uniphier-fi2c";
134                         status = "disabled";
135                         reg = <0x58780000 0x80>;
136                         #address-cells = <1>;
137                         #size-cells = <0>;
138                         interrupts = <0 41 4>;
139                         pinctrl-names = "default";
140                         pinctrl-0 = <&pinctrl_i2c0>;
141                         clocks = <&peri_clk 4>;
142                         resets = <&peri_rst 4>;
143                         clock-frequency = <100000>;
144                 };
145
146                 i2c1: i2c@58781000 {
147                         compatible = "socionext,uniphier-fi2c";
148                         status = "disabled";
149                         reg = <0x58781000 0x80>;
150                         #address-cells = <1>;
151                         #size-cells = <0>;
152                         interrupts = <0 42 4>;
153                         pinctrl-names = "default";
154                         pinctrl-0 = <&pinctrl_i2c1>;
155                         clocks = <&peri_clk 5>;
156                         resets = <&peri_rst 5>;
157                         clock-frequency = <100000>;
158                 };
159
160                 i2c2: i2c@58782000 {
161                         compatible = "socionext,uniphier-fi2c";
162                         status = "disabled";
163                         reg = <0x58782000 0x80>;
164                         #address-cells = <1>;
165                         #size-cells = <0>;
166                         interrupts = <0 43 4>;
167                         pinctrl-names = "default";
168                         pinctrl-0 = <&pinctrl_i2c2>;
169                         clocks = <&peri_clk 6>;
170                         resets = <&peri_rst 6>;
171                         clock-frequency = <100000>;
172                 };
173
174                 i2c3: i2c@58783000 {
175                         compatible = "socionext,uniphier-fi2c";
176                         status = "disabled";
177                         reg = <0x58783000 0x80>;
178                         #address-cells = <1>;
179                         #size-cells = <0>;
180                         interrupts = <0 44 4>;
181                         pinctrl-names = "default";
182                         pinctrl-0 = <&pinctrl_i2c3>;
183                         clocks = <&peri_clk 7>;
184                         resets = <&peri_rst 7>;
185                         clock-frequency = <100000>;
186                 };
187
188                 /* i2c4 does not exist */
189
190                 /* chip-internal connection for DMD */
191                 i2c5: i2c@58785000 {
192                         compatible = "socionext,uniphier-fi2c";
193                         reg = <0x58785000 0x80>;
194                         #address-cells = <1>;
195                         #size-cells = <0>;
196                         interrupts = <0 25 4>;
197                         clocks = <&peri_clk 9>;
198                         resets = <&peri_rst 9>;
199                         clock-frequency = <400000>;
200                 };
201
202                 /* chip-internal connection for HDMI */
203                 i2c6: i2c@58786000 {
204                         compatible = "socionext,uniphier-fi2c";
205                         reg = <0x58786000 0x80>;
206                         #address-cells = <1>;
207                         #size-cells = <0>;
208                         interrupts = <0 26 4>;
209                         clocks = <&peri_clk 10>;
210                         resets = <&peri_rst 10>;
211                         clock-frequency = <400000>;
212                 };
213
214                 system_bus: system-bus@58c00000 {
215                         compatible = "socionext,uniphier-system-bus";
216                         status = "disabled";
217                         reg = <0x58c00000 0x400>;
218                         #address-cells = <2>;
219                         #size-cells = <1>;
220                         pinctrl-names = "default";
221                         pinctrl-0 = <&pinctrl_system_bus>;
222                 };
223
224                 smpctrl@59801000 {
225                         compatible = "socionext,uniphier-smpctrl";
226                         reg = <0x59801000 0x400>;
227                 };
228
229                 mioctrl@59810000 {
230                         compatible = "socionext,uniphier-pro4-mioctrl",
231                                      "simple-mfd", "syscon";
232                         reg = <0x59810000 0x800>;
233
234                         mio_clk: clock {
235                                 compatible = "socionext,uniphier-pro4-mio-clock";
236                                 #clock-cells = <1>;
237                         };
238
239                         mio_rst: reset {
240                                 compatible = "socionext,uniphier-pro4-mio-reset";
241                                 #reset-cells = <1>;
242                         };
243                 };
244
245                 perictrl@59820000 {
246                         compatible = "socionext,uniphier-pro4-perictrl",
247                                      "simple-mfd", "syscon";
248                         reg = <0x59820000 0x200>;
249
250                         peri_clk: clock {
251                                 compatible = "socionext,uniphier-pro4-peri-clock";
252                                 #clock-cells = <1>;
253                         };
254
255                         peri_rst: reset {
256                                 compatible = "socionext,uniphier-pro4-peri-reset";
257                                 #reset-cells = <1>;
258                         };
259                 };
260
261                 usb2: usb@5a800100 {
262                         compatible = "socionext,uniphier-ehci", "generic-ehci";
263                         status = "disabled";
264                         reg = <0x5a800100 0x100>;
265                         interrupts = <0 80 4>;
266                         pinctrl-names = "default";
267                         pinctrl-0 = <&pinctrl_usb2>;
268                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
269                                  <&mio_clk 12>;
270                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
271                                  <&mio_rst 12>;
272                         has-transaction-translator;
273                 };
274
275                 usb3: usb@5a810100 {
276                         compatible = "socionext,uniphier-ehci", "generic-ehci";
277                         status = "disabled";
278                         reg = <0x5a810100 0x100>;
279                         interrupts = <0 81 4>;
280                         pinctrl-names = "default";
281                         pinctrl-0 = <&pinctrl_usb3>;
282                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
283                                  <&mio_clk 13>;
284                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
285                                  <&mio_rst 13>;
286                         has-transaction-translator;
287                 };
288
289                 soc_glue: soc-glue@5f800000 {
290                         compatible = "socionext,uniphier-pro4-soc-glue",
291                                      "simple-mfd", "syscon";
292                         reg = <0x5f800000 0x2000>;
293
294                         pinctrl: pinctrl {
295                                 compatible = "socionext,uniphier-pro4-pinctrl";
296                         };
297                 };
298
299                 soc-glue@5f900000 {
300                         compatible = "socionext,uniphier-pro4-soc-glue-debug",
301                                      "simple-mfd";
302                         #address-cells = <1>;
303                         #size-cells = <1>;
304                         ranges = <0 0x5f900000 0x2000>;
305
306                         efuse@100 {
307                                 compatible = "socionext,uniphier-efuse";
308                                 reg = <0x100 0x28>;
309                         };
310
311                         efuse@130 {
312                                 compatible = "socionext,uniphier-efuse";
313                                 reg = <0x130 0x8>;
314                         };
315
316                         efuse@200 {
317                                 compatible = "socionext,uniphier-efuse";
318                                 reg = <0x200 0x14>;
319                         };
320                 };
321
322                 aidet: aidet@5fc20000 {
323                         compatible = "socionext,uniphier-pro4-aidet";
324                         reg = <0x5fc20000 0x200>;
325                         interrupt-controller;
326                         #interrupt-cells = <2>;
327                 };
328
329                 timer@60000200 {
330                         compatible = "arm,cortex-a9-global-timer";
331                         reg = <0x60000200 0x20>;
332                         interrupts = <1 11 0x304>;
333                         clocks = <&arm_timer_clk>;
334                 };
335
336                 timer@60000600 {
337                         compatible = "arm,cortex-a9-twd-timer";
338                         reg = <0x60000600 0x20>;
339                         interrupts = <1 13 0x304>;
340                         clocks = <&arm_timer_clk>;
341                 };
342
343                 intc: interrupt-controller@60001000 {
344                         compatible = "arm,cortex-a9-gic";
345                         reg = <0x60001000 0x1000>,
346                               <0x60000100 0x100>;
347                         #interrupt-cells = <3>;
348                         interrupt-controller;
349                 };
350
351                 sysctrl@61840000 {
352                         compatible = "socionext,uniphier-pro4-sysctrl",
353                                      "simple-mfd", "syscon";
354                         reg = <0x61840000 0x10000>;
355
356                         sys_clk: clock {
357                                 compatible = "socionext,uniphier-pro4-clock";
358                                 #clock-cells = <1>;
359                         };
360
361                         sys_rst: reset {
362                                 compatible = "socionext,uniphier-pro4-reset";
363                                 #reset-cells = <1>;
364                         };
365                 };
366
367                 eth: ethernet@65000000 {
368                         compatible = "socionext,uniphier-pro4-ave4";
369                         status = "disabled";
370                         reg = <0x65000000 0x8500>;
371                         interrupts = <0 66 4>;
372                         pinctrl-names = "default";
373                         pinctrl-0 = <&pinctrl_ether_rgmii>;
374                         clock-names = "gio", "ether", "ether-gb", "ether-phy";
375                         clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
376                                  <&sys_clk 10>;
377                         reset-names = "gio", "ether";
378                         resets = <&sys_rst 12>, <&sys_rst 6>;
379                         phy-mode = "rgmii";
380                         local-mac-address = [00 00 00 00 00 00];
381                         socionext,syscon-phy-mode = <&soc_glue 0>;
382
383                         mdio: mdio {
384                                 #address-cells = <1>;
385                                 #size-cells = <0>;
386                         };
387                 };
388
389                 nand: nand@68000000 {
390                         compatible = "socionext,uniphier-denali-nand-v5a";
391                         status = "disabled";
392                         reg-names = "nand_data", "denali_reg";
393                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
394                         interrupts = <0 65 4>;
395                         pinctrl-names = "default";
396                         pinctrl-0 = <&pinctrl_nand>;
397                         clocks = <&sys_clk 2>;
398                         resets = <&sys_rst 2>;
399                 };
400         };
401 };
402
403 #include "uniphier-pinctrl.dtsi"