arch/arm/boot/dts/versatile-ab.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3 /include/ "skeleton.dtsi"
   4
   5 / {
   6         model = "ARM Versatile AB";
   7         compatible = "arm,versatile-ab";
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10         interrupt-parent = <&vic>;
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15                 serial2 = &uart2;
  16                 i2c0 = &i2c0;
  17         };
  18
  19         chosen {
  20                 stdout-path = &uart0;
  21         };
  22
  23         memory {
  24                 reg = <0x0 0x08000000>;
  25         };
  26
  27         xtal24mhz: xtal24mhz@24M {
  28                 #clock-cells = <0>;
  29                 compatible = "fixed-clock";
  30                 clock-frequency = <24000000>;
  31         };
  32
  33         bridge {
  34                 compatible = "ti,ths8134b", "ti,ths8134";
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 ports {
  39                         #address-cells = <1>;
  40                         #size-cells = <0>;
  41
  42                         port@0 {
  43                                 reg = <0>;
  44
  45                                 vga_bridge_in: endpoint {
  46                                         remote-endpoint = <&clcd_pads_vga_dac>;
  47                                 };
  48                         };
  49
  50                         port@1 {
  51                                 reg = <1>;
  52
  53                                 vga_bridge_out: endpoint {
  54                                         remote-endpoint = <&vga_con_in>;
  55                                 };
  56                         };
  57                 };
  58         };
  59
  60         vga {
  61                 compatible = "vga-connector";
  62
  63                 port {
  64                         vga_con_in: endpoint {
  65                                 remote-endpoint = <&vga_bridge_out>;
  66                         };
  67                 };
  68         };
  69
  70         core-module@10000000 {
  71                 compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
  72                 reg = <0x10000000 0x200>;
  73
  74                 led@08.0 {
  75                         compatible = "register-bit-led";
  76                         offset = <0x08>;
  77                         mask = <0x01>;
  78                         label = "versatile:0";
  79                         linux,default-trigger = "heartbeat";
  80                         default-state = "on";
  81                 };
  82                 led@08.1 {
  83                         compatible = "register-bit-led";
  84                         offset = <0x08>;
  85                         mask = <0x02>;
  86                         label = "versatile:1";
  87                         linux,default-trigger = "mmc0";
  88                         default-state = "off";
  89                 };
  90                 led@08.2 {
  91                         compatible = "register-bit-led";
  92                         offset = <0x08>;
  93                         mask = <0x04>;
  94                         label = "versatile:2";
  95                         linux,default-trigger = "cpu0";
  96                         default-state = "off";
  97                 };
  98                 led@08.3 {
  99                         compatible = "register-bit-led";
 100                         offset = <0x08>;
 101                         mask = <0x08>;
 102                         label = "versatile:3";
 103                         default-state = "off";
 104                 };
 105                 led@08.4 {
 106                         compatible = "register-bit-led";
 107                         offset = <0x08>;
 108                         mask = <0x10>;
 109                         label = "versatile:4";
 110                         default-state = "off";
 111                 };
 112                 led@08.5 {
 113                         compatible = "register-bit-led";
 114                         offset = <0x08>;
 115                         mask = <0x20>;
 116                         label = "versatile:5";
 117                         default-state = "off";
 118                 };
 119                 led@08.6 {
 120                         compatible = "register-bit-led";
 121                         offset = <0x08>;
 122                         mask = <0x40>;
 123                         label = "versatile:6";
 124                         default-state = "off";
 125                 };
 126                 led@08.7 {
 127                         compatible = "register-bit-led";
 128                         offset = <0x08>;
 129                         mask = <0x80>;
 130                         label = "versatile:7";
 131                         default-state = "off";
 132                 };
 133
 134                 /* OSC1 on AB, OSC4 on PB */
 135                 osc1: cm_aux_osc@24M {
 136                         #clock-cells = <0>;
 137                         compatible = "arm,versatile-cm-auxosc";
 138                         clocks = <&xtal24mhz>;
 139                 };
 140
 141                 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
 142                 timclk: timclk@1M {
 143                         #clock-cells = <0>;
 144                         compatible = "fixed-factor-clock";
 145                         clock-div = <24>;
 146                         clock-mult = <1>;
 147                         clocks = <&xtal24mhz>;
 148                 };
 149
 150                 pclk: pclk@24M {
 151                         #clock-cells = <0>;
 152                         compatible = "fixed-factor-clock";
 153                         clock-div = <1>;
 154                         clock-mult = <1>;
 155                         clocks = <&xtal24mhz>;
 156                 };
 157         };
 158
 159         flash@34000000 {
 160                 /* 64 MiB NOR flash in non-interleaved chips */
 161                 compatible = "arm,versatile-flash", "cfi-flash";
 162                 reg = <0x34000000 0x04000000>;
 163                 bank-width = <4>;
 164         };
 165
 166         i2c0: i2c@10002000 {
 167                 #address-cells = <1>;
 168                 #size-cells = <0>;
 169                 compatible = "arm,versatile-i2c";
 170                 reg = <0x10002000 0x1000>;
 171
 172                 rtc@68 {
 173                         compatible = "dallas,ds1338";
 174                         reg = <0x68>;
 175                 };
 176         };
 177
 178         net@10010000 {
 179                 compatible = "smsc,lan91c111";
 180                 reg = <0x10010000 0x10000>;
 181                 interrupts = <25>;
 182         };
 183
 184         lcd@10008000 {
 185                 compatible = "arm,versatile-lcd";
 186                 reg = <0x10008000 0x1000>;
 187         };
 188
 189         amba {
 190                 compatible = "simple-bus";
 191                 #address-cells = <1>;
 192                 #size-cells = <1>;
 193                 ranges;
 194
 195                 vic: interrupt-controller@10140000 {
 196                         compatible = "arm,versatile-vic";
 197                         interrupt-controller;
 198                         #interrupt-cells = <1>;
 199                         reg = <0x10140000 0x1000>;
 200                         valid-mask = <0xffffffff>;
 201                 };
 202
 203                 sic: interrupt-controller@10003000 {
 204                         compatible = "arm,versatile-sic";
 205                         interrupt-controller;
 206                         #interrupt-cells = <1>;
 207                         reg = <0x10003000 0x1000>;
 208                         interrupt-parent = <&vic>;
 209                         interrupts = <31>; /* Cascaded to vic */
 210                         clear-mask = <0xffffffff>;
 211                         /*
 212                          * Valid interrupt lines mask according to
 213                          * table 4-36 page 4-50 of ARM DUI 0225D
 214                          */
 215                         valid-mask = <0x0760031b>;
 216                 };
 217
 218                 dma@10130000 {
 219                         compatible = "arm,pl081", "arm,primecell";
 220                         reg = <0x10130000 0x1000>;
 221                         interrupts = <17>;
 222                         clocks = <&pclk>;
 223                         clock-names = "apb_pclk";
 224                 };
 225
 226                 uart0: uart@101f1000 {
 227                         compatible = "arm,pl011", "arm,primecell";
 228                         reg = <0x101f1000 0x1000>;
 229                         interrupts = <12>;
 230                         clocks = <&xtal24mhz>, <&pclk>;
 231                         clock-names = "uartclk", "apb_pclk";
 232                 };
 233
 234                 uart1: uart@101f2000 {
 235                         compatible = "arm,pl011", "arm,primecell";
 236                         reg = <0x101f2000 0x1000>;
 237                         interrupts = <13>;
 238                         clocks = <&xtal24mhz>, <&pclk>;
 239                         clock-names = "uartclk", "apb_pclk";
 240                 };
 241
 242                 uart2: uart@101f3000 {
 243                         compatible = "arm,pl011", "arm,primecell";
 244                         reg = <0x101f3000 0x1000>;
 245                         interrupts = <14>;
 246                         clocks = <&xtal24mhz>, <&pclk>;
 247                         clock-names = "uartclk", "apb_pclk";
 248                 };
 249
 250                 smc@10100000 {
 251                         compatible = "arm,primecell";
 252                         reg = <0x10100000 0x1000>;
 253                         clocks = <&pclk>;
 254                         clock-names = "apb_pclk";
 255                 };
 256
 257                 mpmc@10110000 {
 258                         compatible = "arm,primecell";
 259                         reg = <0x10110000 0x1000>;
 260                         clocks = <&pclk>;
 261                         clock-names = "apb_pclk";
 262                 };
 263
 264                 display@10120000 {
 265                         compatible = "arm,pl110", "arm,primecell";
 266                         reg = <0x10120000 0x1000>;
 267                         interrupts = <16>;
 268                         clocks = <&osc1>, <&pclk>;
 269                         clock-names = "clcdclk", "apb_pclk";
 270                         /* 800x600 16bpp @ 36MHz works fine */
 271                         max-memory-bandwidth = <54000000>;
 272
 273                         /*
 274                          * This port is routed through a PLD (Programmable
 275                          * Logic Device) that routes the output from the CLCD
 276                          * (after transformations) to the VGA DAC and also an
 277                          * external panel connector. The PLD is essential for
 278                          * supporting RGB565/BGR565.
 279                          *
 280                          * The signals from the port thus reaches two endpoints.
 281                          * The PLD is managed through a few special bits in the
 282                          * FPGA "sysreg".
 283                          *
 284                          * This arrangement can be clearly seen in
 285                          * ARM DUI 0225D, page 3-41, figure 3-19.
 286                          */
 287                         port@0 {
 288                                 #address-cells = <1>;
 289                                 #size-cells = <0>;
 290
 291                                 clcd_pads_panel: endpoint@0 {
 292                                         reg = <0>;
 293                                         remote-endpoint = <&panel_in>;
 294                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 295                                 };
 296                                 clcd_pads_vga_dac: endpoint@1 {
 297                                         reg = <1>;
 298                                         remote-endpoint = <&vga_bridge_in>;
 299                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 300                                 };
 301                         };
 302                 };
 303
 304                 sctl@101e0000 {
 305                         compatible = "arm,primecell";
 306                         reg = <0x101e0000 0x1000>;
 307                         clocks = <&pclk>;
 308                         clock-names = "apb_pclk";
 309                 };
 310
 311                 watchdog@101e1000 {
 312                         compatible = "arm,primecell";
 313                         reg = <0x101e1000 0x1000>;
 314                         interrupts = <0>;
 315                         clocks = <&pclk>;
 316                         clock-names = "apb_pclk";
 317                 };
 318
 319                 timer@101e2000 {
 320                         compatible = "arm,sp804", "arm,primecell";
 321                         reg = <0x101e2000 0x1000>;
 322                         interrupts = <4>;
 323                         clocks = <&timclk>, <&timclk>, <&pclk>;
 324                         clock-names = "timer0", "timer1", "apb_pclk";
 325                 };
 326
 327                 timer@101e3000 {
 328                         compatible = "arm,sp804", "arm,primecell";
 329                         reg = <0x101e3000 0x1000>;
 330                         interrupts = <5>;
 331                         clocks = <&timclk>, <&timclk>, <&pclk>;
 332                         clock-names = "timer0", "timer1", "apb_pclk";
 333                 };
 334
 335                 gpio0: gpio@101e4000 {
 336                         compatible = "arm,pl061", "arm,primecell";
 337                         reg = <0x101e4000 0x1000>;
 338                         gpio-controller;
 339                         interrupts = <6>;
 340                         #gpio-cells = <2>;
 341                         interrupt-controller;
 342                         #interrupt-cells = <2>;
 343                         clocks = <&pclk>;
 344                         clock-names = "apb_pclk";
 345                 };
 346
 347                 gpio1: gpio@101e5000 {
 348                         compatible = "arm,pl061", "arm,primecell";
 349                         reg = <0x101e5000 0x1000>;
 350                         interrupts = <7>;
 351                         gpio-controller;
 352                         #gpio-cells = <2>;
 353                         interrupt-controller;
 354                         #interrupt-cells = <2>;
 355                         clocks = <&pclk>;
 356                         clock-names = "apb_pclk";
 357                 };
 358
 359                 rtc@101e8000 {
 360                         compatible = "arm,pl030", "arm,primecell";
 361                         reg = <0x101e8000 0x1000>;
 362                         interrupts = <10>;
 363                         clocks = <&pclk>;
 364                         clock-names = "apb_pclk";
 365                 };
 366
 367                 sci@101f0000 {
 368                         compatible = "arm,primecell";
 369                         reg = <0x101f0000 0x1000>;
 370                         interrupts = <15>;
 371                         clocks = <&pclk>;
 372                         clock-names = "apb_pclk";
 373                 };
 374
 375                 spi@101f4000 {
 376                         compatible = "arm,pl022", "arm,primecell";
 377                         reg = <0x101f4000 0x1000>;
 378                         interrupts = <11>;
 379                         clocks = <&xtal24mhz>, <&pclk>;
 380                         clock-names = "SSPCLK", "apb_pclk";
 381                 };
 382
 383                 fpga {
 384                         compatible = "arm,versatile-fpga", "simple-bus";
 385                         #address-cells = <1>;
 386                         #size-cells = <1>;
 387                         ranges = <0 0x10000000 0x10000>;
 388
 389                         sysreg@0 {
 390                                 compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
 391                                 reg = <0x00000 0x1000>;
 392
 393                                 panel: display@0 {
 394                                         compatible = "arm,versatile-tft-panel";
 395
 396                                         port {
 397                                                 panel_in: endpoint {
 398                                                         remote-endpoint = <&clcd_pads_panel>;
 399                                                 };
 400                                         };
 401                                 };
 402                         };
 403
 404                         aaci@4000 {
 405                                 compatible = "arm,primecell";
 406                                 reg = <0x4000 0x1000>;
 407                                 interrupts = <24>;
 408                                 clocks = <&pclk>;
 409                                 clock-names = "apb_pclk";
 410                         };
 411                         mmc@5000 {
 412                                 compatible = "arm,pl180", "arm,primecell";
 413                                 reg = <0x5000 0x1000>;
 414                                 interrupts-extended = <&vic 22 &sic 1>;
 415                                 clocks = <&xtal24mhz>, <&pclk>;
 416                                 clock-names = "mclk", "apb_pclk";
 417                         };
 418                         kmi@6000 {
 419                                 compatible = "arm,pl050", "arm,primecell";
 420                                 reg = <0x6000 0x1000>;
 421                                 interrupt-parent = <&sic>;
 422                                 interrupts = <3>;
 423                                 clocks = <&xtal24mhz>, <&pclk>;
 424                                 clock-names = "KMIREFCLK", "apb_pclk";
 425                         };
 426                         kmi@7000 {
 427                                 compatible = "arm,pl050", "arm,primecell";
 428                                 reg = <0x7000 0x1000>;
 429                                 interrupt-parent = <&sic>;
 430                                 interrupts = <4>;
 431                                 clocks = <&xtal24mhz>, <&pclk>;
 432                                 clock-names = "KMIREFCLK", "apb_pclk";
 433                         };
 434                 };
 435         };
 436 };