GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / vexpress-v2p-ca5s.dts
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * ARM Ltd. Versatile Express
4  *
5  * CoreTile Express A5x2
6  * Cortex-A5 MPCore (V2P-CA5s)
7  *
8  * HBI-0225B
9  */
10
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
13
14 / {
15         model = "V2P-CA5s";
16         arm,hbi = <0x225>;
17         arm,vexpress,site = <0xf>;
18         compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19         interrupt-parent = <&gic>;
20         #address-cells = <1>;
21         #size-cells = <1>;
22
23         chosen { };
24
25         aliases {
26                 serial0 = &v2m_serial0;
27                 serial1 = &v2m_serial1;
28                 serial2 = &v2m_serial2;
29                 serial3 = &v2m_serial3;
30                 i2c0 = &v2m_i2c_dvi;
31                 i2c1 = &v2m_i2c_pcie;
32         };
33
34         cpus {
35                 #address-cells = <1>;
36                 #size-cells = <0>;
37
38                 cpu@0 {
39                         device_type = "cpu";
40                         compatible = "arm,cortex-a5";
41                         reg = <0>;
42                         next-level-cache = <&L2>;
43                 };
44
45                 cpu@1 {
46                         device_type = "cpu";
47                         compatible = "arm,cortex-a5";
48                         reg = <1>;
49                         next-level-cache = <&L2>;
50                 };
51         };
52
53         memory@80000000 {
54                 device_type = "memory";
55                 reg = <0x80000000 0x40000000>;
56         };
57
58         hdlcd@2a110000 {
59                 compatible = "arm,hdlcd";
60                 reg = <0x2a110000 0x1000>;
61                 interrupts = <0 85 4>;
62                 clocks = <&hdlcd_clk>;
63                 clock-names = "pxlclk";
64         };
65
66         memory-controller@2a150000 {
67                 compatible = "arm,pl341", "arm,primecell";
68                 reg = <0x2a150000 0x1000>;
69                 clocks = <&axi_clk>;
70                 clock-names = "apb_pclk";
71         };
72
73         memory-controller@2a190000 {
74                 compatible = "arm,pl354", "arm,primecell";
75                 reg = <0x2a190000 0x1000>;
76                 interrupts = <0 86 4>,
77                              <0 87 4>;
78                 clocks = <&axi_clk>;
79                 clock-names = "apb_pclk";
80         };
81
82         scu@2c000000 {
83                 compatible = "arm,cortex-a5-scu";
84                 reg = <0x2c000000 0x58>;
85         };
86
87         timer@2c000600 {
88                 compatible = "arm,cortex-a5-twd-timer";
89                 reg = <0x2c000600 0x20>;
90                 interrupts = <1 13 0x304>;
91         };
92
93         timer@2c000200 {
94                 compatible = "arm,cortex-a5-global-timer",
95                              "arm,cortex-a9-global-timer";
96                 reg = <0x2c000200 0x20>;
97                 interrupts = <1 11 0x304>;
98                 clocks = <&cpu_clk>;
99         };
100
101         watchdog@2c000620 {
102                 compatible = "arm,cortex-a5-twd-wdt";
103                 reg = <0x2c000620 0x20>;
104                 interrupts = <1 14 0x304>;
105         };
106
107         gic: interrupt-controller@2c001000 {
108                 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
109                 #interrupt-cells = <3>;
110                 #address-cells = <0>;
111                 interrupt-controller;
112                 reg = <0x2c001000 0x1000>,
113                       <0x2c000100 0x100>;
114         };
115
116         L2: cache-controller@2c0f0000 {
117                 compatible = "arm,pl310-cache";
118                 reg = <0x2c0f0000 0x1000>;
119                 interrupts = <0 84 4>;
120                 cache-level = <2>;
121         };
122
123         pmu {
124                 compatible = "arm,cortex-a5-pmu";
125                 interrupts = <0 68 4>,
126                              <0 69 4>;
127         };
128
129         dcc {
130                 compatible = "arm,vexpress,config-bus";
131                 arm,vexpress,config-bridge = <&v2m_sysreg>;
132
133                 cpu_clk: oscclk0 {
134                         /* CPU and internal AXI reference clock */
135                         compatible = "arm,vexpress-osc";
136                         arm,vexpress-sysreg,func = <1 0>;
137                         freq-range = <50000000 100000000>;
138                         #clock-cells = <0>;
139                         clock-output-names = "oscclk0";
140                 };
141
142                 axi_clk: oscclk1 {
143                         /* Multiplexed AXI master clock */
144                         compatible = "arm,vexpress-osc";
145                         arm,vexpress-sysreg,func = <1 1>;
146                         freq-range = <5000000 50000000>;
147                         #clock-cells = <0>;
148                         clock-output-names = "oscclk1";
149                 };
150
151                 oscclk2 {
152                         /* DDR2 */
153                         compatible = "arm,vexpress-osc";
154                         arm,vexpress-sysreg,func = <1 2>;
155                         freq-range = <80000000 120000000>;
156                         #clock-cells = <0>;
157                         clock-output-names = "oscclk2";
158                 };
159
160                 hdlcd_clk: oscclk3 {
161                         /* HDLCD */
162                         compatible = "arm,vexpress-osc";
163                         arm,vexpress-sysreg,func = <1 3>;
164                         freq-range = <23750000 165000000>;
165                         #clock-cells = <0>;
166                         clock-output-names = "oscclk3";
167                 };
168
169                 oscclk4 {
170                         /* Test chip gate configuration */
171                         compatible = "arm,vexpress-osc";
172                         arm,vexpress-sysreg,func = <1 4>;
173                         freq-range = <80000000 80000000>;
174                         #clock-cells = <0>;
175                         clock-output-names = "oscclk4";
176                 };
177
178                 smbclk: oscclk5 {
179                         /* SMB clock */
180                         compatible = "arm,vexpress-osc";
181                         arm,vexpress-sysreg,func = <1 5>;
182                         freq-range = <25000000 60000000>;
183                         #clock-cells = <0>;
184                         clock-output-names = "oscclk5";
185                 };
186
187                 temp-dcc {
188                         /* DCC internal operating temperature */
189                         compatible = "arm,vexpress-temp";
190                         arm,vexpress-sysreg,func = <4 0>;
191                         label = "DCC";
192                 };
193         };
194
195         smb: smb@8000000 {
196                 compatible = "simple-bus";
197
198                 #address-cells = <2>;
199                 #size-cells = <1>;
200                 ranges = <0 0 0x08000000 0x04000000>,
201                          <1 0 0x14000000 0x04000000>,
202                          <2 0 0x18000000 0x04000000>,
203                          <3 0 0x1c000000 0x04000000>,
204                          <4 0 0x0c000000 0x04000000>,
205                          <5 0 0x10000000 0x04000000>;
206
207                 #interrupt-cells = <1>;
208                 interrupt-map-mask = <0 0 63>;
209                 interrupt-map = <0 0  0 &gic 0  0 4>,
210                                 <0 0  1 &gic 0  1 4>,
211                                 <0 0  2 &gic 0  2 4>,
212                                 <0 0  3 &gic 0  3 4>,
213                                 <0 0  4 &gic 0  4 4>,
214                                 <0 0  5 &gic 0  5 4>,
215                                 <0 0  6 &gic 0  6 4>,
216                                 <0 0  7 &gic 0  7 4>,
217                                 <0 0  8 &gic 0  8 4>,
218                                 <0 0  9 &gic 0  9 4>,
219                                 <0 0 10 &gic 0 10 4>,
220                                 <0 0 11 &gic 0 11 4>,
221                                 <0 0 12 &gic 0 12 4>,
222                                 <0 0 13 &gic 0 13 4>,
223                                 <0 0 14 &gic 0 14 4>,
224                                 <0 0 15 &gic 0 15 4>,
225                                 <0 0 16 &gic 0 16 4>,
226                                 <0 0 17 &gic 0 17 4>,
227                                 <0 0 18 &gic 0 18 4>,
228                                 <0 0 19 &gic 0 19 4>,
229                                 <0 0 20 &gic 0 20 4>,
230                                 <0 0 21 &gic 0 21 4>,
231                                 <0 0 22 &gic 0 22 4>,
232                                 <0 0 23 &gic 0 23 4>,
233                                 <0 0 24 &gic 0 24 4>,
234                                 <0 0 25 &gic 0 25 4>,
235                                 <0 0 26 &gic 0 26 4>,
236                                 <0 0 27 &gic 0 27 4>,
237                                 <0 0 28 &gic 0 28 4>,
238                                 <0 0 29 &gic 0 29 4>,
239                                 <0 0 30 &gic 0 30 4>,
240                                 <0 0 31 &gic 0 31 4>,
241                                 <0 0 32 &gic 0 32 4>,
242                                 <0 0 33 &gic 0 33 4>,
243                                 <0 0 34 &gic 0 34 4>,
244                                 <0 0 35 &gic 0 35 4>,
245                                 <0 0 36 &gic 0 36 4>,
246                                 <0 0 37 &gic 0 37 4>,
247                                 <0 0 38 &gic 0 38 4>,
248                                 <0 0 39 &gic 0 39 4>,
249                                 <0 0 40 &gic 0 40 4>,
250                                 <0 0 41 &gic 0 41 4>,
251                                 <0 0 42 &gic 0 42 4>;
252         };
253
254         site2: hsb@40000000 {
255                 compatible = "simple-bus";
256                 #address-cells = <1>;
257                 #size-cells = <1>;
258                 ranges = <0 0x40000000 0x40000000>;
259                 #interrupt-cells = <1>;
260                 interrupt-map-mask = <0 3>;
261                 interrupt-map = <0 0 &gic 0 36 4>,
262                                 <0 1 &gic 0 37 4>,
263                                 <0 2 &gic 0 38 4>,
264                                 <0 3 &gic 0 39 4>;
265         };
266 };