GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / wm8850.dtsi
1 /*
2  * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
3  *
4  * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5  *
6  * Licensed under GPLv2 or later
7  */
8
9 /include/ "skeleton.dtsi"
10
11 / {
12         compatible = "wm,wm8850";
13
14         cpus {
15                 #address-cells = <1>;
16                 #size-cells = <0>;
17
18                 cpu@0 {
19                         device_type = "cpu";
20                         compatible = "arm,cortex-a9";
21                         reg = <0x0>;
22                 };
23         };
24
25         aliases {
26                 serial0 = &uart0;
27                 serial1 = &uart1;
28                 serial2 = &uart2;
29                 serial3 = &uart3;
30         };
31
32         soc {
33                 #address-cells = <1>;
34                 #size-cells = <1>;
35                 compatible = "simple-bus";
36                 ranges;
37                 interrupt-parent = <&intc0>;
38
39                 intc0: interrupt-controller@d8140000 {
40                         compatible = "via,vt8500-intc";
41                         interrupt-controller;
42                         reg = <0xd8140000 0x10000>;
43                         #interrupt-cells = <1>;
44                 };
45
46                 /* Secondary IC cascaded to intc0 */
47                 intc1: interrupt-controller@d8150000 {
48                         compatible = "via,vt8500-intc";
49                         interrupt-controller;
50                         #interrupt-cells = <1>;
51                         reg = <0xD8150000 0x10000>;
52                         interrupts = <56 57 58 59 60 61 62 63>;
53                 };
54
55                 pinctrl: pinctrl@d8110000 {
56                         compatible = "wm,wm8850-pinctrl";
57                         reg = <0xd8110000 0x10000>;
58                         interrupt-controller;
59                         #interrupt-cells = <2>;
60                         gpio-controller;
61                         #gpio-cells = <2>;
62                 };
63
64                 pmc@d8130000 {
65                         compatible = "via,vt8500-pmc";
66                         reg = <0xd8130000 0x1000>;
67
68                         clocks {
69                                 #address-cells = <1>;
70                                 #size-cells = <0>;
71
72                                 ref25: ref25M {
73                                         #clock-cells = <0>;
74                                         compatible = "fixed-clock";
75                                         clock-frequency = <25000000>;
76                                 };
77
78                                 ref24: ref24M {
79                                         #clock-cells = <0>;
80                                         compatible = "fixed-clock";
81                                         clock-frequency = <24000000>;
82                                 };
83
84                                 plla: plla {
85                                         #clock-cells = <0>;
86                                         compatible = "wm,wm8850-pll-clock";
87                                         clocks = <&ref24>;
88                                         reg = <0x200>;
89                                 };
90
91                                 pllb: pllb {
92                                         #clock-cells = <0>;
93                                         compatible = "wm,wm8850-pll-clock";
94                                         clocks = <&ref24>;
95                                         reg = <0x204>;
96                                 };
97
98                                 pllc: pllc {
99                                         #clock-cells = <0>;
100                                         compatible = "wm,wm8850-pll-clock";
101                                         clocks = <&ref24>;
102                                         reg = <0x208>;
103                                 };
104
105                                 plld: plld {
106                                         #clock-cells = <0>;
107                                         compatible = "wm,wm8850-pll-clock";
108                                         clocks = <&ref24>;
109                                         reg = <0x20c>;
110                                 };
111
112                                 plle: plle {
113                                         #clock-cells = <0>;
114                                         compatible = "wm,wm8850-pll-clock";
115                                         clocks = <&ref24>;
116                                         reg = <0x210>;
117                                 };
118
119                                 pllf: pllf {
120                                         #clock-cells = <0>;
121                                         compatible = "wm,wm8850-pll-clock";
122                                         clocks = <&ref24>;
123                                         reg = <0x214>;
124                                 };
125
126                                 pllg: pllg {
127                                         #clock-cells = <0>;
128                                         compatible = "wm,wm8850-pll-clock";
129                                         clocks = <&ref24>;
130                                         reg = <0x218>;
131                                 };
132
133                                 clkarm: arm {
134                                         #clock-cells = <0>;
135                                         compatible = "via,vt8500-device-clock";
136                                         clocks = <&plla>;
137                                         divisor-reg = <0x300>;
138                                 };
139
140                                 clkahb: ahb {
141                                         #clock-cells = <0>;
142                                         compatible = "via,vt8500-device-clock";
143                                         clocks = <&pllb>;
144                                         divisor-reg = <0x304>;
145                                 };
146
147                                 clkapb: apb {
148                                         #clock-cells = <0>;
149                                         compatible = "via,vt8500-device-clock";
150                                         clocks = <&pllb>;
151                                         divisor-reg = <0x320>;
152                                 };
153
154                                 clkddr: ddr {
155                                         #clock-cells = <0>;
156                                         compatible = "via,vt8500-device-clock";
157                                         clocks = <&plld>;
158                                         divisor-reg = <0x310>;
159                                 };
160
161                                 clkuart0: uart0 {
162                                         #clock-cells = <0>;
163                                         compatible = "via,vt8500-device-clock";
164                                         clocks = <&ref24>;
165                                         enable-reg = <0x254>;
166                                         enable-bit = <24>;
167                                 };
168
169                                 clkuart1: uart1 {
170                                         #clock-cells = <0>;
171                                         compatible = "via,vt8500-device-clock";
172                                         clocks = <&ref24>;
173                                         enable-reg = <0x254>;
174                                         enable-bit = <25>;
175                                 };
176
177                                 clkuart2: uart2 {
178                                         #clock-cells = <0>;
179                                         compatible = "via,vt8500-device-clock";
180                                         clocks = <&ref24>;
181                                         enable-reg = <0x254>;
182                                         enable-bit = <26>;
183                                 };
184
185                                 clkuart3: uart3 {
186                                         #clock-cells = <0>;
187                                         compatible = "via,vt8500-device-clock";
188                                         clocks = <&ref24>;
189                                         enable-reg = <0x254>;
190                                         enable-bit = <27>;
191                                 };
192
193                                 clkpwm: pwm {
194                                         #clock-cells = <0>;
195                                         compatible = "via,vt8500-device-clock";
196                                         clocks = <&pllb>;
197                                         divisor-reg = <0x350>;
198                                         enable-reg = <0x250>;
199                                         enable-bit = <17>;
200                                 };
201
202                                 clksdhc: sdhc {
203                                         #clock-cells = <0>;
204                                         compatible = "via,vt8500-device-clock";
205                                         clocks = <&pllb>;
206                                         divisor-reg = <0x330>;
207                                         divisor-mask = <0x3f>;
208                                         enable-reg = <0x250>;
209                                         enable-bit = <0>;
210                                 };
211                         };
212                 };
213
214                 fb: fb@d8051700 {
215                         compatible = "wm,wm8505-fb";
216                         reg = <0xd8051700 0x200>;
217                 };
218
219                 ge_rops@d8050400 {
220                         compatible = "wm,prizm-ge-rops";
221                         reg = <0xd8050400 0x100>;
222                 };
223
224                 pwm: pwm@d8220000 {
225                         #pwm-cells = <3>;
226                         compatible = "via,vt8500-pwm";
227                         reg = <0xd8220000 0x100>;
228                         clocks = <&clkpwm>;
229                 };
230
231                 timer@d8130100 {
232                         compatible = "via,vt8500-timer";
233                         reg = <0xd8130100 0x28>;
234                         interrupts = <36>;
235                 };
236
237                 ehci@d8007900 {
238                         compatible = "via,vt8500-ehci";
239                         reg = <0xd8007900 0x200>;
240                         interrupts = <26>;
241                 };
242
243                 uhci@d8007b00 {
244                         compatible = "platform-uhci";
245                         reg = <0xd8007b00 0x200>;
246                         interrupts = <26>;
247                 };
248
249                 uhci@d8008d00 {
250                         compatible = "platform-uhci";
251                         reg = <0xd8008d00 0x200>;
252                         interrupts = <26>;
253                 };
254
255                 uart0: serial@d8200000 {
256                         compatible = "via,vt8500-uart";
257                         reg = <0xd8200000 0x1040>;
258                         interrupts = <32>;
259                         clocks = <&clkuart0>;
260                         status = "disabled";
261                 };
262
263                 uart1: serial@d82b0000 {
264                         compatible = "via,vt8500-uart";
265                         reg = <0xd82b0000 0x1040>;
266                         interrupts = <33>;
267                         clocks = <&clkuart1>;
268                         status = "disabled";
269                 };
270
271                 uart2: serial@d8210000 {
272                         compatible = "via,vt8500-uart";
273                         reg = <0xd8210000 0x1040>;
274                         interrupts = <47>;
275                         clocks = <&clkuart2>;
276                         status = "disabled";
277                 };
278
279                 uart3: serial@d82c0000 {
280                         compatible = "via,vt8500-uart";
281                         reg = <0xd82c0000 0x1040>;
282                         interrupts = <50>;
283                         clocks = <&clkuart3>;
284                         status = "disabled";
285                 };
286
287                 rtc@d8100000 {
288                         compatible = "via,vt8500-rtc";
289                         reg = <0xd8100000 0x10000>;
290                         interrupts = <48>;
291                 };
292
293                 sdhc@d800a000 {
294                         compatible = "wm,wm8505-sdhc";
295                         reg = <0xd800a000 0x1000>;
296                         interrupts = <20 21>;
297                         clocks = <&clksdhc>;
298                         bus-width = <4>;
299                         sdon-inverted;
300                 };
301
302                 ethernet@d8004000 {
303                         compatible = "via,vt8500-rhine";
304                         reg = <0xd8004000 0x100>;
305                         interrupts = <10>;
306                 };
307         };
308 };