arch/arm/include/debug/brcmstb.S

   1 /*
   2  * Copyright (C) 2016 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 #include <linux/serial_reg.h>
  14 #include <asm/cputype.h>
  15
  16 /* Physical register offset and virtual register offset */
  17 #define REG_PHYS_BASE           0xf0000000
  18 #define REG_PHYS_BASE_V7        0x08000000
  19 #define REG_VIRT_BASE           0xfc000000
  20 #define REG_PHYS_ADDR(x)        ((x) + REG_PHYS_BASE)
  21 #define REG_PHYS_ADDR_V7(x)     ((x) + REG_PHYS_BASE_V7)
  22
  23 /* Product id can be read from here */
  24 #define SUN_TOP_CTRL_BASE       REG_PHYS_ADDR(0x404000)
  25 #define SUN_TOP_CTRL_BASE_V7    REG_PHYS_ADDR_V7(0x404000)
  26
  27 #define UARTA_3390              REG_PHYS_ADDR(0x40a900)
  28 #define UARTA_7250              REG_PHYS_ADDR(0x40b400)
  29 #define UARTA_7260              REG_PHYS_ADDR(0x40c000)
  30 #define UARTA_7268              UARTA_7260
  31 #define UARTA_7271              UARTA_7268
  32 #define UARTA_7278              REG_PHYS_ADDR_V7(0x40c000)
  33 #define UARTA_7364              REG_PHYS_ADDR(0x40b000)
  34 #define UARTA_7366              UARTA_7364
  35 #define UARTA_74371             REG_PHYS_ADDR(0x406b00)
  36 #define UARTA_7439              REG_PHYS_ADDR(0x40a900)
  37 #define UARTA_7445              REG_PHYS_ADDR(0x40ab00)
  38
  39 #define UART_SHIFT              2
  40
  41 #define checkuart(rp, rv, family_id, family) \
  42                 /* Load family id */ \
  43                 ldr     rp, =family_id ; \
  44                 /* Compare SUN_TOP_CTRL value against it */ \
  45                 cmp     rp, rv ; \
  46                 /* Passed test, load address */ \
  47                 ldreq   rp, =UARTA_##family ; \
  48                 /* Jump to save UART address */ \
  49                 beq     91f
  50
  51                 .macro  addruart, rp, rv, tmp
  52                 adr     \rp, 99f                @ actual addr of 99f
  53                 ldr     \rv, [\rp]              @ linked addr is stored there
  54                 sub     \rv, \rv, \rp           @ offset between the two
  55                 ldr     \rp, [\rp, #4]          @ linked brcmstb_uart_config
  56                 sub     \tmp, \rp, \rv          @ actual brcmstb_uart_config
  57                 ldr     \rp, [\tmp]             @ Load brcmstb_uart_config
  58                 cmp     \rp, #1                 @ needs initialization?
  59                 bne     100f                    @ no; go load the addresses
  60                 mov     \rv, #0                 @ yes; record init is done
  61                 str     \rv, [\tmp]
  62
  63                 /* Check for V7 memory map if B53 */
  64                 mrc     p15, 0, \rv, c0, c0, 0  @ get Main ID register
  65                 ldr     \rp, =ARM_CPU_PART_MASK
  66                 and     \rv, \rv, \rp
  67                 ldr     \rp, =ARM_CPU_PART_BRAHMA_B53   @ check for B53 CPU
  68                 cmp     \rv, \rp
  69                 bne     10f
  70
  71                 /* if PERIPHBASE doesn't overlap REG_PHYS_BASE use V7 map */
  72                 mrc     p15, 1, \rv, c15, c3, 0 @ get PERIPHBASE from CBAR
  73                 ands    \rv, \rv, #REG_PHYS_BASE
  74                 ldreq   \rp, =SUN_TOP_CTRL_BASE_V7
  75
  76                 /* Check SUN_TOP_CTRL base */
  77 10:             ldrne   \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA
  78                 ldr     \rv, [\rp, #0]          @ get register contents
  79 ARM_BE8(        rev     \rv, \rv )
  80                 and     \rv, \rv, #0xffffff00   @ strip revision bits [7:0]
  81
  82                 /* Chip specific detection starts here */
  83 20:             checkuart(\rp, \rv, 0x33900000, 3390)
  84 21:             checkuart(\rp, \rv, 0x72500000, 7250)
  85 22:             checkuart(\rp, \rv, 0x72600000, 7260)
  86 23:             checkuart(\rp, \rv, 0x72680000, 7268)
  87 24:             checkuart(\rp, \rv, 0x72710000, 7271)
  88 25:             checkuart(\rp, \rv, 0x73640000, 7364)
  89 26:             checkuart(\rp, \rv, 0x73660000, 7366)
  90 27:             checkuart(\rp, \rv, 0x07437100, 74371)
  91 28:             checkuart(\rp, \rv, 0x74390000, 7439)
  92 29:             checkuart(\rp, \rv, 0x74450000, 7445)
  93 30:             checkuart(\rp, \rv, 0x72780000, 7278)
  94
  95                 /* No valid UART found */
  96 90:             mov     \rp, #0
  97                 /* fall through */
  98
  99                 /* Record whichever UART we chose */
 100 91:             str     \rp, [\tmp, #4]         @ Store in brcmstb_uart_phys
 101                 cmp     \rp, #0                 @ Valid UART address?
 102                 bne     92f                     @ Yes, go process it
 103                 str     \rp, [\tmp, #8]         @ Store 0 in brcmstb_uart_virt
 104                 b       100f                    @ Done
 105 92:             and     \rv, \rp, #0xffffff     @ offset within 16MB section
 106                 add     \rv, \rv, #REG_VIRT_BASE
 107                 str     \rv, [\tmp, #8]         @ Store in brcmstb_uart_virt
 108                 b       100f
 109
 110                 .align
 111 99:             .word   .
 112                 .word   brcmstb_uart_config
 113                 .ltorg
 114
 115                 /* Load previously selected UART address */
 116 100:            ldr     \rp, [\tmp, #4]         @ Load brcmstb_uart_phys
 117                 ldr     \rv, [\tmp, #8]         @ Load brcmstb_uart_virt
 118                 .endm
 119
 120                 .macro  store, rd, rx:vararg
 121 ARM_BE8(        rev     \rd, \rd )
 122                 str     \rd, \rx
 123                 .endm
 124
 125                 .macro  load, rd, rx:vararg
 126                 ldr     \rd, \rx
 127 ARM_BE8(        rev     \rd, \rd )
 128                 .endm
 129
 130                 .macro  senduart,rd,rx
 131                 store   \rd, [\rx, #UART_TX << UART_SHIFT]
 132                 .endm
 133
 134                 .macro  busyuart,rd,rx
 135 1002:           load    \rd, [\rx, #UART_LSR << UART_SHIFT]
 136                 and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
 137                 teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
 138                 bne     1002b
 139                 .endm
 140
 141                 .macro  waituart,rd,rx
 142                 .endm
 143
 144 /*
 145  * Storage for the state maintained by the macros above.
 146  *
 147  * In the kernel proper, this data is located in arch/arm/mach-bcm/brcmstb.c.
 148  * That's because this header is included from multiple files, and we only
 149  * want a single copy of the data. In particular, the UART probing code above
 150  * assumes it's running using physical addresses. This is true when this file
 151  * is included from head.o, but not when included from debug.o. So we need
 152  * to share the probe results between the two copies, rather than having
 153  * to re-run the probing again later.
 154  *
 155  * In the decompressor, we put the symbol/storage right here, since common.c
 156  * isn't included in the decompressor build. This symbol gets put in .text
 157  * even though it's really data, since .data is discarded from the
 158  * decompressor. Luckily, .text is writeable in the decompressor, unless
 159  * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug.
 160  */
 161 #if defined(ZIMAGE)
 162 brcmstb_uart_config:
 163         /* Debug UART initialization required */
 164         .word 1
 165         /* Debug UART physical address */
 166         .word 0
 167         /* Debug UART virtual address */
 168         .word 0
 169 #endif