arch/arm/mach-exynos/suspend.c

   1 /*
   2  * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Suspend support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/io.h>
  21 #include <linux/irq.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/irqdomain.h>
  24 #include <linux/of_address.h>
  25 #include <linux/err.h>
  26 #include <linux/regulator/machine.h>
  27 #include <linux/soc/samsung/exynos-pmu.h>
  28 #include <linux/soc/samsung/exynos-regs-pmu.h>
  29
  30 #include <asm/cacheflush.h>
  31 #include <asm/hardware/cache-l2x0.h>
  32 #include <asm/firmware.h>
  33 #include <asm/mcpm.h>
  34 #include <asm/smp_scu.h>
  35 #include <asm/suspend.h>
  36
  37 #include <mach/map.h>
  38
  39 #include <plat/pm-common.h>
  40
  41 #include "common.h"
  42
  43 #define REG_TABLE_END (-1U)
  44
  45 #define EXYNOS5420_CPU_STATE    0x28
  46
  47 /**
  48  * struct exynos_wkup_irq - PMU IRQ to mask mapping
  49  * @hwirq: Hardware IRQ signal of the PMU
  50  * @mask: Mask in PMU wake-up mask register
  51  */
  52 struct exynos_wkup_irq {
  53         unsigned int hwirq;
  54         u32 mask;
  55 };
  56
  57 struct exynos_pm_data {
  58         const struct exynos_wkup_irq *wkup_irq;
  59         unsigned int wake_disable_mask;
  60
  61         void (*pm_prepare)(void);
  62         void (*pm_resume_prepare)(void);
  63         void (*pm_resume)(void);
  64         int (*pm_suspend)(void);
  65         int (*cpu_suspend)(unsigned long);
  66 };
  67
  68 static const struct exynos_pm_data *pm_data __ro_after_init;
  69
  70 static int exynos5420_cpu_state;
  71 static unsigned int exynos_pmu_spare3;
  72
  73 /*
  74  * GIC wake-up support
  75  */
  76
  77 static u32 exynos_irqwake_intmask = 0xffffffff;
  78
  79 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
  80         { 73, BIT(1) }, /* RTC alarm */
  81         { 74, BIT(2) }, /* RTC tick */
  82         { /* sentinel */ },
  83 };
  84
  85 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
  86         { 44, BIT(1) }, /* RTC alarm */
  87         { 45, BIT(2) }, /* RTC tick */
  88         { /* sentinel */ },
  89 };
  90
  91 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
  92         { 43, BIT(1) }, /* RTC alarm */
  93         { 44, BIT(2) }, /* RTC tick */
  94         { /* sentinel */ },
  95 };
  96
  97 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
  98 {
  99         const struct exynos_wkup_irq *wkup_irq;
 100
 101         if (!pm_data->wkup_irq)
 102                 return -ENOENT;
 103         wkup_irq = pm_data->wkup_irq;
 104
 105         while (wkup_irq->mask) {
 106                 if (wkup_irq->hwirq == data->hwirq) {
 107                         if (!state)
 108                                 exynos_irqwake_intmask |= wkup_irq->mask;
 109                         else
 110                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
 111                         return 0;
 112                 }
 113                 ++wkup_irq;
 114         }
 115
 116         return -ENOENT;
 117 }
 118
 119 static struct irq_chip exynos_pmu_chip = {
 120         .name                   = "PMU",
 121         .irq_eoi                = irq_chip_eoi_parent,
 122         .irq_mask               = irq_chip_mask_parent,
 123         .irq_unmask             = irq_chip_unmask_parent,
 124         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 125         .irq_set_wake           = exynos_irq_set_wake,
 126 #ifdef CONFIG_SMP
 127         .irq_set_affinity       = irq_chip_set_affinity_parent,
 128 #endif
 129 };
 130
 131 static int exynos_pmu_domain_translate(struct irq_domain *d,
 132                                        struct irq_fwspec *fwspec,
 133                                        unsigned long *hwirq,
 134                                        unsigned int *type)
 135 {
 136         if (is_of_node(fwspec->fwnode)) {
 137                 if (fwspec->param_count != 3)
 138                         return -EINVAL;
 139
 140                 /* No PPI should point to this domain */
 141                 if (fwspec->param[0] != 0)
 142                         return -EINVAL;
 143
 144                 *hwirq = fwspec->param[1];
 145                 *type = fwspec->param[2];
 146                 return 0;
 147         }
 148
 149         return -EINVAL;
 150 }
 151
 152 static int exynos_pmu_domain_alloc(struct irq_domain *domain,
 153                                    unsigned int virq,
 154                                    unsigned int nr_irqs, void *data)
 155 {
 156         struct irq_fwspec *fwspec = data;
 157         struct irq_fwspec parent_fwspec;
 158         irq_hw_number_t hwirq;
 159         int i;
 160
 161         if (fwspec->param_count != 3)
 162                 return -EINVAL; /* Not GIC compliant */
 163         if (fwspec->param[0] != 0)
 164                 return -EINVAL; /* No PPI should point to this domain */
 165
 166         hwirq = fwspec->param[1];
 167
 168         for (i = 0; i < nr_irqs; i++)
 169                 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
 170                                               &exynos_pmu_chip, NULL);
 171
 172         parent_fwspec = *fwspec;
 173         parent_fwspec.fwnode = domain->parent->fwnode;
 174         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 175                                             &parent_fwspec);
 176 }
 177
 178 static const struct irq_domain_ops exynos_pmu_domain_ops = {
 179         .translate      = exynos_pmu_domain_translate,
 180         .alloc          = exynos_pmu_domain_alloc,
 181         .free           = irq_domain_free_irqs_common,
 182 };
 183
 184 static int __init exynos_pmu_irq_init(struct device_node *node,
 185                                       struct device_node *parent)
 186 {
 187         struct irq_domain *parent_domain, *domain;
 188
 189         if (!parent) {
 190                 pr_err("%pOF: no parent, giving up\n", node);
 191                 return -ENODEV;
 192         }
 193
 194         parent_domain = irq_find_host(parent);
 195         if (!parent_domain) {
 196                 pr_err("%pOF: unable to obtain parent domain\n", node);
 197                 return -ENXIO;
 198         }
 199
 200         pmu_base_addr = of_iomap(node, 0);
 201
 202         if (!pmu_base_addr) {
 203                 pr_err("%pOF: failed to find exynos pmu register\n", node);
 204                 return -ENOMEM;
 205         }
 206
 207         domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
 208                                           node, &exynos_pmu_domain_ops,
 209                                           NULL);
 210         if (!domain) {
 211                 iounmap(pmu_base_addr);
 212                 pmu_base_addr = NULL;
 213                 return -ENOMEM;
 214         }
 215
 216         /*
 217          * Clear the OF_POPULATED flag set in of_irq_init so that
 218          * later the Exynos PMU platform device won't be skipped.
 219          */
 220         of_node_clear_flag(node, OF_POPULATED);
 221
 222         return 0;
 223 }
 224
 225 #define EXYNOS_PMU_IRQ(symbol, name)    IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init)
 226
 227 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
 228 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
 229 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu");
 230 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
 231 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
 232 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
 233
 234 static int exynos_cpu_do_idle(void)
 235 {
 236         /* issue the standby signal into the pm unit. */
 237         cpu_do_idle();
 238
 239         pr_info("Failed to suspend the system\n");
 240         return 1; /* Aborting suspend */
 241 }
 242 static void exynos_flush_cache_all(void)
 243 {
 244         flush_cache_all();
 245         outer_flush_all();
 246 }
 247
 248 static int exynos_cpu_suspend(unsigned long arg)
 249 {
 250         exynos_flush_cache_all();
 251         return exynos_cpu_do_idle();
 252 }
 253
 254 static int exynos3250_cpu_suspend(unsigned long arg)
 255 {
 256         flush_cache_all();
 257         return exynos_cpu_do_idle();
 258 }
 259
 260 static int exynos5420_cpu_suspend(unsigned long arg)
 261 {
 262         /* MCPM works with HW CPU identifiers */
 263         unsigned int mpidr = read_cpuid_mpidr();
 264         unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 265         unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 266
 267         writel_relaxed(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
 268
 269         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
 270                 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
 271                 mcpm_cpu_suspend();
 272         }
 273
 274         pr_info("Failed to suspend the system\n");
 275
 276         /* return value != 0 means failure */
 277         return 1;
 278 }
 279
 280 static void exynos_pm_set_wakeup_mask(void)
 281 {
 282         /* Set wake-up mask registers */
 283         pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
 284         pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 285 }
 286
 287 static void exynos_pm_enter_sleep_mode(void)
 288 {
 289         /* Set value of power down register for sleep mode */
 290         exynos_sys_powerdown_conf(SYS_SLEEP);
 291         pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
 292 }
 293
 294 static void exynos_pm_prepare(void)
 295 {
 296         exynos_set_delayed_reset_assertion(false);
 297
 298         /* Set wake-up mask registers */
 299         exynos_pm_set_wakeup_mask();
 300
 301         exynos_pm_enter_sleep_mode();
 302
 303         /* ensure at least INFORM0 has the resume address */
 304         pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
 305 }
 306
 307 static void exynos3250_pm_prepare(void)
 308 {
 309         unsigned int tmp;
 310
 311         /* Set wake-up mask registers */
 312         exynos_pm_set_wakeup_mask();
 313
 314         tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
 315         tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 316         pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
 317
 318         exynos_pm_enter_sleep_mode();
 319
 320         /* ensure at least INFORM0 has the resume address */
 321         pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
 322 }
 323
 324 static void exynos5420_pm_prepare(void)
 325 {
 326         unsigned int tmp;
 327
 328         /* Set wake-up mask registers */
 329         exynos_pm_set_wakeup_mask();
 330
 331         exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
 332         /*
 333          * The cpu state needs to be saved and restored so that the
 334          * secondary CPUs will enter low power start. Though the U-Boot
 335          * is setting the cpu state with low power flag, the kernel
 336          * needs to restore it back in case, the primary cpu fails to
 337          * suspend for any reason.
 338          */
 339         exynos5420_cpu_state = readl_relaxed(sysram_base_addr +
 340                                              EXYNOS5420_CPU_STATE);
 341
 342         exynos_pm_enter_sleep_mode();
 343
 344         /* ensure at least INFORM0 has the resume address */
 345         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
 346                 pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
 347
 348         tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
 349         tmp &= ~EXYNOS_L2_USE_RETENTION;
 350         pmu_raw_writel(tmp, EXYNOS_L2_OPTION(0));
 351
 352         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
 353         tmp |= EXYNOS5420_UFS;
 354         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
 355
 356         tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
 357         tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
 358         pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
 359
 360         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
 361         tmp |= EXYNOS5420_EMULATION;
 362         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
 363
 364         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
 365         tmp |= EXYNOS5420_EMULATION;
 366         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
 367 }
 368
 369
 370 static int exynos_pm_suspend(void)
 371 {
 372         exynos_pm_central_suspend();
 373
 374         /* Setting SEQ_OPTION register */
 375         pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
 376                        S5P_CENTRAL_SEQ_OPTION);
 377
 378         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 379                 exynos_cpu_save_register();
 380
 381         return 0;
 382 }
 383
 384 static int exynos5420_pm_suspend(void)
 385 {
 386         u32 this_cluster;
 387
 388         exynos_pm_central_suspend();
 389
 390         /* Setting SEQ_OPTION register */
 391
 392         this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
 393         if (!this_cluster)
 394                 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
 395                                 S5P_CENTRAL_SEQ_OPTION);
 396         else
 397                 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
 398                                 S5P_CENTRAL_SEQ_OPTION);
 399         return 0;
 400 }
 401
 402 static void exynos_pm_resume(void)
 403 {
 404         u32 cpuid = read_cpuid_part();
 405
 406         if (exynos_pm_central_resume())
 407                 goto early_wakeup;
 408
 409         if (cpuid == ARM_CPU_PART_CORTEX_A9)
 410                 scu_enable(S5P_VA_SCU);
 411
 412         if (call_firmware_op(resume) == -ENOSYS
 413             && cpuid == ARM_CPU_PART_CORTEX_A9)
 414                 exynos_cpu_restore_register();
 415
 416 early_wakeup:
 417
 418         /* Clear SLEEP mode set in INFORM1 */
 419         pmu_raw_writel(0x0, S5P_INFORM1);
 420         exynos_set_delayed_reset_assertion(true);
 421 }
 422
 423 static void exynos3250_pm_resume(void)
 424 {
 425         u32 cpuid = read_cpuid_part();
 426
 427         if (exynos_pm_central_resume())
 428                 goto early_wakeup;
 429
 430         pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
 431
 432         if (call_firmware_op(resume) == -ENOSYS
 433             && cpuid == ARM_CPU_PART_CORTEX_A9)
 434                 exynos_cpu_restore_register();
 435
 436 early_wakeup:
 437
 438         /* Clear SLEEP mode set in INFORM1 */
 439         pmu_raw_writel(0x0, S5P_INFORM1);
 440 }
 441
 442 static void exynos5420_prepare_pm_resume(void)
 443 {
 444         unsigned int mpidr, cluster;
 445
 446         mpidr = read_cpuid_mpidr();
 447         cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 448
 449         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
 450                 WARN_ON(mcpm_cpu_powered_up());
 451
 452         if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
 453                 /*
 454                  * When system is resumed on the LITTLE/KFC core (cluster 1),
 455                  * the DSCR is not properly updated until the power is turned
 456                  * on also for the cluster 0. Enable it for a while to
 457                  * propagate the SPNIDEN and SPIDEN signals from Secure JTAG
 458                  * block and avoid undefined instruction issue on CP14 reset.
 459                  */
 460                 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
 461                                 EXYNOS_COMMON_CONFIGURATION(0));
 462                 pmu_raw_writel(0,
 463                                 EXYNOS_COMMON_CONFIGURATION(0));
 464         }
 465 }
 466
 467 static void exynos5420_pm_resume(void)
 468 {
 469         unsigned long tmp;
 470
 471         /* Restore the CPU0 low power state register */
 472         tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 473         pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
 474                        EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 475
 476         /* Restore the sysram cpu state register */
 477         writel_relaxed(exynos5420_cpu_state,
 478                        sysram_base_addr + EXYNOS5420_CPU_STATE);
 479
 480         pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
 481                         S5P_CENTRAL_SEQ_OPTION);
 482
 483         if (exynos_pm_central_resume())
 484                 goto early_wakeup;
 485
 486         pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
 487
 488 early_wakeup:
 489
 490         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
 491         tmp &= ~EXYNOS5420_UFS;
 492         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
 493
 494         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
 495         tmp &= ~EXYNOS5420_EMULATION;
 496         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
 497
 498         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
 499         tmp &= ~EXYNOS5420_EMULATION;
 500         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
 501
 502         /* Clear SLEEP mode set in INFORM1 */
 503         pmu_raw_writel(0x0, S5P_INFORM1);
 504 }
 505
 506 /*
 507  * Suspend Ops
 508  */
 509
 510 static int exynos_suspend_enter(suspend_state_t state)
 511 {
 512         int ret;
 513
 514         s3c_pm_debug_init();
 515
 516         S3C_PMDBG("%s: suspending the system...\n", __func__);
 517
 518         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
 519                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
 520
 521         if (exynos_irqwake_intmask == -1U
 522             && exynos_get_eint_wake_mask() == -1U) {
 523                 pr_err("%s: No wake-up sources!\n", __func__);
 524                 pr_err("%s: Aborting sleep\n", __func__);
 525                 return -EINVAL;
 526         }
 527
 528         s3c_pm_save_uarts();
 529         if (pm_data->pm_prepare)
 530                 pm_data->pm_prepare();
 531         flush_cache_all();
 532         s3c_pm_check_store();
 533
 534         ret = call_firmware_op(suspend);
 535         if (ret == -ENOSYS)
 536                 ret = cpu_suspend(0, pm_data->cpu_suspend);
 537         if (ret)
 538                 return ret;
 539
 540         if (pm_data->pm_resume_prepare)
 541                 pm_data->pm_resume_prepare();
 542         s3c_pm_restore_uarts();
 543
 544         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
 545                         pmu_raw_readl(S5P_WAKEUP_STAT));
 546
 547         s3c_pm_check_restore();
 548
 549         S3C_PMDBG("%s: resuming the system...\n", __func__);
 550
 551         return 0;
 552 }
 553
 554 static int exynos_suspend_prepare(void)
 555 {
 556         int ret;
 557
 558         /*
 559          * REVISIT: It would be better if struct platform_suspend_ops
 560          * .prepare handler get the suspend_state_t as a parameter to
 561          * avoid hard-coding the suspend to mem state. It's safe to do
 562          * it now only because the suspend_valid_only_mem function is
 563          * used as the .valid callback used to check if a given state
 564          * is supported by the platform anyways.
 565          */
 566         ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
 567         if (ret) {
 568                 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
 569                 return ret;
 570         }
 571
 572         s3c_pm_check_prepare();
 573
 574         return 0;
 575 }
 576
 577 static void exynos_suspend_finish(void)
 578 {
 579         int ret;
 580
 581         s3c_pm_check_cleanup();
 582
 583         ret = regulator_suspend_finish();
 584         if (ret)
 585                 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
 586 }
 587
 588 static const struct platform_suspend_ops exynos_suspend_ops = {
 589         .enter          = exynos_suspend_enter,
 590         .prepare        = exynos_suspend_prepare,
 591         .finish         = exynos_suspend_finish,
 592         .valid          = suspend_valid_only_mem,
 593 };
 594
 595 static const struct exynos_pm_data exynos3250_pm_data = {
 596         .wkup_irq       = exynos3250_wkup_irq,
 597         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 598         .pm_suspend     = exynos_pm_suspend,
 599         .pm_resume      = exynos3250_pm_resume,
 600         .pm_prepare     = exynos3250_pm_prepare,
 601         .cpu_suspend    = exynos3250_cpu_suspend,
 602 };
 603
 604 static const struct exynos_pm_data exynos4_pm_data = {
 605         .wkup_irq       = exynos4_wkup_irq,
 606         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 607         .pm_suspend     = exynos_pm_suspend,
 608         .pm_resume      = exynos_pm_resume,
 609         .pm_prepare     = exynos_pm_prepare,
 610         .cpu_suspend    = exynos_cpu_suspend,
 611 };
 612
 613 static const struct exynos_pm_data exynos5250_pm_data = {
 614         .wkup_irq       = exynos5250_wkup_irq,
 615         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 616         .pm_suspend     = exynos_pm_suspend,
 617         .pm_resume      = exynos_pm_resume,
 618         .pm_prepare     = exynos_pm_prepare,
 619         .cpu_suspend    = exynos_cpu_suspend,
 620 };
 621
 622 static const struct exynos_pm_data exynos5420_pm_data = {
 623         .wkup_irq       = exynos5250_wkup_irq,
 624         .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
 625         .pm_resume_prepare = exynos5420_prepare_pm_resume,
 626         .pm_resume      = exynos5420_pm_resume,
 627         .pm_suspend     = exynos5420_pm_suspend,
 628         .pm_prepare     = exynos5420_pm_prepare,
 629         .cpu_suspend    = exynos5420_cpu_suspend,
 630 };
 631
 632 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
 633         {
 634                 .compatible = "samsung,exynos3250-pmu",
 635                 .data = &exynos3250_pm_data,
 636         }, {
 637                 .compatible = "samsung,exynos4210-pmu",
 638                 .data = &exynos4_pm_data,
 639         }, {
 640                 .compatible = "samsung,exynos4212-pmu",
 641                 .data = &exynos4_pm_data,
 642         }, {
 643                 .compatible = "samsung,exynos4412-pmu",
 644                 .data = &exynos4_pm_data,
 645         }, {
 646                 .compatible = "samsung,exynos5250-pmu",
 647                 .data = &exynos5250_pm_data,
 648         }, {
 649                 .compatible = "samsung,exynos5420-pmu",
 650                 .data = &exynos5420_pm_data,
 651         },
 652         { /*sentinel*/ },
 653 };
 654
 655 static struct syscore_ops exynos_pm_syscore_ops;
 656
 657 void __init exynos_pm_init(void)
 658 {
 659         const struct of_device_id *match;
 660         struct device_node *np;
 661         u32 tmp;
 662
 663         np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
 664         if (!np) {
 665                 pr_err("Failed to find PMU node\n");
 666                 return;
 667         }
 668
 669         if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
 670                 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
 671                 of_node_put(np);
 672                 return;
 673         }
 674         of_node_put(np);
 675
 676         pm_data = (const struct exynos_pm_data *) match->data;
 677
 678         /* All wakeup disable */
 679         tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
 680         tmp |= pm_data->wake_disable_mask;
 681         pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
 682
 683         exynos_pm_syscore_ops.suspend   = pm_data->pm_suspend;
 684         exynos_pm_syscore_ops.resume    = pm_data->pm_resume;
 685
 686         register_syscore_ops(&exynos_pm_syscore_ops);
 687         suspend_set_ops(&exynos_suspend_ops);
 688 }