arch/arm/mach-hisi/platsmp.c

   1 /*
   2  * Copyright (c) 2013 Linaro Ltd.
   3  * Copyright (c) 2013 Hisilicon Limited.
   4  * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  */
  10 #include <linux/smp.h>
  11 #include <linux/io.h>
  12 #include <linux/of_address.h>
  13 #include <linux/delay.h>
  14
  15 #include <asm/cacheflush.h>
  16 #include <asm/smp_plat.h>
  17 #include <asm/smp_scu.h>
  18 #include <asm/mach/map.h>
  19
  20 #include "core.h"
  21
  22 #define HIX5HD2_BOOT_ADDRESS            0xffff0000
  23
  24 static void __iomem *ctrl_base;
  25
  26 void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
  27 {
  28         cpu = cpu_logical_map(cpu);
  29         if (!cpu || !ctrl_base)
  30                 return;
  31         writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2));
  32 }
  33
  34 int hi3xxx_get_cpu_jump(int cpu)
  35 {
  36         cpu = cpu_logical_map(cpu);
  37         if (!cpu || !ctrl_base)
  38                 return 0;
  39         return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
  40 }
  41
  42 static void __init hisi_enable_scu_a9(void)
  43 {
  44         unsigned long base = 0;
  45         void __iomem *scu_base = NULL;
  46
  47         if (scu_a9_has_base()) {
  48                 base = scu_a9_get_base();
  49                 scu_base = ioremap(base, SZ_4K);
  50                 if (!scu_base) {
  51                         pr_err("ioremap(scu_base) failed\n");
  52                         return;
  53                 }
  54                 scu_enable(scu_base);
  55                 iounmap(scu_base);
  56         }
  57 }
  58
  59 static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
  60 {
  61         struct device_node *np = NULL;
  62         u32 offset = 0;
  63
  64         hisi_enable_scu_a9();
  65         if (!ctrl_base) {
  66                 np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
  67                 if (!np) {
  68                         pr_err("failed to find hisilicon,sysctrl node\n");
  69                         return;
  70                 }
  71                 ctrl_base = of_iomap(np, 0);
  72                 if (!ctrl_base) {
  73                         of_node_put(np);
  74                         pr_err("failed to map address\n");
  75                         return;
  76                 }
  77                 if (of_property_read_u32(np, "smp-offset", &offset) < 0) {
  78                         of_node_put(np);
  79                         pr_err("failed to find smp-offset property\n");
  80                         return;
  81                 }
  82                 ctrl_base += offset;
  83                 of_node_put(np);
  84         }
  85 }
  86
  87 static int hi3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
  88 {
  89         hi3xxx_set_cpu(cpu, true);
  90         hi3xxx_set_cpu_jump(cpu, secondary_startup);
  91         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  92         return 0;
  93 }
  94
  95 static const struct smp_operations hi3xxx_smp_ops __initconst = {
  96         .smp_prepare_cpus       = hi3xxx_smp_prepare_cpus,
  97         .smp_boot_secondary     = hi3xxx_boot_secondary,
  98 #ifdef CONFIG_HOTPLUG_CPU
  99         .cpu_die                = hi3xxx_cpu_die,
 100         .cpu_kill               = hi3xxx_cpu_kill,
 101 #endif
 102 };
 103
 104 static void __init hisi_common_smp_prepare_cpus(unsigned int max_cpus)
 105 {
 106         hisi_enable_scu_a9();
 107 }
 108
 109 static void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
 110 {
 111         void __iomem *virt;
 112
 113         virt = ioremap(start_addr, PAGE_SIZE);
 114
 115         writel_relaxed(0xe51ff004, virt);       /* ldr pc, [pc, #-4] */
 116         writel_relaxed(jump_addr, virt + 4);    /* pc jump phy address */
 117         iounmap(virt);
 118 }
 119
 120 static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 121 {
 122         phys_addr_t jumpaddr;
 123
 124         jumpaddr = __pa_symbol(secondary_startup);
 125         hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
 126         hix5hd2_set_cpu(cpu, true);
 127         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 128         return 0;
 129 }
 130
 131
 132 static const struct smp_operations hix5hd2_smp_ops __initconst = {
 133         .smp_prepare_cpus       = hisi_common_smp_prepare_cpus,
 134         .smp_boot_secondary     = hix5hd2_boot_secondary,
 135 #ifdef CONFIG_HOTPLUG_CPU
 136         .cpu_die                = hix5hd2_cpu_die,
 137 #endif
 138 };
 139
 140
 141 #define SC_SCTL_REMAP_CLR      0x00000100
 142 #define HIP01_BOOT_ADDRESS     0x80000000
 143 #define REG_SC_CTRL            0x000
 144
 145 static void hip01_set_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
 146 {
 147         void __iomem *virt;
 148
 149         virt = phys_to_virt(start_addr);
 150
 151         writel_relaxed(0xe51ff004, virt);
 152         writel_relaxed(jump_addr, virt + 4);
 153 }
 154
 155 static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
 156 {
 157         phys_addr_t jumpaddr;
 158         unsigned int remap_reg_value = 0;
 159         struct device_node *node;
 160
 161
 162         jumpaddr = __pa_symbol(secondary_startup);
 163         hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
 164
 165         node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
 166         if (WARN_ON(!node))
 167                 return -1;
 168         ctrl_base = of_iomap(node, 0);
 169         of_node_put(node);
 170
 171         /* set the secondary core boot from DDR */
 172         remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL);
 173         barrier();
 174         remap_reg_value |= SC_SCTL_REMAP_CLR;
 175         barrier();
 176         writel_relaxed(remap_reg_value, ctrl_base + REG_SC_CTRL);
 177
 178         hip01_set_cpu(cpu, true);
 179
 180         return 0;
 181 }
 182
 183 static const struct smp_operations hip01_smp_ops __initconst = {
 184         .smp_prepare_cpus       = hisi_common_smp_prepare_cpus,
 185         .smp_boot_secondary     = hip01_boot_secondary,
 186 };
 187
 188 CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3620-smp", &hi3xxx_smp_ops);
 189 CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);
 190 CPU_METHOD_OF_DECLARE(hip01_smp, "hisilicon,hip01-smp", &hip01_smp_ops);