GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / mach-imx / pm-imx6.c
1 /*
2  * Copyright 2011-2014 Freescale Semiconductor, Inc.
3  * Copyright 2011 Linaro Ltd.
4  *
5  * The code contained herein is licensed under the GNU General Public
6  * License. You may obtain a copy of the GNU General Public License
7  * Version 2 or later at the following locations:
8  *
9  * http://www.opensource.org/licenses/gpl-license.html
10  * http://www.gnu.org/copyleft/gpl.html
11  */
12
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/irq.h>
17 #include <linux/genalloc.h>
18 #include <linux/irqchip/arm-gic.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/of_platform.h>
24 #include <linux/regmap.h>
25 #include <linux/suspend.h>
26 #include <asm/cacheflush.h>
27 #include <asm/fncpy.h>
28 #include <asm/proc-fns.h>
29 #include <asm/suspend.h>
30 #include <asm/tlb.h>
31
32 #include "common.h"
33 #include "hardware.h"
34
35 #define CCR                             0x0
36 #define BM_CCR_WB_COUNT                 (0x7 << 16)
37 #define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
38 #define BM_CCR_RBC_EN                   (0x1 << 27)
39
40 #define CLPCR                           0x54
41 #define BP_CLPCR_LPM                    0
42 #define BM_CLPCR_LPM                    (0x3 << 0)
43 #define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
44 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
45 #define BM_CLPCR_SBYOS                  (0x1 << 6)
46 #define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
47 #define BM_CLPCR_VSTBY                  (0x1 << 8)
48 #define BP_CLPCR_STBY_COUNT             9
49 #define BM_CLPCR_STBY_COUNT             (0x3 << 9)
50 #define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
51 #define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
52 #define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
53 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
54 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
55 #define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
56 #define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
57 #define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
58 #define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
59 #define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
60 #define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
61
62 #define CGPR                            0x64
63 #define BM_CGPR_INT_MEM_CLK_LPM         (0x1 << 17)
64
65 #define MX6Q_SUSPEND_OCRAM_SIZE         0x1000
66 #define MX6_MAX_MMDC_IO_NUM             33
67
68 static void __iomem *ccm_base;
69 static void __iomem *suspend_ocram_base;
70 static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
71
72 /*
73  * suspend ocram space layout:
74  * ======================== high address ======================
75  *                              .
76  *                              .
77  *                              .
78  *                              ^
79  *                              ^
80  *                              ^
81  *                      imx6_suspend code
82  *              PM_INFO structure(imx6_cpu_pm_info)
83  * ======================== low address =======================
84  */
85
86 struct imx6_pm_base {
87         phys_addr_t pbase;
88         void __iomem *vbase;
89 };
90
91 struct imx6_pm_socdata {
92         u32 ddr_type;
93         const char *mmdc_compat;
94         const char *src_compat;
95         const char *iomuxc_compat;
96         const char *gpc_compat;
97         const char *pl310_compat;
98         const u32 mmdc_io_num;
99         const u32 *mmdc_io_offset;
100 };
101
102 static const u32 imx6q_mmdc_io_offset[] __initconst = {
103         0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
104         0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
105         0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
106         0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
107         0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
108         0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
109         0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
110         0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
111         0x74c,                      /* GPR_ADDS */
112 };
113
114 static const u32 imx6dl_mmdc_io_offset[] __initconst = {
115         0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
116         0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
117         0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
118         0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
119         0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
120         0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
121         0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
122         0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
123         0x74c,                      /* GPR_ADDS */
124 };
125
126 static const u32 imx6sl_mmdc_io_offset[] __initconst = {
127         0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
128         0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
129         0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
130         0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
131         0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
132 };
133
134 static const u32 imx6sll_mmdc_io_offset[] __initconst = {
135         0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */
136         0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */
137         0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */
138         0x2a4, 0x2a8,               /* SDCKE0, SDCKE1*/
139 };
140
141 static const u32 imx6sx_mmdc_io_offset[] __initconst = {
142         0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
143         0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
144         0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
145         0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
146         0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
147 };
148
149 static const u32 imx6ul_mmdc_io_offset[] __initconst = {
150         0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
151         0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */
152         0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */
153         0x494, 0x4b0,               /* MODE_CTL, MODE, */
154 };
155
156 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
157         .mmdc_compat = "fsl,imx6q-mmdc",
158         .src_compat = "fsl,imx6q-src",
159         .iomuxc_compat = "fsl,imx6q-iomuxc",
160         .gpc_compat = "fsl,imx6q-gpc",
161         .pl310_compat = "arm,pl310-cache",
162         .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
163         .mmdc_io_offset = imx6q_mmdc_io_offset,
164 };
165
166 static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
167         .mmdc_compat = "fsl,imx6q-mmdc",
168         .src_compat = "fsl,imx6q-src",
169         .iomuxc_compat = "fsl,imx6dl-iomuxc",
170         .gpc_compat = "fsl,imx6q-gpc",
171         .pl310_compat = "arm,pl310-cache",
172         .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
173         .mmdc_io_offset = imx6dl_mmdc_io_offset,
174 };
175
176 static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
177         .mmdc_compat = "fsl,imx6sl-mmdc",
178         .src_compat = "fsl,imx6sl-src",
179         .iomuxc_compat = "fsl,imx6sl-iomuxc",
180         .gpc_compat = "fsl,imx6sl-gpc",
181         .pl310_compat = "arm,pl310-cache",
182         .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
183         .mmdc_io_offset = imx6sl_mmdc_io_offset,
184 };
185
186 static const struct imx6_pm_socdata imx6sll_pm_data __initconst = {
187         .mmdc_compat = "fsl,imx6sll-mmdc",
188         .src_compat = "fsl,imx6sll-src",
189         .iomuxc_compat = "fsl,imx6sll-iomuxc",
190         .gpc_compat = "fsl,imx6sll-gpc",
191         .pl310_compat = "arm,pl310-cache",
192         .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset),
193         .mmdc_io_offset = imx6sll_mmdc_io_offset,
194 };
195
196 static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
197         .mmdc_compat = "fsl,imx6sx-mmdc",
198         .src_compat = "fsl,imx6sx-src",
199         .iomuxc_compat = "fsl,imx6sx-iomuxc",
200         .gpc_compat = "fsl,imx6sx-gpc",
201         .pl310_compat = "arm,pl310-cache",
202         .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
203         .mmdc_io_offset = imx6sx_mmdc_io_offset,
204 };
205
206 static const struct imx6_pm_socdata imx6ul_pm_data __initconst = {
207         .mmdc_compat = "fsl,imx6ul-mmdc",
208         .src_compat = "fsl,imx6ul-src",
209         .iomuxc_compat = "fsl,imx6ul-iomuxc",
210         .gpc_compat = "fsl,imx6ul-gpc",
211         .pl310_compat = NULL,
212         .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset),
213         .mmdc_io_offset = imx6ul_mmdc_io_offset,
214 };
215
216 /*
217  * This structure is for passing necessary data for low level ocram
218  * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
219  * definition is changed, the offset definition in
220  * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
221  * otherwise, the suspend to ocram function will be broken!
222  */
223 struct imx6_cpu_pm_info {
224         phys_addr_t pbase; /* The physical address of pm_info. */
225         phys_addr_t resume_addr; /* The physical resume address for asm code */
226         u32 ddr_type;
227         u32 pm_info_size; /* Size of pm_info. */
228         struct imx6_pm_base mmdc_base;
229         struct imx6_pm_base src_base;
230         struct imx6_pm_base iomuxc_base;
231         struct imx6_pm_base ccm_base;
232         struct imx6_pm_base gpc_base;
233         struct imx6_pm_base l2_base;
234         u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
235         u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
236 } __aligned(8);
237
238 void imx6_set_int_mem_clk_lpm(bool enable)
239 {
240         u32 val = readl_relaxed(ccm_base + CGPR);
241
242         val &= ~BM_CGPR_INT_MEM_CLK_LPM;
243         if (enable)
244                 val |= BM_CGPR_INT_MEM_CLK_LPM;
245         writel_relaxed(val, ccm_base + CGPR);
246 }
247
248 void imx6_enable_rbc(bool enable)
249 {
250         u32 val;
251
252         /*
253          * need to mask all interrupts in GPC before
254          * operating RBC configurations
255          */
256         imx_gpc_mask_all();
257
258         /* configure RBC enable bit */
259         val = readl_relaxed(ccm_base + CCR);
260         val &= ~BM_CCR_RBC_EN;
261         val |= enable ? BM_CCR_RBC_EN : 0;
262         writel_relaxed(val, ccm_base + CCR);
263
264         /* configure RBC count */
265         val = readl_relaxed(ccm_base + CCR);
266         val &= ~BM_CCR_RBC_BYPASS_COUNT;
267         val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
268         writel(val, ccm_base + CCR);
269
270         /*
271          * need to delay at least 2 cycles of CKIL(32K)
272          * due to hardware design requirement, which is
273          * ~61us, here we use 65us for safe
274          */
275         udelay(65);
276
277         /* restore GPC interrupt mask settings */
278         imx_gpc_restore_all();
279 }
280
281 static void imx6q_enable_wb(bool enable)
282 {
283         u32 val;
284
285         /* configure well bias enable bit */
286         val = readl_relaxed(ccm_base + CLPCR);
287         val &= ~BM_CLPCR_WB_PER_AT_LPM;
288         val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
289         writel_relaxed(val, ccm_base + CLPCR);
290
291         /* configure well bias count */
292         val = readl_relaxed(ccm_base + CCR);
293         val &= ~BM_CCR_WB_COUNT;
294         val |= enable ? BM_CCR_WB_COUNT : 0;
295         writel_relaxed(val, ccm_base + CCR);
296 }
297
298 int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
299 {
300         u32 val = readl_relaxed(ccm_base + CLPCR);
301
302         val &= ~BM_CLPCR_LPM;
303         switch (mode) {
304         case WAIT_CLOCKED:
305                 break;
306         case WAIT_UNCLOCKED:
307                 val |= 0x1 << BP_CLPCR_LPM;
308                 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
309                 break;
310         case STOP_POWER_ON:
311                 val |= 0x2 << BP_CLPCR_LPM;
312                 val &= ~BM_CLPCR_VSTBY;
313                 val &= ~BM_CLPCR_SBYOS;
314                 if (cpu_is_imx6sl())
315                         val |= BM_CLPCR_BYPASS_PMIC_READY;
316                 if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
317                     cpu_is_imx6ull() || cpu_is_imx6sll())
318                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
319                 else
320                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
321                 break;
322         case WAIT_UNCLOCKED_POWER_OFF:
323                 val |= 0x1 << BP_CLPCR_LPM;
324                 val &= ~BM_CLPCR_VSTBY;
325                 val &= ~BM_CLPCR_SBYOS;
326                 break;
327         case STOP_POWER_OFF:
328                 val |= 0x2 << BP_CLPCR_LPM;
329                 val |= 0x3 << BP_CLPCR_STBY_COUNT;
330                 val |= BM_CLPCR_VSTBY;
331                 val |= BM_CLPCR_SBYOS;
332                 if (cpu_is_imx6sl() || cpu_is_imx6sx())
333                         val |= BM_CLPCR_BYPASS_PMIC_READY;
334                 if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
335                     cpu_is_imx6ull() || cpu_is_imx6sll())
336                         val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
337                 else
338                         val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
339                 break;
340         default:
341                 return -EINVAL;
342         }
343
344         /*
345          * ERR007265: CCM: When improper low-power sequence is used,
346          * the SoC enters low power mode before the ARM core executes WFI.
347          *
348          * Software workaround:
349          * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
350          *    by setting IOMUX_GPR1_GINT.
351          * 2) Software should then unmask IRQ #32 in GPC before setting CCM
352          *    Low-Power mode.
353          * 3) Software should mask IRQ #32 right after CCM Low-Power mode
354          *    is set (set bits 0-1 of CCM_CLPCR).
355          *
356          * Note that IRQ #32 is GIC SPI #0.
357          */
358         imx_gpc_hwirq_unmask(0);
359         writel_relaxed(val, ccm_base + CLPCR);
360         imx_gpc_hwirq_mask(0);
361
362         return 0;
363 }
364
365 static int imx6q_suspend_finish(unsigned long val)
366 {
367         if (!imx6_suspend_in_ocram_fn) {
368                 cpu_do_idle();
369         } else {
370                 /*
371                  * call low level suspend function in ocram,
372                  * as we need to float DDR IO.
373                  */
374                 local_flush_tlb_all();
375                 /* check if need to flush internal L2 cache */
376                 if (!((struct imx6_cpu_pm_info *)
377                         suspend_ocram_base)->l2_base.vbase)
378                         flush_cache_all();
379                 imx6_suspend_in_ocram_fn(suspend_ocram_base);
380         }
381
382         return 0;
383 }
384
385 static int imx6q_pm_enter(suspend_state_t state)
386 {
387         switch (state) {
388         case PM_SUSPEND_STANDBY:
389                 imx6_set_lpm(STOP_POWER_ON);
390                 imx6_set_int_mem_clk_lpm(true);
391                 imx_gpc_pre_suspend(false);
392                 if (cpu_is_imx6sl())
393                         imx6sl_set_wait_clk(true);
394                 /* Zzz ... */
395                 cpu_do_idle();
396                 if (cpu_is_imx6sl())
397                         imx6sl_set_wait_clk(false);
398                 imx_gpc_post_resume();
399                 imx6_set_lpm(WAIT_CLOCKED);
400                 break;
401         case PM_SUSPEND_MEM:
402                 imx6_set_lpm(STOP_POWER_OFF);
403                 imx6_set_int_mem_clk_lpm(false);
404                 imx6q_enable_wb(true);
405                 /*
406                  * For suspend into ocram, asm code already take care of
407                  * RBC setting, so we do NOT need to do that here.
408                  */
409                 if (!imx6_suspend_in_ocram_fn)
410                         imx6_enable_rbc(true);
411                 imx_gpc_pre_suspend(true);
412                 imx_anatop_pre_suspend();
413                 /* Zzz ... */
414                 cpu_suspend(0, imx6q_suspend_finish);
415                 if (cpu_is_imx6q() || cpu_is_imx6dl())
416                         imx_smp_prepare();
417                 imx_anatop_post_resume();
418                 imx_gpc_post_resume();
419                 imx6_enable_rbc(false);
420                 imx6q_enable_wb(false);
421                 imx6_set_int_mem_clk_lpm(true);
422                 imx6_set_lpm(WAIT_CLOCKED);
423                 break;
424         default:
425                 return -EINVAL;
426         }
427
428         return 0;
429 }
430
431 static int imx6q_pm_valid(suspend_state_t state)
432 {
433         return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
434 }
435
436 static const struct platform_suspend_ops imx6q_pm_ops = {
437         .enter = imx6q_pm_enter,
438         .valid = imx6q_pm_valid,
439 };
440
441 static int __init imx6_pm_get_base(struct imx6_pm_base *base,
442                                 const char *compat)
443 {
444         struct device_node *node;
445         struct resource res;
446         int ret = 0;
447
448         node = of_find_compatible_node(NULL, NULL, compat);
449         if (!node)
450                 return -ENODEV;
451
452         ret = of_address_to_resource(node, 0, &res);
453         if (ret)
454                 goto put_node;
455
456         base->pbase = res.start;
457         base->vbase = ioremap(res.start, resource_size(&res));
458         if (!base->vbase)
459                 ret = -ENOMEM;
460
461 put_node:
462         of_node_put(node);
463         return ret;
464 }
465
466 static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
467 {
468         phys_addr_t ocram_pbase;
469         struct device_node *node;
470         struct platform_device *pdev;
471         struct imx6_cpu_pm_info *pm_info;
472         struct gen_pool *ocram_pool;
473         unsigned long ocram_base;
474         int i, ret = 0;
475         const u32 *mmdc_offset_array;
476
477         suspend_set_ops(&imx6q_pm_ops);
478
479         if (!socdata) {
480                 pr_warn("%s: invalid argument!\n", __func__);
481                 return -EINVAL;
482         }
483
484         node = of_find_compatible_node(NULL, NULL, "mmio-sram");
485         if (!node) {
486                 pr_warn("%s: failed to find ocram node!\n", __func__);
487                 return -ENODEV;
488         }
489
490         pdev = of_find_device_by_node(node);
491         if (!pdev) {
492                 pr_warn("%s: failed to find ocram device!\n", __func__);
493                 ret = -ENODEV;
494                 goto put_node;
495         }
496
497         ocram_pool = gen_pool_get(&pdev->dev, NULL);
498         if (!ocram_pool) {
499                 pr_warn("%s: ocram pool unavailable!\n", __func__);
500                 ret = -ENODEV;
501                 goto put_device;
502         }
503
504         ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
505         if (!ocram_base) {
506                 pr_warn("%s: unable to alloc ocram!\n", __func__);
507                 ret = -ENOMEM;
508                 goto put_device;
509         }
510
511         ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
512
513         suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
514                 MX6Q_SUSPEND_OCRAM_SIZE, false);
515
516         memset(suspend_ocram_base, 0, sizeof(*pm_info));
517         pm_info = suspend_ocram_base;
518         pm_info->pbase = ocram_pbase;
519         pm_info->resume_addr = __pa_symbol(v7_cpu_resume);
520         pm_info->pm_info_size = sizeof(*pm_info);
521
522         /*
523          * ccm physical address is not used by asm code currently,
524          * so get ccm virtual address directly.
525          */
526         pm_info->ccm_base.vbase = ccm_base;
527
528         ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
529         if (ret) {
530                 pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
531                 goto put_device;
532         }
533
534         ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
535         if (ret) {
536                 pr_warn("%s: failed to get src base %d!\n", __func__, ret);
537                 goto src_map_failed;
538         }
539
540         ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
541         if (ret) {
542                 pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
543                 goto iomuxc_map_failed;
544         }
545
546         ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
547         if (ret) {
548                 pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
549                 goto gpc_map_failed;
550         }
551
552         if (socdata->pl310_compat) {
553                 ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat);
554                 if (ret) {
555                         pr_warn("%s: failed to get pl310-cache base %d!\n",
556                                 __func__, ret);
557                         goto pl310_cache_map_failed;
558                 }
559         }
560
561         pm_info->ddr_type = imx_mmdc_get_ddr_type();
562         pm_info->mmdc_io_num = socdata->mmdc_io_num;
563         mmdc_offset_array = socdata->mmdc_io_offset;
564
565         for (i = 0; i < pm_info->mmdc_io_num; i++) {
566                 pm_info->mmdc_io_val[i][0] =
567                         mmdc_offset_array[i];
568                 pm_info->mmdc_io_val[i][1] =
569                         readl_relaxed(pm_info->iomuxc_base.vbase +
570                         mmdc_offset_array[i]);
571         }
572
573         imx6_suspend_in_ocram_fn = fncpy(
574                 suspend_ocram_base + sizeof(*pm_info),
575                 &imx6_suspend,
576                 MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
577
578         goto put_device;
579
580 pl310_cache_map_failed:
581         iounmap(pm_info->gpc_base.vbase);
582 gpc_map_failed:
583         iounmap(pm_info->iomuxc_base.vbase);
584 iomuxc_map_failed:
585         iounmap(pm_info->src_base.vbase);
586 src_map_failed:
587         iounmap(pm_info->mmdc_base.vbase);
588 put_device:
589         put_device(&pdev->dev);
590 put_node:
591         of_node_put(node);
592
593         return ret;
594 }
595
596 static void __init imx6_pm_common_init(const struct imx6_pm_socdata
597                                         *socdata)
598 {
599         struct regmap *gpr;
600         int ret;
601
602         WARN_ON(!ccm_base);
603
604         if (IS_ENABLED(CONFIG_SUSPEND)) {
605                 ret = imx6q_suspend_init(socdata);
606                 if (ret)
607                         pr_warn("%s: No DDR LPM support with suspend %d!\n",
608                                 __func__, ret);
609         }
610
611         /*
612          * This is for SW workaround step #1 of ERR007265, see comments
613          * in imx6_set_lpm for details of this errata.
614          * Force IOMUXC irq pending, so that the interrupt to GPC can be
615          * used to deassert dsm_request signal when the signal gets
616          * asserted unexpectedly.
617          */
618         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
619         if (!IS_ERR(gpr))
620                 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
621                                    IMX6Q_GPR1_GINT);
622 }
623
624 static void imx6_pm_stby_poweroff(void)
625 {
626         gic_cpu_if_down(0);
627         imx6_set_lpm(STOP_POWER_OFF);
628         imx6q_suspend_finish(0);
629
630         mdelay(1000);
631
632         pr_emerg("Unable to poweroff system\n");
633 }
634
635 static int imx6_pm_stby_poweroff_probe(void)
636 {
637         if (pm_power_off) {
638                 pr_warn("%s: pm_power_off already claimed  %p %pf!\n",
639                         __func__, pm_power_off, pm_power_off);
640                 return -EBUSY;
641         }
642
643         pm_power_off = imx6_pm_stby_poweroff;
644         return 0;
645 }
646
647 void __init imx6_pm_ccm_init(const char *ccm_compat)
648 {
649         struct device_node *np;
650         u32 val;
651
652         np = of_find_compatible_node(NULL, NULL, ccm_compat);
653         ccm_base = of_iomap(np, 0);
654         BUG_ON(!ccm_base);
655
656         /*
657          * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core
658          * clock being shut down unexpectedly by WAIT mode.
659          */
660         val = readl_relaxed(ccm_base + CLPCR);
661         val &= ~BM_CLPCR_LPM;
662         writel_relaxed(val, ccm_base + CLPCR);
663
664         if (of_property_read_bool(np, "fsl,pmic-stby-poweroff"))
665                 imx6_pm_stby_poweroff_probe();
666 }
667
668 void __init imx6q_pm_init(void)
669 {
670         imx6_pm_common_init(&imx6q_pm_data);
671 }
672
673 void __init imx6dl_pm_init(void)
674 {
675         imx6_pm_common_init(&imx6dl_pm_data);
676 }
677
678 void __init imx6sl_pm_init(void)
679 {
680         struct regmap *gpr;
681
682         if (cpu_is_imx6sl()) {
683                 imx6_pm_common_init(&imx6sl_pm_data);
684         } else {
685                 imx6_pm_common_init(&imx6sll_pm_data);
686                 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
687                 if (!IS_ERR(gpr))
688                         regmap_update_bits(gpr, IOMUXC_GPR5,
689                                 IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0);
690         }
691 }
692
693 void __init imx6sx_pm_init(void)
694 {
695         imx6_pm_common_init(&imx6sx_pm_data);
696 }
697
698 void __init imx6ul_pm_init(void)
699 {
700         imx6_pm_common_init(&imx6ul_pm_data);
701 }