arch/arm/mach-omap2/control.c

   1 /*
   2  * OMAP2/3 System Control Module register access
   3  *
   4  * Copyright (C) 2007, 2012 Texas Instruments, Inc.
   5  * Copyright (C) 2007 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #undef DEBUG
  14
  15 #include <linux/kernel.h>
  16 #include <linux/io.h>
  17 #include <linux/of_address.h>
  18 #include <linux/regmap.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/cpu_pm.h>
  21
  22 #include "soc.h"
  23 #include "iomap.h"
  24 #include "common.h"
  25 #include "cm-regbits-34xx.h"
  26 #include "prm-regbits-34xx.h"
  27 #include "prm3xxx.h"
  28 #include "cm3xxx.h"
  29 #include "sdrc.h"
  30 #include "pm.h"
  31 #include "control.h"
  32 #include "clock.h"
  33
  34 /* Used by omap3_ctrl_save_padconf() */
  35 #define START_PADCONF_SAVE              0x2
  36 #define PADCONF_SAVE_DONE               0x1
  37
  38 static void __iomem *omap2_ctrl_base;
  39 static s16 omap2_ctrl_offset;
  40
  41 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  42 struct omap3_scratchpad {
  43         u32 boot_config_ptr;
  44         u32 public_restore_ptr;
  45         u32 secure_ram_restore_ptr;
  46         u32 sdrc_module_semaphore;
  47         u32 prcm_block_offset;
  48         u32 sdrc_block_offset;
  49 };
  50
  51 struct omap3_scratchpad_prcm_block {
  52         u32 prm_contents[2];
  53         u32 cm_contents[11];
  54         u32 prcm_block_size;
  55 };
  56
  57 struct omap3_scratchpad_sdrc_block {
  58         u16 sysconfig;
  59         u16 cs_cfg;
  60         u16 sharing;
  61         u16 err_type;
  62         u32 dll_a_ctrl;
  63         u32 dll_b_ctrl;
  64         u32 power;
  65         u32 cs_0;
  66         u32 mcfg_0;
  67         u16 mr_0;
  68         u16 emr_1_0;
  69         u16 emr_2_0;
  70         u16 emr_3_0;
  71         u32 actim_ctrla_0;
  72         u32 actim_ctrlb_0;
  73         u32 rfr_ctrl_0;
  74         u32 cs_1;
  75         u32 mcfg_1;
  76         u16 mr_1;
  77         u16 emr_1_1;
  78         u16 emr_2_1;
  79         u16 emr_3_1;
  80         u32 actim_ctrla_1;
  81         u32 actim_ctrlb_1;
  82         u32 rfr_ctrl_1;
  83         u16 dcdl_1_ctrl;
  84         u16 dcdl_2_ctrl;
  85         u32 flags;
  86         u32 block_size;
  87 };
  88
  89 void *omap3_secure_ram_storage;
  90
  91 /*
  92  * This is used to store ARM registers in SDRAM before attempting
  93  * an MPU OFF. The save and restore happens from the SRAM sleep code.
  94  * The address is stored in scratchpad, so that it can be used
  95  * during the restore path.
  96  */
  97 u32 omap3_arm_context[128];
  98
  99 struct omap3_control_regs {
 100         u32 sysconfig;
 101         u32 devconf0;
 102         u32 mem_dftrw0;
 103         u32 mem_dftrw1;
 104         u32 msuspendmux_0;
 105         u32 msuspendmux_1;
 106         u32 msuspendmux_2;
 107         u32 msuspendmux_3;
 108         u32 msuspendmux_4;
 109         u32 msuspendmux_5;
 110         u32 sec_ctrl;
 111         u32 devconf1;
 112         u32 csirxfe;
 113         u32 iva2_bootaddr;
 114         u32 iva2_bootmod;
 115         u32 wkup_ctrl;
 116         u32 debobs_0;
 117         u32 debobs_1;
 118         u32 debobs_2;
 119         u32 debobs_3;
 120         u32 debobs_4;
 121         u32 debobs_5;
 122         u32 debobs_6;
 123         u32 debobs_7;
 124         u32 debobs_8;
 125         u32 prog_io0;
 126         u32 prog_io1;
 127         u32 dss_dpll_spreading;
 128         u32 core_dpll_spreading;
 129         u32 per_dpll_spreading;
 130         u32 usbhost_dpll_spreading;
 131         u32 pbias_lite;
 132         u32 temp_sensor;
 133         u32 sramldo4;
 134         u32 sramldo5;
 135         u32 csi;
 136         u32 padconf_sys_nirq;
 137 };
 138
 139 static struct omap3_control_regs control_context;
 140 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 141
 142 void __init omap2_set_globals_control(void __iomem *ctrl)
 143 {
 144         omap2_ctrl_base = ctrl;
 145 }
 146
 147 u8 omap_ctrl_readb(u16 offset)
 148 {
 149         u32 val;
 150         u8 byte_offset = offset & 0x3;
 151
 152         val = omap_ctrl_readl(offset);
 153
 154         return (val >> (byte_offset * 8)) & 0xff;
 155 }
 156
 157 u16 omap_ctrl_readw(u16 offset)
 158 {
 159         u32 val;
 160         u16 byte_offset = offset & 0x2;
 161
 162         val = omap_ctrl_readl(offset);
 163
 164         return (val >> (byte_offset * 8)) & 0xffff;
 165 }
 166
 167 u32 omap_ctrl_readl(u16 offset)
 168 {
 169         offset &= 0xfffc;
 170
 171         return readl_relaxed(omap2_ctrl_base + offset);
 172 }
 173
 174 void omap_ctrl_writeb(u8 val, u16 offset)
 175 {
 176         u32 tmp;
 177         u8 byte_offset = offset & 0x3;
 178
 179         tmp = omap_ctrl_readl(offset);
 180
 181         tmp &= 0xffffffff ^ (0xff << (byte_offset * 8));
 182         tmp |= val << (byte_offset * 8);
 183
 184         omap_ctrl_writel(tmp, offset);
 185 }
 186
 187 void omap_ctrl_writew(u16 val, u16 offset)
 188 {
 189         u32 tmp;
 190         u8 byte_offset = offset & 0x2;
 191
 192         tmp = omap_ctrl_readl(offset);
 193
 194         tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8));
 195         tmp |= val << (byte_offset * 8);
 196
 197         omap_ctrl_writel(tmp, offset);
 198 }
 199
 200 void omap_ctrl_writel(u32 val, u16 offset)
 201 {
 202         offset &= 0xfffc;
 203         writel_relaxed(val, omap2_ctrl_base + offset);
 204 }
 205
 206 #ifdef CONFIG_ARCH_OMAP3
 207
 208 /**
 209  * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
 210  * @bootmode: 8-bit value to pass to some boot code
 211  *
 212  * Set the bootmode in the scratchpad RAM.  This is used after the
 213  * system restarts.  Not sure what actually uses this - it may be the
 214  * bootloader, rather than the boot ROM - contrary to the preserved
 215  * comment below.  No return value.
 216  */
 217 void omap3_ctrl_write_boot_mode(u8 bootmode)
 218 {
 219         u32 l;
 220
 221         l = ('B' << 24) | ('M' << 16) | bootmode;
 222
 223         /*
 224          * Reserve the first word in scratchpad for communicating
 225          * with the boot ROM. A pointer to a data structure
 226          * describing the boot process can be stored there,
 227          * cf. OMAP34xx TRM, Initialization / Software Booting
 228          * Configuration.
 229          *
 230          * XXX This should use some omap_ctrl_writel()-type function
 231          */
 232         writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
 233 }
 234
 235 #endif
 236
 237 /**
 238  * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
 239  * @bootaddr: physical address of the boot loader
 240  *
 241  * Set boot address for the boot loader of a supported processor
 242  * when a power ON sequence occurs.
 243  */
 244 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
 245 {
 246         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
 247                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
 248                      cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
 249                      soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
 250                      0;
 251
 252         if (!offset) {
 253                 pr_err("%s: unsupported omap type\n", __func__);
 254                 return;
 255         }
 256
 257         omap_ctrl_writel(bootaddr, offset);
 258 }
 259
 260 /**
 261  * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
 262  * @bootmode: 8-bit value to pass to some boot code
 263  *
 264  * Sets boot mode for the boot loader of a supported processor
 265  * when a power ON sequence occurs.
 266  */
 267 void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
 268 {
 269         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
 270                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
 271                      0;
 272
 273         if (!offset) {
 274                 pr_err("%s: unsupported omap type\n", __func__);
 275                 return;
 276         }
 277
 278         omap_ctrl_writel(bootmode, offset);
 279 }
 280
 281 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 282 /*
 283  * Clears the scratchpad contents in case of cold boot-
 284  * called during bootup
 285  */
 286 void omap3_clear_scratchpad_contents(void)
 287 {
 288         u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
 289         void __iomem *v_addr;
 290         u32 offset = 0;
 291
 292         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
 293         if (omap3xxx_prm_clear_global_cold_reset()) {
 294                 for ( ; offset <= max_offset; offset += 0x4)
 295                         writel_relaxed(0x0, (v_addr + offset));
 296         }
 297 }
 298
 299 /* Populate the scratchpad structure with restore structure */
 300 void omap3_save_scratchpad_contents(void)
 301 {
 302         void  __iomem *scratchpad_address;
 303         u32 arm_context_addr;
 304         struct omap3_scratchpad scratchpad_contents;
 305         struct omap3_scratchpad_prcm_block prcm_block_contents;
 306         struct omap3_scratchpad_sdrc_block sdrc_block_contents;
 307
 308         /*
 309          * Populate the Scratchpad contents
 310          *
 311          * The "get_*restore_pointer" functions are used to provide a
 312          * physical restore address where the ROM code jumps while waking
 313          * up from MPU OFF/OSWR state.
 314          * The restore pointer is stored into the scratchpad.
 315          */
 316         scratchpad_contents.boot_config_ptr = 0x0;
 317         if (cpu_is_omap3630())
 318                 scratchpad_contents.public_restore_ptr =
 319                         __pa_symbol(omap3_restore_3630);
 320         else if (omap_rev() != OMAP3430_REV_ES3_0 &&
 321                                         omap_rev() != OMAP3430_REV_ES3_1 &&
 322                                         omap_rev() != OMAP3430_REV_ES3_1_2)
 323                 scratchpad_contents.public_restore_ptr =
 324                         __pa_symbol(omap3_restore);
 325         else
 326                 scratchpad_contents.public_restore_ptr =
 327                         __pa_symbol(omap3_restore_es3);
 328
 329         if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 330                 scratchpad_contents.secure_ram_restore_ptr = 0x0;
 331         else
 332                 scratchpad_contents.secure_ram_restore_ptr =
 333                         (u32) __pa(omap3_secure_ram_storage);
 334         scratchpad_contents.sdrc_module_semaphore = 0x0;
 335         scratchpad_contents.prcm_block_offset = 0x2C;
 336         scratchpad_contents.sdrc_block_offset = 0x64;
 337
 338         /* Populate the PRCM block contents */
 339         omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
 340         omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
 341
 342         prcm_block_contents.prcm_block_size = 0x0;
 343
 344         /* Populate the SDRC block contents */
 345         sdrc_block_contents.sysconfig =
 346                         (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
 347         sdrc_block_contents.cs_cfg =
 348                         (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
 349         sdrc_block_contents.sharing =
 350                         (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
 351         sdrc_block_contents.err_type =
 352                         (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
 353         sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
 354         sdrc_block_contents.dll_b_ctrl = 0x0;
 355         /*
 356          * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
 357          * be programed to issue automatic self refresh on timeout
 358          * of AUTO_CNT = 1 prior to any transition to OFF mode.
 359          */
 360         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
 361                         && (omap_rev() >= OMAP3430_REV_ES3_0))
 362                 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
 363                                 ~(SDRC_POWER_AUTOCOUNT_MASK|
 364                                 SDRC_POWER_CLKCTRL_MASK)) |
 365                                 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
 366                                 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
 367         else
 368                 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
 369
 370         sdrc_block_contents.cs_0 = 0x0;
 371         sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
 372         sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
 373         sdrc_block_contents.emr_1_0 = 0x0;
 374         sdrc_block_contents.emr_2_0 = 0x0;
 375         sdrc_block_contents.emr_3_0 = 0x0;
 376         sdrc_block_contents.actim_ctrla_0 =
 377                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
 378         sdrc_block_contents.actim_ctrlb_0 =
 379                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
 380         sdrc_block_contents.rfr_ctrl_0 =
 381                         sdrc_read_reg(SDRC_RFR_CTRL_0);
 382         sdrc_block_contents.cs_1 = 0x0;
 383         sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
 384         sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
 385         sdrc_block_contents.emr_1_1 = 0x0;
 386         sdrc_block_contents.emr_2_1 = 0x0;
 387         sdrc_block_contents.emr_3_1 = 0x0;
 388         sdrc_block_contents.actim_ctrla_1 =
 389                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
 390         sdrc_block_contents.actim_ctrlb_1 =
 391                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
 392         sdrc_block_contents.rfr_ctrl_1 =
 393                         sdrc_read_reg(SDRC_RFR_CTRL_1);
 394         sdrc_block_contents.dcdl_1_ctrl = 0x0;
 395         sdrc_block_contents.dcdl_2_ctrl = 0x0;
 396         sdrc_block_contents.flags = 0x0;
 397         sdrc_block_contents.block_size = 0x0;
 398
 399         arm_context_addr = __pa_symbol(omap3_arm_context);
 400
 401         /* Copy all the contents to the scratchpad location */
 402         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 403         memcpy_toio(scratchpad_address, &scratchpad_contents,
 404                  sizeof(scratchpad_contents));
 405         /* Scratchpad contents being 32 bits, a divide by 4 done here */
 406         memcpy_toio(scratchpad_address +
 407                 scratchpad_contents.prcm_block_offset,
 408                 &prcm_block_contents, sizeof(prcm_block_contents));
 409         memcpy_toio(scratchpad_address +
 410                 scratchpad_contents.sdrc_block_offset,
 411                 &sdrc_block_contents, sizeof(sdrc_block_contents));
 412         /*
 413          * Copies the address of the location in SDRAM where ARM
 414          * registers get saved during a MPU OFF transition.
 415          */
 416         memcpy_toio(scratchpad_address +
 417                 scratchpad_contents.sdrc_block_offset +
 418                 sizeof(sdrc_block_contents), &arm_context_addr, 4);
 419 }
 420
 421 void omap3_control_save_context(void)
 422 {
 423         control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
 424         control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 425         control_context.mem_dftrw0 =
 426                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
 427         control_context.mem_dftrw1 =
 428                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
 429         control_context.msuspendmux_0 =
 430                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
 431         control_context.msuspendmux_1 =
 432                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
 433         control_context.msuspendmux_2 =
 434                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
 435         control_context.msuspendmux_3 =
 436                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
 437         control_context.msuspendmux_4 =
 438                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
 439         control_context.msuspendmux_5 =
 440                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
 441         control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
 442         control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
 443         control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
 444         control_context.iva2_bootaddr =
 445                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
 446         control_context.iva2_bootmod =
 447                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
 448         control_context.wkup_ctrl = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL);
 449         control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
 450         control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
 451         control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
 452         control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
 453         control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
 454         control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
 455         control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
 456         control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
 457         control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
 458         control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
 459         control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
 460         control_context.dss_dpll_spreading =
 461                         omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 462         control_context.core_dpll_spreading =
 463                         omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 464         control_context.per_dpll_spreading =
 465                         omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
 466         control_context.usbhost_dpll_spreading =
 467                 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 468         control_context.pbias_lite =
 469                         omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
 470         control_context.temp_sensor =
 471                         omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
 472         control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
 473         control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
 474         control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
 475         control_context.padconf_sys_nirq =
 476                 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 477 }
 478
 479 void omap3_control_restore_context(void)
 480 {
 481         omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
 482         omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
 483         omap_ctrl_writel(control_context.mem_dftrw0,
 484                                         OMAP343X_CONTROL_MEM_DFTRW0);
 485         omap_ctrl_writel(control_context.mem_dftrw1,
 486                                         OMAP343X_CONTROL_MEM_DFTRW1);
 487         omap_ctrl_writel(control_context.msuspendmux_0,
 488                                         OMAP2_CONTROL_MSUSPENDMUX_0);
 489         omap_ctrl_writel(control_context.msuspendmux_1,
 490                                         OMAP2_CONTROL_MSUSPENDMUX_1);
 491         omap_ctrl_writel(control_context.msuspendmux_2,
 492                                         OMAP2_CONTROL_MSUSPENDMUX_2);
 493         omap_ctrl_writel(control_context.msuspendmux_3,
 494                                         OMAP2_CONTROL_MSUSPENDMUX_3);
 495         omap_ctrl_writel(control_context.msuspendmux_4,
 496                                         OMAP2_CONTROL_MSUSPENDMUX_4);
 497         omap_ctrl_writel(control_context.msuspendmux_5,
 498                                         OMAP2_CONTROL_MSUSPENDMUX_5);
 499         omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
 500         omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
 501         omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
 502         omap_ctrl_writel(control_context.iva2_bootaddr,
 503                                         OMAP343X_CONTROL_IVA2_BOOTADDR);
 504         omap_ctrl_writel(control_context.iva2_bootmod,
 505                                         OMAP343X_CONTROL_IVA2_BOOTMOD);
 506         omap_ctrl_writel(control_context.wkup_ctrl, OMAP34XX_CONTROL_WKUP_CTRL);
 507         omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
 508         omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
 509         omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
 510         omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
 511         omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
 512         omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
 513         omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
 514         omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
 515         omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
 516         omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
 517         omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
 518         omap_ctrl_writel(control_context.dss_dpll_spreading,
 519                                         OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 520         omap_ctrl_writel(control_context.core_dpll_spreading,
 521                                         OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 522         omap_ctrl_writel(control_context.per_dpll_spreading,
 523                                         OMAP343X_CONTROL_PER_DPLL_SPREADING);
 524         omap_ctrl_writel(control_context.usbhost_dpll_spreading,
 525                                 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 526         omap_ctrl_writel(control_context.pbias_lite,
 527                                         OMAP343X_CONTROL_PBIAS_LITE);
 528         omap_ctrl_writel(control_context.temp_sensor,
 529                                         OMAP343X_CONTROL_TEMP_SENSOR);
 530         omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
 531         omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
 532         omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
 533         omap_ctrl_writel(control_context.padconf_sys_nirq,
 534                          OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 535 }
 536
 537 void omap3630_ctrl_disable_rta(void)
 538 {
 539         if (!cpu_is_omap3630())
 540                 return;
 541         omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
 542 }
 543
 544 /**
 545  * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
 546  *
 547  * Tell the SCM to start saving the padconf registers, then wait for
 548  * the process to complete.  Returns 0 unconditionally, although it
 549  * should also eventually be able to return -ETIMEDOUT, if the save
 550  * does not complete.
 551  *
 552  * XXX This function is missing a timeout.  What should it be?
 553  */
 554 int omap3_ctrl_save_padconf(void)
 555 {
 556         u32 cpo;
 557
 558         /* Save the padconf registers */
 559         cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
 560         cpo |= START_PADCONF_SAVE;
 561         omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
 562
 563         /* wait for the save to complete */
 564         while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 565                  & PADCONF_SAVE_DONE))
 566                 udelay(1);
 567
 568         return 0;
 569 }
 570
 571 /**
 572  * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
 573  *
 574  * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
 575  * force disable IVA2 so that it does not prevent any low-power states.
 576  */
 577 static void __init omap3_ctrl_set_iva_bootmode_idle(void)
 578 {
 579         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 580                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 581 }
 582
 583 /**
 584  * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
 585  *
 586  * Sets up the pads controlling the stacked modem in such way that the
 587  * device can enter idle.
 588  */
 589 static void __init omap3_ctrl_setup_d2d_padconf(void)
 590 {
 591         u16 mask, padconf;
 592
 593         /*
 594          * In a stand alone OMAP3430 where there is not a stacked
 595          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 596          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 597          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
 598          */
 599         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 600         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 601         padconf |= mask;
 602         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 603
 604         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 605         padconf |= mask;
 606         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 607 }
 608
 609 /**
 610  * omap3_ctrl_init - does static initializations for control module
 611  *
 612  * Initializes system control module. This sets up the sysconfig autoidle,
 613  * and sets up modem and iva2 so that they can be idled properly.
 614  */
 615 void __init omap3_ctrl_init(void)
 616 {
 617         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 618
 619         omap3_ctrl_set_iva_bootmode_idle();
 620
 621         omap3_ctrl_setup_d2d_padconf();
 622 }
 623 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 624
 625 static unsigned long am43xx_control_reg_offsets[] = {
 626         AM33XX_CONTROL_SYSCONFIG_OFFSET,
 627         AM33XX_CONTROL_STATUS_OFFSET,
 628         AM43XX_CONTROL_MPU_L2_CTRL_OFFSET,
 629         AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET,
 630         AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET,
 631         AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET,
 632         AM33XX_CONTROL_BANDGAP_CTRL_OFFSET,
 633         AM33XX_CONTROL_BANDGAP_TRIM_OFFSET,
 634         AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET,
 635         AM33XX_CONTROL_MOSC_CTRL_OFFSET,
 636         AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET,
 637         AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET,
 638         AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET,
 639         AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET,
 640         AM33XX_CONTROL_TPTC_CFG_OFFSET,
 641         AM33XX_CONTROL_USB_CTRL0_OFFSET,
 642         AM33XX_CONTROL_USB_CTRL1_OFFSET,
 643         AM43XX_CONTROL_USB_CTRL2_OFFSET,
 644         AM43XX_CONTROL_GMII_SEL_OFFSET,
 645         AM43XX_CONTROL_MPUSS_CTRL_OFFSET,
 646         AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET,
 647         AM43XX_CONTROL_PWMSS_CTRL_OFFSET,
 648         AM33XX_CONTROL_MREQPRIO_0_OFFSET,
 649         AM33XX_CONTROL_MREQPRIO_1_OFFSET,
 650         AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET,
 651         AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET,
 652         AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET,
 653         AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET,
 654         AM33XX_CONTROL_SMRT_CTRL_OFFSET,
 655         AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET,
 656         AM43XX_CONTROL_CQDETECT_STS_OFFSET,
 657         AM43XX_CONTROL_CQDETECT_STS2_OFFSET,
 658         AM43XX_CONTROL_VTP_CTRL_OFFSET,
 659         AM33XX_CONTROL_VREF_CTRL_OFFSET,
 660         AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET,
 661         AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET,
 662         AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET,
 663         AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET,
 664         AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET,
 665         AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET,
 666         AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET,
 667         AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET,
 668         AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET,
 669         AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET,
 670         AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET,
 671         AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET,
 672         AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET,
 673         AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET,
 674         AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET,
 675         AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET,
 676         AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET,
 677         AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET,
 678         AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET,
 679         AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET,
 680         AM33XX_CONTROL_RESET_ISO_OFFSET,
 681 };
 682
 683 static u32 am33xx_control_vals[ARRAY_SIZE(am43xx_control_reg_offsets)];
 684
 685 /**
 686  * am43xx_control_save_context - Save the wakeup domain registers
 687  *
 688  * Save the wkup domain registers
 689  */
 690 void am43xx_control_save_context(void)
 691 {
 692         int i;
 693
 694         for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++)
 695                 am33xx_control_vals[i] =
 696                                 omap_ctrl_readl(am43xx_control_reg_offsets[i]);
 697 }
 698
 699 /**
 700  * am43xx_control_restore_context - Restore the wakeup domain registers
 701  *
 702  * Restore the wkup domain registers
 703  */
 704 void am43xx_control_restore_context(void)
 705 {
 706         int i;
 707
 708         for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++)
 709                 omap_ctrl_writel(am33xx_control_vals[i],
 710                                  am43xx_control_reg_offsets[i]);
 711 }
 712
 713 static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
 714 {
 715         switch (cmd) {
 716         case CPU_CLUSTER_PM_ENTER:
 717                 if (enable_off_mode)
 718                         am43xx_control_save_context();
 719                 break;
 720         case CPU_CLUSTER_PM_EXIT:
 721                 if (enable_off_mode)
 722                         am43xx_control_restore_context();
 723                 break;
 724         }
 725
 726         return NOTIFY_OK;
 727 }
 728
 729 struct control_init_data {
 730         int index;
 731         void __iomem *mem;
 732         s16 offset;
 733 };
 734
 735 static struct control_init_data ctrl_data = {
 736         .index = TI_CLKM_CTRL,
 737 };
 738
 739 static const struct control_init_data omap2_ctrl_data = {
 740         .index = TI_CLKM_CTRL,
 741         .offset = -OMAP2_CONTROL_GENERAL,
 742 };
 743
 744 static const struct control_init_data ctrl_aux_data = {
 745         .index = TI_CLKM_CTRL_AUX,
 746 };
 747
 748 static const struct of_device_id omap_scrm_dt_match_table[] = {
 749         { .compatible = "ti,am3-scm", .data = &ctrl_data },
 750         { .compatible = "ti,am4-scm", .data = &ctrl_data },
 751         { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
 752         { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
 753         { .compatible = "ti,dm814-scm", .data = &ctrl_data },
 754         { .compatible = "ti,dm816-scrm", .data = &ctrl_data },
 755         { .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
 756         { .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
 757         { .compatible = "ti,omap5-scm-wkup-pad-conf", .data = &ctrl_aux_data },
 758         { .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
 759         { }
 760 };
 761
 762 /**
 763  * omap2_control_base_init - initialize iomappings for the control driver
 764  *
 765  * Detects and initializes the iomappings for the control driver, based
 766  * on the DT data. Returns 0 in success, negative error value
 767  * otherwise.
 768  */
 769 int __init omap2_control_base_init(void)
 770 {
 771         struct device_node *np;
 772         const struct of_device_id *match;
 773         struct control_init_data *data;
 774         void __iomem *mem;
 775
 776         for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
 777                 data = (struct control_init_data *)match->data;
 778
 779                 mem = of_iomap(np, 0);
 780                 if (!mem)
 781                         return -ENOMEM;
 782
 783                 if (data->index == TI_CLKM_CTRL) {
 784                         omap2_ctrl_base = mem;
 785                         omap2_ctrl_offset = data->offset;
 786                 }
 787
 788                 data->mem = mem;
 789         }
 790
 791         return 0;
 792 }
 793
 794 /**
 795  * omap_control_init - low level init for the control driver
 796  *
 797  * Initializes the low level clock infrastructure for control driver.
 798  * Returns 0 in success, negative error value in failure.
 799  */
 800 int __init omap_control_init(void)
 801 {
 802         struct device_node *np, *scm_conf;
 803         const struct of_device_id *match;
 804         const struct omap_prcm_init_data *data;
 805         int ret;
 806         struct regmap *syscon;
 807         static struct notifier_block nb;
 808
 809         for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
 810                 data = match->data;
 811
 812                 /*
 813                  * Check if we have scm_conf node, if yes, use this to
 814                  * access clock registers.
 815                  */
 816                 scm_conf = of_get_child_by_name(np, "scm_conf");
 817
 818                 if (scm_conf) {
 819                         syscon = syscon_node_to_regmap(scm_conf);
 820
 821                         if (IS_ERR(syscon))
 822                                 return PTR_ERR(syscon);
 823
 824                         if (of_get_child_by_name(scm_conf, "clocks")) {
 825                                 ret = omap2_clk_provider_init(scm_conf,
 826                                                               data->index,
 827                                                               syscon, NULL);
 828                                 if (ret)
 829                                         return ret;
 830                         }
 831                 } else {
 832                         /* No scm_conf found, direct access */
 833                         ret = omap2_clk_provider_init(np, data->index, NULL,
 834                                                       data->mem);
 835                         if (ret)
 836                                 return ret;
 837                 }
 838         }
 839
 840         /* Only AM43XX can lose ctrl registers context during rtc-ddr suspend */
 841         if (soc_is_am43xx()) {
 842                 nb.notifier_call = cpu_notifier;
 843                 cpu_pm_register_notifier(&nb);
 844         }
 845
 846         return 0;
 847 }
 848
 849 /**
 850  * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
 851  *
 852  * Legacy iomap init for clock provider. Needed only by legacy boot mode,
 853  * where the base addresses are not parsed from DT, but still required
 854  * by the clock driver to be setup properly.
 855  */
 856 void __init omap3_control_legacy_iomap_init(void)
 857 {
 858         omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
 859 }