arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 /*
   2  * Hardware modules present on the DRA7xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/hsmmc-omap.h>
  22 #include <linux/power/smartreflex.h>
  23 #include <linux/platform_data/i2c-omap.h>
  24
  25 #include <linux/omap-dma.h>
  26
  27 #include "omap_hwmod.h"
  28 #include "omap_hwmod_common_data.h"
  29 #include "cm1_7xx.h"
  30 #include "cm2_7xx.h"
  31 #include "prm7xx.h"
  32 #include "i2c.h"
  33 #include "wd_timer.h"
  34 #include "soc.h"
  35
  36 /* Base offset for all DRA7XX interrupts external to MPUSS */
  37 #define DRA7XX_IRQ_GIC_START    32
  38
  39 /* Base offset for all DRA7XX dma requests */
  40 #define DRA7XX_DMA_REQ_START    1
  41
  42
  43 /*
  44  * IP blocks
  45  */
  46
  47 /*
  48  * 'dmm' class
  49  * instance(s): dmm
  50  */
  51 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
  52         .name   = "dmm",
  53 };
  54
  55 /* dmm */
  56 static struct omap_hwmod dra7xx_dmm_hwmod = {
  57         .name           = "dmm",
  58         .class          = &dra7xx_dmm_hwmod_class,
  59         .clkdm_name     = "emif_clkdm",
  60         .prcm = {
  61                 .omap4 = {
  62                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  63                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  64                 },
  65         },
  66 };
  67
  68 /*
  69  * 'l3' class
  70  * instance(s): l3_instr, l3_main_1, l3_main_2
  71  */
  72 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  73         .name   = "l3",
  74 };
  75
  76 /* l3_instr */
  77 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  78         .name           = "l3_instr",
  79         .class          = &dra7xx_l3_hwmod_class,
  80         .clkdm_name     = "l3instr_clkdm",
  81         .prcm = {
  82                 .omap4 = {
  83                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  84                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  85                         .modulemode   = MODULEMODE_HWCTRL,
  86                 },
  87         },
  88 };
  89
  90 /* l3_main_1 */
  91 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  92         .name           = "l3_main_1",
  93         .class          = &dra7xx_l3_hwmod_class,
  94         .clkdm_name     = "l3main1_clkdm",
  95         .prcm = {
  96                 .omap4 = {
  97                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  98                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  99                 },
 100         },
 101 };
 102
 103 /* l3_main_2 */
 104 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
 105         .name           = "l3_main_2",
 106         .class          = &dra7xx_l3_hwmod_class,
 107         .clkdm_name     = "l3instr_clkdm",
 108         .prcm = {
 109                 .omap4 = {
 110                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
 111                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
 112                         .modulemode   = MODULEMODE_HWCTRL,
 113                 },
 114         },
 115 };
 116
 117 /*
 118  * 'l4' class
 119  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 120  */
 121 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 122         .name   = "l4",
 123 };
 124
 125 /* l4_cfg */
 126 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 127         .name           = "l4_cfg",
 128         .class          = &dra7xx_l4_hwmod_class,
 129         .clkdm_name     = "l4cfg_clkdm",
 130         .prcm = {
 131                 .omap4 = {
 132                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 133                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 134                 },
 135         },
 136 };
 137
 138 /* l4_per1 */
 139 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 140         .name           = "l4_per1",
 141         .class          = &dra7xx_l4_hwmod_class,
 142         .clkdm_name     = "l4per_clkdm",
 143         .prcm = {
 144                 .omap4 = {
 145                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 146                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 147                 },
 148         },
 149 };
 150
 151 /* l4_per2 */
 152 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 153         .name           = "l4_per2",
 154         .class          = &dra7xx_l4_hwmod_class,
 155         .clkdm_name     = "l4per2_clkdm",
 156         .prcm = {
 157                 .omap4 = {
 158                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 159                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 160                 },
 161         },
 162 };
 163
 164 /* l4_per3 */
 165 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 166         .name           = "l4_per3",
 167         .class          = &dra7xx_l4_hwmod_class,
 168         .clkdm_name     = "l4per3_clkdm",
 169         .prcm = {
 170                 .omap4 = {
 171                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 172                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 173                 },
 174         },
 175 };
 176
 177 /* l4_wkup */
 178 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 179         .name           = "l4_wkup",
 180         .class          = &dra7xx_l4_hwmod_class,
 181         .clkdm_name     = "wkupaon_clkdm",
 182         .prcm = {
 183                 .omap4 = {
 184                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 185                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 186                 },
 187         },
 188 };
 189
 190 /*
 191  * 'atl' class
 192  *
 193  */
 194
 195 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 196         .name   = "atl",
 197 };
 198
 199 /* atl */
 200 static struct omap_hwmod dra7xx_atl_hwmod = {
 201         .name           = "atl",
 202         .class          = &dra7xx_atl_hwmod_class,
 203         .clkdm_name     = "atl_clkdm",
 204         .main_clk       = "atl_gfclk_mux",
 205         .prcm = {
 206                 .omap4 = {
 207                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 208                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 209                         .modulemode   = MODULEMODE_SWCTRL,
 210                 },
 211         },
 212 };
 213
 214 /*
 215  * 'bb2d' class
 216  *
 217  */
 218
 219 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 220         .name   = "bb2d",
 221 };
 222
 223 /* bb2d */
 224 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 225         .name           = "bb2d",
 226         .class          = &dra7xx_bb2d_hwmod_class,
 227         .clkdm_name     = "dss_clkdm",
 228         .main_clk       = "dpll_core_h24x2_ck",
 229         .prcm = {
 230                 .omap4 = {
 231                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 232                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 233                         .modulemode   = MODULEMODE_SWCTRL,
 234                 },
 235         },
 236 };
 237
 238 /*
 239  * 'counter' class
 240  *
 241  */
 242
 243 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 244         .rev_offs       = 0x0000,
 245         .sysc_offs      = 0x0010,
 246         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 247         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 248                            SIDLE_SMART_WKUP),
 249         .sysc_fields    = &omap_hwmod_sysc_type1,
 250 };
 251
 252 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 253         .name   = "counter",
 254         .sysc   = &dra7xx_counter_sysc,
 255 };
 256
 257 /* counter_32k */
 258 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 259         .name           = "counter_32k",
 260         .class          = &dra7xx_counter_hwmod_class,
 261         .clkdm_name     = "wkupaon_clkdm",
 262         .flags          = HWMOD_SWSUP_SIDLE,
 263         .main_clk       = "wkupaon_iclk_mux",
 264         .prcm = {
 265                 .omap4 = {
 266                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 267                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 268                 },
 269         },
 270 };
 271
 272 /*
 273  * 'ctrl_module' class
 274  *
 275  */
 276
 277 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 278         .name   = "ctrl_module",
 279 };
 280
 281 /* ctrl_module_wkup */
 282 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 283         .name           = "ctrl_module_wkup",
 284         .class          = &dra7xx_ctrl_module_hwmod_class,
 285         .clkdm_name     = "wkupaon_clkdm",
 286         .prcm = {
 287                 .omap4 = {
 288                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 289                 },
 290         },
 291 };
 292
 293 /*
 294  * 'gmac' class
 295  * cpsw/gmac sub system
 296  */
 297 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
 298         .rev_offs       = 0x0,
 299         .sysc_offs      = 0x8,
 300         .syss_offs      = 0x4,
 301         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 302                            SYSS_HAS_RESET_STATUS),
 303         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 304                            MSTANDBY_NO),
 305         .sysc_fields    = &omap_hwmod_sysc_type3,
 306 };
 307
 308 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
 309         .name           = "gmac",
 310         .sysc           = &dra7xx_gmac_sysc,
 311 };
 312
 313 static struct omap_hwmod dra7xx_gmac_hwmod = {
 314         .name           = "gmac",
 315         .class          = &dra7xx_gmac_hwmod_class,
 316         .clkdm_name     = "gmac_clkdm",
 317         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 318         .main_clk       = "dpll_gmac_ck",
 319         .mpu_rt_idx     = 1,
 320         .prcm           = {
 321                 .omap4  = {
 322                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
 323                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
 324                         .modulemode     = MODULEMODE_SWCTRL,
 325                 },
 326         },
 327 };
 328
 329 /*
 330  * 'mdio' class
 331  */
 332 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
 333         .name           = "davinci_mdio",
 334 };
 335
 336 static struct omap_hwmod dra7xx_mdio_hwmod = {
 337         .name           = "davinci_mdio",
 338         .class          = &dra7xx_mdio_hwmod_class,
 339         .clkdm_name     = "gmac_clkdm",
 340         .main_clk       = "dpll_gmac_ck",
 341 };
 342
 343 /*
 344  * 'dcan' class
 345  *
 346  */
 347
 348 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 349         .name   = "dcan",
 350 };
 351
 352 /* dcan1 */
 353 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 354         .name           = "dcan1",
 355         .class          = &dra7xx_dcan_hwmod_class,
 356         .clkdm_name     = "wkupaon_clkdm",
 357         .main_clk       = "dcan1_sys_clk_mux",
 358         .flags          = HWMOD_CLKDM_NOAUTO,
 359         .prcm = {
 360                 .omap4 = {
 361                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 362                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 363                         .modulemode   = MODULEMODE_SWCTRL,
 364                 },
 365         },
 366 };
 367
 368 /* dcan2 */
 369 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 370         .name           = "dcan2",
 371         .class          = &dra7xx_dcan_hwmod_class,
 372         .clkdm_name     = "l4per2_clkdm",
 373         .main_clk       = "sys_clkin1",
 374         .flags          = HWMOD_CLKDM_NOAUTO,
 375         .prcm = {
 376                 .omap4 = {
 377                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 378                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 379                         .modulemode   = MODULEMODE_SWCTRL,
 380                 },
 381         },
 382 };
 383
 384 /* pwmss  */
 385 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
 386         .rev_offs       = 0x0,
 387         .sysc_offs      = 0x4,
 388         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 389                           SYSC_HAS_RESET_STATUS,
 390         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 391         .sysc_fields    = &omap_hwmod_sysc_type2,
 392 };
 393
 394 /*
 395  * epwmss class
 396  */
 397 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
 398         .name           = "epwmss",
 399         .sysc           = &dra7xx_epwmss_sysc,
 400 };
 401
 402 /* epwmss0 */
 403 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
 404         .name           = "epwmss0",
 405         .class          = &dra7xx_epwmss_hwmod_class,
 406         .clkdm_name     = "l4per2_clkdm",
 407         .main_clk       = "l4_root_clk_div",
 408         .prcm           = {
 409                 .omap4  = {
 410                         .modulemode     = MODULEMODE_SWCTRL,
 411                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
 412                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
 413                 },
 414         },
 415 };
 416
 417 /* epwmss1 */
 418 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
 419         .name           = "epwmss1",
 420         .class          = &dra7xx_epwmss_hwmod_class,
 421         .clkdm_name     = "l4per2_clkdm",
 422         .main_clk       = "l4_root_clk_div",
 423         .prcm           = {
 424                 .omap4  = {
 425                         .modulemode     = MODULEMODE_SWCTRL,
 426                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
 427                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
 428                 },
 429         },
 430 };
 431
 432 /* epwmss2 */
 433 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
 434         .name           = "epwmss2",
 435         .class          = &dra7xx_epwmss_hwmod_class,
 436         .clkdm_name     = "l4per2_clkdm",
 437         .main_clk       = "l4_root_clk_div",
 438         .prcm           = {
 439                 .omap4  = {
 440                         .modulemode     = MODULEMODE_SWCTRL,
 441                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
 442                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
 443                 },
 444         },
 445 };
 446
 447 /*
 448  * 'dma' class
 449  *
 450  */
 451
 452 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 453         .rev_offs       = 0x0000,
 454         .sysc_offs      = 0x002c,
 455         .syss_offs      = 0x0028,
 456         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 457                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 458                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 459                            SYSS_HAS_RESET_STATUS),
 460         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 461                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 462                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 463         .sysc_fields    = &omap_hwmod_sysc_type1,
 464 };
 465
 466 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 467         .name   = "dma",
 468         .sysc   = &dra7xx_dma_sysc,
 469 };
 470
 471 /* dma dev_attr */
 472 static struct omap_dma_dev_attr dma_dev_attr = {
 473         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 474                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 475         .lch_count      = 32,
 476 };
 477
 478 /* dma_system */
 479 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 480         .name           = "dma_system",
 481         .class          = &dra7xx_dma_hwmod_class,
 482         .clkdm_name     = "dma_clkdm",
 483         .main_clk       = "l3_iclk_div",
 484         .prcm = {
 485                 .omap4 = {
 486                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 487                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 488                 },
 489         },
 490         .dev_attr       = &dma_dev_attr,
 491 };
 492
 493 /*
 494  * 'tpcc' class
 495  *
 496  */
 497 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
 498         .name           = "tpcc",
 499 };
 500
 501 static struct omap_hwmod dra7xx_tpcc_hwmod = {
 502         .name           = "tpcc",
 503         .class          = &dra7xx_tpcc_hwmod_class,
 504         .clkdm_name     = "l3main1_clkdm",
 505         .main_clk       = "l3_iclk_div",
 506         .prcm           = {
 507                 .omap4  = {
 508                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
 509                         .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
 510                 },
 511         },
 512 };
 513
 514 /*
 515  * 'tptc' class
 516  *
 517  */
 518 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
 519         .name           = "tptc",
 520 };
 521
 522 /* tptc0 */
 523 static struct omap_hwmod dra7xx_tptc0_hwmod = {
 524         .name           = "tptc0",
 525         .class          = &dra7xx_tptc_hwmod_class,
 526         .clkdm_name     = "l3main1_clkdm",
 527         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 528         .main_clk       = "l3_iclk_div",
 529         .prcm           = {
 530                 .omap4  = {
 531                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
 532                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
 533                         .modulemode   = MODULEMODE_HWCTRL,
 534                 },
 535         },
 536 };
 537
 538 /* tptc1 */
 539 static struct omap_hwmod dra7xx_tptc1_hwmod = {
 540         .name           = "tptc1",
 541         .class          = &dra7xx_tptc_hwmod_class,
 542         .clkdm_name     = "l3main1_clkdm",
 543         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 544         .main_clk       = "l3_iclk_div",
 545         .prcm           = {
 546                 .omap4  = {
 547                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
 548                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
 549                         .modulemode   = MODULEMODE_HWCTRL,
 550                 },
 551         },
 552 };
 553
 554 /*
 555  * 'dss' class
 556  *
 557  */
 558
 559 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 560         .rev_offs       = 0x0000,
 561         .syss_offs      = 0x0014,
 562         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 563 };
 564
 565 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 566         .name   = "dss",
 567         .sysc   = &dra7xx_dss_sysc,
 568         .reset  = omap_dss_reset,
 569 };
 570
 571 /* dss */
 572 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 573         { .role = "dss_clk", .clk = "dss_dss_clk" },
 574         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 575         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 576         { .role = "video2_clk", .clk = "dss_video2_clk" },
 577         { .role = "video1_clk", .clk = "dss_video1_clk" },
 578         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 579         { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
 580 };
 581
 582 static struct omap_hwmod dra7xx_dss_hwmod = {
 583         .name           = "dss_core",
 584         .class          = &dra7xx_dss_hwmod_class,
 585         .clkdm_name     = "dss_clkdm",
 586         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 587         .main_clk       = "dss_dss_clk",
 588         .prcm = {
 589                 .omap4 = {
 590                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 591                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 592                         .modulemode   = MODULEMODE_SWCTRL,
 593                 },
 594         },
 595         .opt_clks       = dss_opt_clks,
 596         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 597 };
 598
 599 /*
 600  * 'dispc' class
 601  * display controller
 602  */
 603
 604 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 605         .rev_offs       = 0x0000,
 606         .sysc_offs      = 0x0010,
 607         .syss_offs      = 0x0014,
 608         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 609                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 610                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 611                            SYSS_HAS_RESET_STATUS),
 612         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 613                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 614         .sysc_fields    = &omap_hwmod_sysc_type1,
 615 };
 616
 617 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 618         .name   = "dispc",
 619         .sysc   = &dra7xx_dispc_sysc,
 620 };
 621
 622 /* dss_dispc */
 623 /* dss_dispc dev_attr */
 624 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 625         .has_framedonetv_irq    = 1,
 626         .manager_count          = 4,
 627 };
 628
 629 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 630         .name           = "dss_dispc",
 631         .class          = &dra7xx_dispc_hwmod_class,
 632         .clkdm_name     = "dss_clkdm",
 633         .main_clk       = "dss_dss_clk",
 634         .prcm = {
 635                 .omap4 = {
 636                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 637                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 638                 },
 639         },
 640         .dev_attr       = &dss_dispc_dev_attr,
 641         .parent_hwmod   = &dra7xx_dss_hwmod,
 642 };
 643
 644 /*
 645  * 'hdmi' class
 646  * hdmi controller
 647  */
 648
 649 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 650         .rev_offs       = 0x0000,
 651         .sysc_offs      = 0x0010,
 652         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 653                            SYSC_HAS_SOFTRESET),
 654         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 655                            SIDLE_SMART_WKUP),
 656         .sysc_fields    = &omap_hwmod_sysc_type2,
 657 };
 658
 659 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 660         .name   = "hdmi",
 661         .sysc   = &dra7xx_hdmi_sysc,
 662 };
 663
 664 /* dss_hdmi */
 665
 666 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 667         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 668 };
 669
 670 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 671         .name           = "dss_hdmi",
 672         .class          = &dra7xx_hdmi_hwmod_class,
 673         .clkdm_name     = "dss_clkdm",
 674         .main_clk       = "dss_48mhz_clk",
 675         .prcm = {
 676                 .omap4 = {
 677                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 678                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 679                 },
 680         },
 681         .opt_clks       = dss_hdmi_opt_clks,
 682         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 683         .parent_hwmod   = &dra7xx_dss_hwmod,
 684 };
 685
 686 /* AES (the 'P' (public) device) */
 687 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
 688         .rev_offs       = 0x0080,
 689         .sysc_offs      = 0x0084,
 690         .syss_offs      = 0x0088,
 691         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 692 };
 693
 694 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
 695         .name   = "aes",
 696         .sysc   = &dra7xx_aes_sysc,
 697         .rev    = 2,
 698 };
 699
 700 /* AES1 */
 701 static struct omap_hwmod dra7xx_aes1_hwmod = {
 702         .name           = "aes1",
 703         .class          = &dra7xx_aes_hwmod_class,
 704         .clkdm_name     = "l4sec_clkdm",
 705         .main_clk       = "l3_iclk_div",
 706         .prcm = {
 707                 .omap4 = {
 708                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 709                         .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
 710                         .modulemode   = MODULEMODE_HWCTRL,
 711                 },
 712         },
 713 };
 714
 715 /* AES2 */
 716 static struct omap_hwmod dra7xx_aes2_hwmod = {
 717         .name           = "aes2",
 718         .class          = &dra7xx_aes_hwmod_class,
 719         .clkdm_name     = "l4sec_clkdm",
 720         .main_clk       = "l3_iclk_div",
 721         .prcm = {
 722                 .omap4 = {
 723                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 724                         .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
 725                         .modulemode   = MODULEMODE_HWCTRL,
 726                 },
 727         },
 728 };
 729
 730 /* sha0 HIB2 (the 'P' (public) device) */
 731 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
 732         .rev_offs       = 0x100,
 733         .sysc_offs      = 0x110,
 734         .syss_offs      = 0x114,
 735         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 736 };
 737
 738 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
 739         .name           = "sham",
 740         .sysc           = &dra7xx_sha0_sysc,
 741         .rev            = 2,
 742 };
 743
 744 struct omap_hwmod dra7xx_sha0_hwmod = {
 745         .name           = "sham",
 746         .class          = &dra7xx_sha0_hwmod_class,
 747         .clkdm_name     = "l4sec_clkdm",
 748         .main_clk       = "l3_iclk_div",
 749         .prcm           = {
 750                 .omap4 = {
 751                         .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 752                         .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 753                         .modulemode   = MODULEMODE_HWCTRL,
 754                 },
 755         },
 756 };
 757
 758 /*
 759  * 'elm' class
 760  *
 761  */
 762
 763 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 764         .rev_offs       = 0x0000,
 765         .sysc_offs      = 0x0010,
 766         .syss_offs      = 0x0014,
 767         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 768                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 769                            SYSS_HAS_RESET_STATUS),
 770         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 771                            SIDLE_SMART_WKUP),
 772         .sysc_fields    = &omap_hwmod_sysc_type1,
 773 };
 774
 775 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 776         .name   = "elm",
 777         .sysc   = &dra7xx_elm_sysc,
 778 };
 779
 780 /* elm */
 781
 782 static struct omap_hwmod dra7xx_elm_hwmod = {
 783         .name           = "elm",
 784         .class          = &dra7xx_elm_hwmod_class,
 785         .clkdm_name     = "l4per_clkdm",
 786         .main_clk       = "l3_iclk_div",
 787         .prcm = {
 788                 .omap4 = {
 789                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 790                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 791                 },
 792         },
 793 };
 794
 795 /*
 796  * 'gpio' class
 797  *
 798  */
 799
 800 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
 801         .rev_offs       = 0x0000,
 802         .sysc_offs      = 0x0010,
 803         .syss_offs      = 0x0114,
 804         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 805                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 806                            SYSS_HAS_RESET_STATUS),
 807         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 808                            SIDLE_SMART_WKUP),
 809         .sysc_fields    = &omap_hwmod_sysc_type1,
 810 };
 811
 812 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 813         .name   = "gpio",
 814         .sysc   = &dra7xx_gpio_sysc,
 815         .rev    = 2,
 816 };
 817
 818 /* gpio1 */
 819 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 820         { .role = "dbclk", .clk = "gpio1_dbclk" },
 821 };
 822
 823 static struct omap_hwmod dra7xx_gpio1_hwmod = {
 824         .name           = "gpio1",
 825         .class          = &dra7xx_gpio_hwmod_class,
 826         .clkdm_name     = "wkupaon_clkdm",
 827         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 828         .main_clk       = "wkupaon_iclk_mux",
 829         .prcm = {
 830                 .omap4 = {
 831                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 832                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 833                         .modulemode   = MODULEMODE_HWCTRL,
 834                 },
 835         },
 836         .opt_clks       = gpio1_opt_clks,
 837         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 838 };
 839
 840 /* gpio2 */
 841 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 842         { .role = "dbclk", .clk = "gpio2_dbclk" },
 843 };
 844
 845 static struct omap_hwmod dra7xx_gpio2_hwmod = {
 846         .name           = "gpio2",
 847         .class          = &dra7xx_gpio_hwmod_class,
 848         .clkdm_name     = "l4per_clkdm",
 849         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 850         .main_clk       = "l3_iclk_div",
 851         .prcm = {
 852                 .omap4 = {
 853                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 854                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 855                         .modulemode   = MODULEMODE_HWCTRL,
 856                 },
 857         },
 858         .opt_clks       = gpio2_opt_clks,
 859         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 860 };
 861
 862 /* gpio3 */
 863 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 864         { .role = "dbclk", .clk = "gpio3_dbclk" },
 865 };
 866
 867 static struct omap_hwmod dra7xx_gpio3_hwmod = {
 868         .name           = "gpio3",
 869         .class          = &dra7xx_gpio_hwmod_class,
 870         .clkdm_name     = "l4per_clkdm",
 871         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 872         .main_clk       = "l3_iclk_div",
 873         .prcm = {
 874                 .omap4 = {
 875                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 876                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 877                         .modulemode   = MODULEMODE_HWCTRL,
 878                 },
 879         },
 880         .opt_clks       = gpio3_opt_clks,
 881         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 882 };
 883
 884 /* gpio4 */
 885 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 886         { .role = "dbclk", .clk = "gpio4_dbclk" },
 887 };
 888
 889 static struct omap_hwmod dra7xx_gpio4_hwmod = {
 890         .name           = "gpio4",
 891         .class          = &dra7xx_gpio_hwmod_class,
 892         .clkdm_name     = "l4per_clkdm",
 893         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 894         .main_clk       = "l3_iclk_div",
 895         .prcm = {
 896                 .omap4 = {
 897                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 898                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 899                         .modulemode   = MODULEMODE_HWCTRL,
 900                 },
 901         },
 902         .opt_clks       = gpio4_opt_clks,
 903         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 904 };
 905
 906 /* gpio5 */
 907 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 908         { .role = "dbclk", .clk = "gpio5_dbclk" },
 909 };
 910
 911 static struct omap_hwmod dra7xx_gpio5_hwmod = {
 912         .name           = "gpio5",
 913         .class          = &dra7xx_gpio_hwmod_class,
 914         .clkdm_name     = "l4per_clkdm",
 915         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 916         .main_clk       = "l3_iclk_div",
 917         .prcm = {
 918                 .omap4 = {
 919                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 920                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 921                         .modulemode   = MODULEMODE_HWCTRL,
 922                 },
 923         },
 924         .opt_clks       = gpio5_opt_clks,
 925         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 926 };
 927
 928 /* gpio6 */
 929 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 930         { .role = "dbclk", .clk = "gpio6_dbclk" },
 931 };
 932
 933 static struct omap_hwmod dra7xx_gpio6_hwmod = {
 934         .name           = "gpio6",
 935         .class          = &dra7xx_gpio_hwmod_class,
 936         .clkdm_name     = "l4per_clkdm",
 937         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 938         .main_clk       = "l3_iclk_div",
 939         .prcm = {
 940                 .omap4 = {
 941                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 942                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 943                         .modulemode   = MODULEMODE_HWCTRL,
 944                 },
 945         },
 946         .opt_clks       = gpio6_opt_clks,
 947         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 948 };
 949
 950 /* gpio7 */
 951 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 952         { .role = "dbclk", .clk = "gpio7_dbclk" },
 953 };
 954
 955 static struct omap_hwmod dra7xx_gpio7_hwmod = {
 956         .name           = "gpio7",
 957         .class          = &dra7xx_gpio_hwmod_class,
 958         .clkdm_name     = "l4per_clkdm",
 959         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 960         .main_clk       = "l3_iclk_div",
 961         .prcm = {
 962                 .omap4 = {
 963                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 964                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 965                         .modulemode   = MODULEMODE_HWCTRL,
 966                 },
 967         },
 968         .opt_clks       = gpio7_opt_clks,
 969         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 970 };
 971
 972 /* gpio8 */
 973 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 974         { .role = "dbclk", .clk = "gpio8_dbclk" },
 975 };
 976
 977 static struct omap_hwmod dra7xx_gpio8_hwmod = {
 978         .name           = "gpio8",
 979         .class          = &dra7xx_gpio_hwmod_class,
 980         .clkdm_name     = "l4per_clkdm",
 981         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 982         .main_clk       = "l3_iclk_div",
 983         .prcm = {
 984                 .omap4 = {
 985                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 986                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 987                         .modulemode   = MODULEMODE_HWCTRL,
 988                 },
 989         },
 990         .opt_clks       = gpio8_opt_clks,
 991         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 992 };
 993
 994 /*
 995  * 'gpmc' class
 996  *
 997  */
 998
 999 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1000         .rev_offs       = 0x0000,
1001         .sysc_offs      = 0x0010,
1002         .syss_offs      = 0x0014,
1003         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1004                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1005         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1006         .sysc_fields    = &omap_hwmod_sysc_type1,
1007 };
1008
1009 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1010         .name   = "gpmc",
1011         .sysc   = &dra7xx_gpmc_sysc,
1012 };
1013
1014 /* gpmc */
1015
1016 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1017         .name           = "gpmc",
1018         .class          = &dra7xx_gpmc_hwmod_class,
1019         .clkdm_name     = "l3main1_clkdm",
1020         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1021         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1022         .main_clk       = "l3_iclk_div",
1023         .prcm = {
1024                 .omap4 = {
1025                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1026                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1027                         .modulemode   = MODULEMODE_HWCTRL,
1028                 },
1029         },
1030 };
1031
1032 /*
1033  * 'hdq1w' class
1034  *
1035  */
1036
1037 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1038         .rev_offs       = 0x0000,
1039         .sysc_offs      = 0x0014,
1040         .syss_offs      = 0x0018,
1041         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1042                            SYSS_HAS_RESET_STATUS),
1043         .sysc_fields    = &omap_hwmod_sysc_type1,
1044 };
1045
1046 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1047         .name   = "hdq1w",
1048         .sysc   = &dra7xx_hdq1w_sysc,
1049 };
1050
1051 /* hdq1w */
1052
1053 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1054         .name           = "hdq1w",
1055         .class          = &dra7xx_hdq1w_hwmod_class,
1056         .clkdm_name     = "l4per_clkdm",
1057         .flags          = HWMOD_INIT_NO_RESET,
1058         .main_clk       = "func_12m_fclk",
1059         .prcm = {
1060                 .omap4 = {
1061                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1062                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1063                         .modulemode   = MODULEMODE_SWCTRL,
1064                 },
1065         },
1066 };
1067
1068 /*
1069  * 'i2c' class
1070  *
1071  */
1072
1073 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1074         .rev_offs       = 0,
1075         .sysc_offs      = 0x0010,
1076         .syss_offs      = 0x0090,
1077         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1078                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1079                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1080         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1081                            SIDLE_SMART_WKUP),
1082         .sysc_fields    = &omap_hwmod_sysc_type1,
1083 };
1084
1085 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1086         .name   = "i2c",
1087         .sysc   = &dra7xx_i2c_sysc,
1088         .reset  = &omap_i2c_reset,
1089         .rev    = OMAP_I2C_IP_VERSION_2,
1090 };
1091
1092 /* i2c1 */
1093 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1094         .name           = "i2c1",
1095         .class          = &dra7xx_i2c_hwmod_class,
1096         .clkdm_name     = "l4per_clkdm",
1097         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1098         .main_clk       = "func_96m_fclk",
1099         .prcm = {
1100                 .omap4 = {
1101                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1102                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1103                         .modulemode   = MODULEMODE_SWCTRL,
1104                 },
1105         },
1106 };
1107
1108 /* i2c2 */
1109 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1110         .name           = "i2c2",
1111         .class          = &dra7xx_i2c_hwmod_class,
1112         .clkdm_name     = "l4per_clkdm",
1113         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1114         .main_clk       = "func_96m_fclk",
1115         .prcm = {
1116                 .omap4 = {
1117                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1118                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1119                         .modulemode   = MODULEMODE_SWCTRL,
1120                 },
1121         },
1122 };
1123
1124 /* i2c3 */
1125 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1126         .name           = "i2c3",
1127         .class          = &dra7xx_i2c_hwmod_class,
1128         .clkdm_name     = "l4per_clkdm",
1129         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1130         .main_clk       = "func_96m_fclk",
1131         .prcm = {
1132                 .omap4 = {
1133                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1134                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1135                         .modulemode   = MODULEMODE_SWCTRL,
1136                 },
1137         },
1138 };
1139
1140 /* i2c4 */
1141 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1142         .name           = "i2c4",
1143         .class          = &dra7xx_i2c_hwmod_class,
1144         .clkdm_name     = "l4per_clkdm",
1145         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1146         .main_clk       = "func_96m_fclk",
1147         .prcm = {
1148                 .omap4 = {
1149                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1150                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1151                         .modulemode   = MODULEMODE_SWCTRL,
1152                 },
1153         },
1154 };
1155
1156 /* i2c5 */
1157 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1158         .name           = "i2c5",
1159         .class          = &dra7xx_i2c_hwmod_class,
1160         .clkdm_name     = "ipu_clkdm",
1161         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1162         .main_clk       = "func_96m_fclk",
1163         .prcm = {
1164                 .omap4 = {
1165                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1166                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1167                         .modulemode   = MODULEMODE_SWCTRL,
1168                 },
1169         },
1170 };
1171
1172 /*
1173  * 'mailbox' class
1174  *
1175  */
1176
1177 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1178         .rev_offs       = 0x0000,
1179         .sysc_offs      = 0x0010,
1180         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1181                            SYSC_HAS_SOFTRESET),
1182         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1183         .sysc_fields    = &omap_hwmod_sysc_type2,
1184 };
1185
1186 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1187         .name   = "mailbox",
1188         .sysc   = &dra7xx_mailbox_sysc,
1189 };
1190
1191 /* mailbox1 */
1192 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1193         .name           = "mailbox1",
1194         .class          = &dra7xx_mailbox_hwmod_class,
1195         .clkdm_name     = "l4cfg_clkdm",
1196         .prcm = {
1197                 .omap4 = {
1198                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1199                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1200                 },
1201         },
1202 };
1203
1204 /* mailbox2 */
1205 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1206         .name           = "mailbox2",
1207         .class          = &dra7xx_mailbox_hwmod_class,
1208         .clkdm_name     = "l4cfg_clkdm",
1209         .prcm = {
1210                 .omap4 = {
1211                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1212                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1213                 },
1214         },
1215 };
1216
1217 /* mailbox3 */
1218 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1219         .name           = "mailbox3",
1220         .class          = &dra7xx_mailbox_hwmod_class,
1221         .clkdm_name     = "l4cfg_clkdm",
1222         .prcm = {
1223                 .omap4 = {
1224                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1225                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1226                 },
1227         },
1228 };
1229
1230 /* mailbox4 */
1231 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1232         .name           = "mailbox4",
1233         .class          = &dra7xx_mailbox_hwmod_class,
1234         .clkdm_name     = "l4cfg_clkdm",
1235         .prcm = {
1236                 .omap4 = {
1237                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1238                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1239                 },
1240         },
1241 };
1242
1243 /* mailbox5 */
1244 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1245         .name           = "mailbox5",
1246         .class          = &dra7xx_mailbox_hwmod_class,
1247         .clkdm_name     = "l4cfg_clkdm",
1248         .prcm = {
1249                 .omap4 = {
1250                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1251                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1252                 },
1253         },
1254 };
1255
1256 /* mailbox6 */
1257 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1258         .name           = "mailbox6",
1259         .class          = &dra7xx_mailbox_hwmod_class,
1260         .clkdm_name     = "l4cfg_clkdm",
1261         .prcm = {
1262                 .omap4 = {
1263                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1264                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1265                 },
1266         },
1267 };
1268
1269 /* mailbox7 */
1270 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1271         .name           = "mailbox7",
1272         .class          = &dra7xx_mailbox_hwmod_class,
1273         .clkdm_name     = "l4cfg_clkdm",
1274         .prcm = {
1275                 .omap4 = {
1276                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1277                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1278                 },
1279         },
1280 };
1281
1282 /* mailbox8 */
1283 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1284         .name           = "mailbox8",
1285         .class          = &dra7xx_mailbox_hwmod_class,
1286         .clkdm_name     = "l4cfg_clkdm",
1287         .prcm = {
1288                 .omap4 = {
1289                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1290                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1291                 },
1292         },
1293 };
1294
1295 /* mailbox9 */
1296 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1297         .name           = "mailbox9",
1298         .class          = &dra7xx_mailbox_hwmod_class,
1299         .clkdm_name     = "l4cfg_clkdm",
1300         .prcm = {
1301                 .omap4 = {
1302                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1303                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1304                 },
1305         },
1306 };
1307
1308 /* mailbox10 */
1309 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1310         .name           = "mailbox10",
1311         .class          = &dra7xx_mailbox_hwmod_class,
1312         .clkdm_name     = "l4cfg_clkdm",
1313         .prcm = {
1314                 .omap4 = {
1315                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1316                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1317                 },
1318         },
1319 };
1320
1321 /* mailbox11 */
1322 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1323         .name           = "mailbox11",
1324         .class          = &dra7xx_mailbox_hwmod_class,
1325         .clkdm_name     = "l4cfg_clkdm",
1326         .prcm = {
1327                 .omap4 = {
1328                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1329                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1330                 },
1331         },
1332 };
1333
1334 /* mailbox12 */
1335 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1336         .name           = "mailbox12",
1337         .class          = &dra7xx_mailbox_hwmod_class,
1338         .clkdm_name     = "l4cfg_clkdm",
1339         .prcm = {
1340                 .omap4 = {
1341                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1342                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1343                 },
1344         },
1345 };
1346
1347 /* mailbox13 */
1348 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1349         .name           = "mailbox13",
1350         .class          = &dra7xx_mailbox_hwmod_class,
1351         .clkdm_name     = "l4cfg_clkdm",
1352         .prcm = {
1353                 .omap4 = {
1354                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1355                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1356                 },
1357         },
1358 };
1359
1360 /*
1361  * 'mcspi' class
1362  *
1363  */
1364
1365 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1366         .rev_offs       = 0x0000,
1367         .sysc_offs      = 0x0010,
1368         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1369                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1370         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1371                            SIDLE_SMART_WKUP),
1372         .sysc_fields    = &omap_hwmod_sysc_type2,
1373 };
1374
1375 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1376         .name   = "mcspi",
1377         .sysc   = &dra7xx_mcspi_sysc,
1378 };
1379
1380 /* mcspi1 */
1381 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1382         .name           = "mcspi1",
1383         .class          = &dra7xx_mcspi_hwmod_class,
1384         .clkdm_name     = "l4per_clkdm",
1385         .main_clk       = "func_48m_fclk",
1386         .prcm = {
1387                 .omap4 = {
1388                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1389                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1390                         .modulemode   = MODULEMODE_SWCTRL,
1391                 },
1392         },
1393 };
1394
1395 /* mcspi2 */
1396 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1397         .name           = "mcspi2",
1398         .class          = &dra7xx_mcspi_hwmod_class,
1399         .clkdm_name     = "l4per_clkdm",
1400         .main_clk       = "func_48m_fclk",
1401         .prcm = {
1402                 .omap4 = {
1403                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1404                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1405                         .modulemode   = MODULEMODE_SWCTRL,
1406                 },
1407         },
1408 };
1409
1410 /* mcspi3 */
1411 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1412         .name           = "mcspi3",
1413         .class          = &dra7xx_mcspi_hwmod_class,
1414         .clkdm_name     = "l4per_clkdm",
1415         .main_clk       = "func_48m_fclk",
1416         .prcm = {
1417                 .omap4 = {
1418                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1419                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1420                         .modulemode   = MODULEMODE_SWCTRL,
1421                 },
1422         },
1423 };
1424
1425 /* mcspi4 */
1426 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1427         .name           = "mcspi4",
1428         .class          = &dra7xx_mcspi_hwmod_class,
1429         .clkdm_name     = "l4per_clkdm",
1430         .main_clk       = "func_48m_fclk",
1431         .prcm = {
1432                 .omap4 = {
1433                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1434                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1435                         .modulemode   = MODULEMODE_SWCTRL,
1436                 },
1437         },
1438 };
1439
1440 /*
1441  * 'mcasp' class
1442  *
1443  */
1444 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1445         .rev_offs       = 0,
1446         .sysc_offs      = 0x0004,
1447         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1448         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1449         .sysc_fields    = &omap_hwmod_sysc_type3,
1450 };
1451
1452 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1453         .name   = "mcasp",
1454         .sysc   = &dra7xx_mcasp_sysc,
1455 };
1456
1457 /* mcasp1 */
1458 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1459         { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1460         { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1461 };
1462
1463 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1464         .name           = "mcasp1",
1465         .class          = &dra7xx_mcasp_hwmod_class,
1466         .clkdm_name     = "ipu_clkdm",
1467         .main_clk       = "mcasp1_aux_gfclk_mux",
1468         .flags          = HWMOD_OPT_CLKS_NEEDED,
1469         .prcm = {
1470                 .omap4 = {
1471                         .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1472                         .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1473                         .modulemode   = MODULEMODE_SWCTRL,
1474                 },
1475         },
1476         .opt_clks       = mcasp1_opt_clks,
1477         .opt_clks_cnt   = ARRAY_SIZE(mcasp1_opt_clks),
1478 };
1479
1480 /* mcasp2 */
1481 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1482         { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1483         { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1484 };
1485
1486 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1487         .name           = "mcasp2",
1488         .class          = &dra7xx_mcasp_hwmod_class,
1489         .clkdm_name     = "l4per2_clkdm",
1490         .main_clk       = "mcasp2_aux_gfclk_mux",
1491         .flags          = HWMOD_OPT_CLKS_NEEDED,
1492         .prcm = {
1493                 .omap4 = {
1494                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1495                         .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1496                         .modulemode   = MODULEMODE_SWCTRL,
1497                 },
1498         },
1499         .opt_clks       = mcasp2_opt_clks,
1500         .opt_clks_cnt   = ARRAY_SIZE(mcasp2_opt_clks),
1501 };
1502
1503 /* mcasp3 */
1504 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1505         { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1506 };
1507
1508 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1509         .name           = "mcasp3",
1510         .class          = &dra7xx_mcasp_hwmod_class,
1511         .clkdm_name     = "l4per2_clkdm",
1512         .main_clk       = "mcasp3_aux_gfclk_mux",
1513         .flags          = HWMOD_OPT_CLKS_NEEDED,
1514         .prcm = {
1515                 .omap4 = {
1516                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1517                         .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1518                         .modulemode   = MODULEMODE_SWCTRL,
1519                 },
1520         },
1521         .opt_clks       = mcasp3_opt_clks,
1522         .opt_clks_cnt   = ARRAY_SIZE(mcasp3_opt_clks),
1523 };
1524
1525 /* mcasp4 */
1526 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1527         { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1528 };
1529
1530 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1531         .name           = "mcasp4",
1532         .class          = &dra7xx_mcasp_hwmod_class,
1533         .clkdm_name     = "l4per2_clkdm",
1534         .main_clk       = "mcasp4_aux_gfclk_mux",
1535         .flags          = HWMOD_OPT_CLKS_NEEDED,
1536         .prcm = {
1537                 .omap4 = {
1538                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1539                         .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1540                         .modulemode   = MODULEMODE_SWCTRL,
1541                 },
1542         },
1543         .opt_clks       = mcasp4_opt_clks,
1544         .opt_clks_cnt   = ARRAY_SIZE(mcasp4_opt_clks),
1545 };
1546
1547 /* mcasp5 */
1548 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1549         { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1550 };
1551
1552 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1553         .name           = "mcasp5",
1554         .class          = &dra7xx_mcasp_hwmod_class,
1555         .clkdm_name     = "l4per2_clkdm",
1556         .main_clk       = "mcasp5_aux_gfclk_mux",
1557         .flags          = HWMOD_OPT_CLKS_NEEDED,
1558         .prcm = {
1559                 .omap4 = {
1560                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1561                         .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1562                         .modulemode   = MODULEMODE_SWCTRL,
1563                 },
1564         },
1565         .opt_clks       = mcasp5_opt_clks,
1566         .opt_clks_cnt   = ARRAY_SIZE(mcasp5_opt_clks),
1567 };
1568
1569 /* mcasp6 */
1570 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1571         { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1572 };
1573
1574 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1575         .name           = "mcasp6",
1576         .class          = &dra7xx_mcasp_hwmod_class,
1577         .clkdm_name     = "l4per2_clkdm",
1578         .main_clk       = "mcasp6_aux_gfclk_mux",
1579         .flags          = HWMOD_OPT_CLKS_NEEDED,
1580         .prcm = {
1581                 .omap4 = {
1582                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1583                         .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1584                         .modulemode   = MODULEMODE_SWCTRL,
1585                 },
1586         },
1587         .opt_clks       = mcasp6_opt_clks,
1588         .opt_clks_cnt   = ARRAY_SIZE(mcasp6_opt_clks),
1589 };
1590
1591 /* mcasp7 */
1592 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1593         { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1594 };
1595
1596 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1597         .name           = "mcasp7",
1598         .class          = &dra7xx_mcasp_hwmod_class,
1599         .clkdm_name     = "l4per2_clkdm",
1600         .main_clk       = "mcasp7_aux_gfclk_mux",
1601         .flags          = HWMOD_OPT_CLKS_NEEDED,
1602         .prcm = {
1603                 .omap4 = {
1604                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1605                         .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1606                         .modulemode   = MODULEMODE_SWCTRL,
1607                 },
1608         },
1609         .opt_clks       = mcasp7_opt_clks,
1610         .opt_clks_cnt   = ARRAY_SIZE(mcasp7_opt_clks),
1611 };
1612
1613 /* mcasp8 */
1614 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1615         { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1616 };
1617
1618 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1619         .name           = "mcasp8",
1620         .class          = &dra7xx_mcasp_hwmod_class,
1621         .clkdm_name     = "l4per2_clkdm",
1622         .main_clk       = "mcasp8_aux_gfclk_mux",
1623         .flags          = HWMOD_OPT_CLKS_NEEDED,
1624         .prcm = {
1625                 .omap4 = {
1626                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1627                         .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1628                         .modulemode   = MODULEMODE_SWCTRL,
1629                 },
1630         },
1631         .opt_clks       = mcasp8_opt_clks,
1632         .opt_clks_cnt   = ARRAY_SIZE(mcasp8_opt_clks),
1633 };
1634
1635 /*
1636  * 'mmc' class
1637  *
1638  */
1639
1640 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1641         .rev_offs       = 0x0000,
1642         .sysc_offs      = 0x0010,
1643         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1644                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1645                            SYSC_HAS_SOFTRESET),
1646         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1647                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1648                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1649         .sysc_fields    = &omap_hwmod_sysc_type2,
1650 };
1651
1652 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1653         .name   = "mmc",
1654         .sysc   = &dra7xx_mmc_sysc,
1655 };
1656
1657 /* mmc1 */
1658 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1659         { .role = "clk32k", .clk = "mmc1_clk32k" },
1660 };
1661
1662 /* mmc1 dev_attr */
1663 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1664         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1665 };
1666
1667 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1668         .name           = "mmc1",
1669         .class          = &dra7xx_mmc_hwmod_class,
1670         .clkdm_name     = "l3init_clkdm",
1671         .main_clk       = "mmc1_fclk_div",
1672         .prcm = {
1673                 .omap4 = {
1674                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1675                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1676                         .modulemode   = MODULEMODE_SWCTRL,
1677                 },
1678         },
1679         .opt_clks       = mmc1_opt_clks,
1680         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1681         .dev_attr       = &mmc1_dev_attr,
1682 };
1683
1684 /* mmc2 */
1685 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1686         { .role = "clk32k", .clk = "mmc2_clk32k" },
1687 };
1688
1689 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1690         .name           = "mmc2",
1691         .class          = &dra7xx_mmc_hwmod_class,
1692         .clkdm_name     = "l3init_clkdm",
1693         .main_clk       = "mmc2_fclk_div",
1694         .prcm = {
1695                 .omap4 = {
1696                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1697                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1698                         .modulemode   = MODULEMODE_SWCTRL,
1699                 },
1700         },
1701         .opt_clks       = mmc2_opt_clks,
1702         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1703 };
1704
1705 /* mmc3 */
1706 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1707         { .role = "clk32k", .clk = "mmc3_clk32k" },
1708 };
1709
1710 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1711         .name           = "mmc3",
1712         .class          = &dra7xx_mmc_hwmod_class,
1713         .clkdm_name     = "l4per_clkdm",
1714         .main_clk       = "mmc3_gfclk_div",
1715         .prcm = {
1716                 .omap4 = {
1717                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1718                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1719                         .modulemode   = MODULEMODE_SWCTRL,
1720                 },
1721         },
1722         .opt_clks       = mmc3_opt_clks,
1723         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1724 };
1725
1726 /* mmc4 */
1727 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1728         { .role = "clk32k", .clk = "mmc4_clk32k" },
1729 };
1730
1731 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1732         .name           = "mmc4",
1733         .class          = &dra7xx_mmc_hwmod_class,
1734         .clkdm_name     = "l4per_clkdm",
1735         .main_clk       = "mmc4_gfclk_div",
1736         .prcm = {
1737                 .omap4 = {
1738                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1739                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1740                         .modulemode   = MODULEMODE_SWCTRL,
1741                 },
1742         },
1743         .opt_clks       = mmc4_opt_clks,
1744         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1745 };
1746
1747 /*
1748  * 'mpu' class
1749  *
1750  */
1751
1752 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1753         .name   = "mpu",
1754 };
1755
1756 /* mpu */
1757 static struct omap_hwmod dra7xx_mpu_hwmod = {
1758         .name           = "mpu",
1759         .class          = &dra7xx_mpu_hwmod_class,
1760         .clkdm_name     = "mpu_clkdm",
1761         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1762         .main_clk       = "dpll_mpu_m2_ck",
1763         .prcm = {
1764                 .omap4 = {
1765                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1766                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1767                 },
1768         },
1769 };
1770
1771 /*
1772  * 'ocp2scp' class
1773  *
1774  */
1775
1776 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1777         .rev_offs       = 0x0000,
1778         .sysc_offs      = 0x0010,
1779         .syss_offs      = 0x0014,
1780         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1781                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1782         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1783         .sysc_fields    = &omap_hwmod_sysc_type1,
1784 };
1785
1786 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1787         .name   = "ocp2scp",
1788         .sysc   = &dra7xx_ocp2scp_sysc,
1789 };
1790
1791 /* ocp2scp1 */
1792 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1793         .name           = "ocp2scp1",
1794         .class          = &dra7xx_ocp2scp_hwmod_class,
1795         .clkdm_name     = "l3init_clkdm",
1796         .main_clk       = "l4_root_clk_div",
1797         .prcm = {
1798                 .omap4 = {
1799                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1800                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1801                         .modulemode   = MODULEMODE_HWCTRL,
1802                 },
1803         },
1804 };
1805
1806 /* ocp2scp3 */
1807 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1808         .name           = "ocp2scp3",
1809         .class          = &dra7xx_ocp2scp_hwmod_class,
1810         .clkdm_name     = "l3init_clkdm",
1811         .main_clk       = "l4_root_clk_div",
1812         .prcm = {
1813                 .omap4 = {
1814                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1815                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1816                         .modulemode   = MODULEMODE_HWCTRL,
1817                 },
1818         },
1819 };
1820
1821 /*
1822  * 'PCIE' class
1823  *
1824  */
1825
1826 /*
1827  * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1828  * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1829  * associated with an IP automatically leaving the driver to handle that
1830  * by itself. This does not work for PCIeSS which needs the reset lines
1831  * deasserted for the driver to start accessing registers.
1832  *
1833  * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1834  * lines after asserting them.
1835  */
1836 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1837 {
1838         int i;
1839
1840         for (i = 0; i < oh->rst_lines_cnt; i++) {
1841                 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1842                 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1843         }
1844
1845         return 0;
1846 }
1847
1848 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1849         .name   = "pcie",
1850         .reset  = dra7xx_pciess_reset,
1851 };
1852
1853 /* pcie1 */
1854 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1855         { .name = "pcie", .rst_shift = 0 },
1856 };
1857
1858 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1859         .name           = "pcie1",
1860         .class          = &dra7xx_pciess_hwmod_class,
1861         .clkdm_name     = "pcie_clkdm",
1862         .rst_lines      = dra7xx_pciess1_resets,
1863         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess1_resets),
1864         .main_clk       = "l4_root_clk_div",
1865         .prcm = {
1866                 .omap4 = {
1867                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1868                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1869                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1870                         .modulemode   = MODULEMODE_SWCTRL,
1871                 },
1872         },
1873 };
1874
1875 /* pcie2 */
1876 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1877         { .name = "pcie", .rst_shift = 1 },
1878 };
1879
1880 /* pcie2 */
1881 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1882         .name           = "pcie2",
1883         .class          = &dra7xx_pciess_hwmod_class,
1884         .clkdm_name     = "pcie_clkdm",
1885         .rst_lines      = dra7xx_pciess2_resets,
1886         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess2_resets),
1887         .main_clk       = "l4_root_clk_div",
1888         .prcm = {
1889                 .omap4 = {
1890                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1891                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1892                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1893                         .modulemode   = MODULEMODE_SWCTRL,
1894                 },
1895         },
1896 };
1897
1898 /*
1899  * 'qspi' class
1900  *
1901  */
1902
1903 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1904         .rev_offs       = 0,
1905         .sysc_offs      = 0x0010,
1906         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1907         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1908                            SIDLE_SMART_WKUP),
1909         .sysc_fields    = &omap_hwmod_sysc_type2,
1910 };
1911
1912 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1913         .name   = "qspi",
1914         .sysc   = &dra7xx_qspi_sysc,
1915 };
1916
1917 /* qspi */
1918 static struct omap_hwmod dra7xx_qspi_hwmod = {
1919         .name           = "qspi",
1920         .class          = &dra7xx_qspi_hwmod_class,
1921         .clkdm_name     = "l4per2_clkdm",
1922         .main_clk       = "qspi_gfclk_div",
1923         .prcm = {
1924                 .omap4 = {
1925                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1926                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1927                         .modulemode   = MODULEMODE_SWCTRL,
1928                 },
1929         },
1930 };
1931
1932 /*
1933  * 'rtcss' class
1934  *
1935  */
1936 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1937         .rev_offs       = 0x0074,
1938         .sysc_offs      = 0x0078,
1939         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1940         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1941                            SIDLE_SMART_WKUP),
1942         .sysc_fields    = &omap_hwmod_sysc_type3,
1943 };
1944
1945 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1946         .name   = "rtcss",
1947         .sysc   = &dra7xx_rtcss_sysc,
1948         .unlock = &omap_hwmod_rtc_unlock,
1949         .lock   = &omap_hwmod_rtc_lock,
1950 };
1951
1952 /* rtcss */
1953 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1954         .name           = "rtcss",
1955         .class          = &dra7xx_rtcss_hwmod_class,
1956         .clkdm_name     = "rtc_clkdm",
1957         .main_clk       = "sys_32k_ck",
1958         .prcm = {
1959                 .omap4 = {
1960                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1961                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1962                         .modulemode   = MODULEMODE_SWCTRL,
1963                 },
1964         },
1965 };
1966
1967 /*
1968  * 'sata' class
1969  *
1970  */
1971
1972 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1973         .rev_offs       = 0x00fc,
1974         .sysc_offs      = 0x0000,
1975         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1976         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1977                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1978                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1979         .sysc_fields    = &omap_hwmod_sysc_type2,
1980 };
1981
1982 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1983         .name   = "sata",
1984         .sysc   = &dra7xx_sata_sysc,
1985 };
1986
1987 /* sata */
1988
1989 static struct omap_hwmod dra7xx_sata_hwmod = {
1990         .name           = "sata",
1991         .class          = &dra7xx_sata_hwmod_class,
1992         .clkdm_name     = "l3init_clkdm",
1993         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1994         .main_clk       = "func_48m_fclk",
1995         .mpu_rt_idx     = 1,
1996         .prcm = {
1997                 .omap4 = {
1998                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1999                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2000                         .modulemode   = MODULEMODE_SWCTRL,
2001                 },
2002         },
2003 };
2004
2005 /*
2006  * 'smartreflex' class
2007  *
2008  */
2009
2010 /* The IP is not compliant to type1 / type2 scheme */
2011 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2012         .rev_offs       = -ENODEV,
2013         .sysc_offs      = 0x0038,
2014         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2015         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2016                            SIDLE_SMART_WKUP),
2017         .sysc_fields    = &omap36xx_sr_sysc_fields,
2018 };
2019
2020 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2021         .name   = "smartreflex",
2022         .sysc   = &dra7xx_smartreflex_sysc,
2023         .rev    = 2,
2024 };
2025
2026 /* smartreflex_core */
2027 /* smartreflex_core dev_attr */
2028 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2029         .sensor_voltdm_name     = "core",
2030 };
2031
2032 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2033         .name           = "smartreflex_core",
2034         .class          = &dra7xx_smartreflex_hwmod_class,
2035         .clkdm_name     = "coreaon_clkdm",
2036         .main_clk       = "wkupaon_iclk_mux",
2037         .prcm = {
2038                 .omap4 = {
2039                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2040                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2041                         .modulemode   = MODULEMODE_SWCTRL,
2042                 },
2043         },
2044         .dev_attr       = &smartreflex_core_dev_attr,
2045 };
2046
2047 /* smartreflex_mpu */
2048 /* smartreflex_mpu dev_attr */
2049 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2050         .sensor_voltdm_name     = "mpu",
2051 };
2052
2053 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2054         .name           = "smartreflex_mpu",
2055         .class          = &dra7xx_smartreflex_hwmod_class,
2056         .clkdm_name     = "coreaon_clkdm",
2057         .main_clk       = "wkupaon_iclk_mux",
2058         .prcm = {
2059                 .omap4 = {
2060                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2061                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2062                         .modulemode   = MODULEMODE_SWCTRL,
2063                 },
2064         },
2065         .dev_attr       = &smartreflex_mpu_dev_attr,
2066 };
2067
2068 /*
2069  * 'spinlock' class
2070  *
2071  */
2072
2073 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2074         .rev_offs       = 0x0000,
2075         .sysc_offs      = 0x0010,
2076         .syss_offs      = 0x0014,
2077         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2078                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2079                            SYSS_HAS_RESET_STATUS),
2080         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2081         .sysc_fields    = &omap_hwmod_sysc_type1,
2082 };
2083
2084 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2085         .name   = "spinlock",
2086         .sysc   = &dra7xx_spinlock_sysc,
2087 };
2088
2089 /* spinlock */
2090 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2091         .name           = "spinlock",
2092         .class          = &dra7xx_spinlock_hwmod_class,
2093         .clkdm_name     = "l4cfg_clkdm",
2094         .main_clk       = "l3_iclk_div",
2095         .prcm = {
2096                 .omap4 = {
2097                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2098                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2099                 },
2100         },
2101 };
2102
2103 /*
2104  * 'timer' class
2105  *
2106  * This class contains several variants: ['timer_1ms', 'timer_secure',
2107  * 'timer']
2108  */
2109
2110 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2111         .rev_offs       = 0x0000,
2112         .sysc_offs      = 0x0010,
2113         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2114                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2115         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2116                            SIDLE_SMART_WKUP),
2117         .sysc_fields    = &omap_hwmod_sysc_type2,
2118 };
2119
2120 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2121         .name   = "timer",
2122         .sysc   = &dra7xx_timer_1ms_sysc,
2123 };
2124
2125 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2126         .rev_offs       = 0x0000,
2127         .sysc_offs      = 0x0010,
2128         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2129                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2130         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2131                            SIDLE_SMART_WKUP),
2132         .sysc_fields    = &omap_hwmod_sysc_type2,
2133 };
2134
2135 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2136         .name   = "timer",
2137         .sysc   = &dra7xx_timer_sysc,
2138 };
2139
2140 /* timer1 */
2141 static struct omap_hwmod dra7xx_timer1_hwmod = {
2142         .name           = "timer1",
2143         .class          = &dra7xx_timer_1ms_hwmod_class,
2144         .clkdm_name     = "wkupaon_clkdm",
2145         .main_clk       = "timer1_gfclk_mux",
2146         .prcm = {
2147                 .omap4 = {
2148                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2149                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2150                         .modulemode   = MODULEMODE_SWCTRL,
2151                 },
2152         },
2153 };
2154
2155 /* timer2 */
2156 static struct omap_hwmod dra7xx_timer2_hwmod = {
2157         .name           = "timer2",
2158         .class          = &dra7xx_timer_1ms_hwmod_class,
2159         .clkdm_name     = "l4per_clkdm",
2160         .main_clk       = "timer2_gfclk_mux",
2161         .prcm = {
2162                 .omap4 = {
2163                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2164                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2165                         .modulemode   = MODULEMODE_SWCTRL,
2166                 },
2167         },
2168 };
2169
2170 /* timer3 */
2171 static struct omap_hwmod dra7xx_timer3_hwmod = {
2172         .name           = "timer3",
2173         .class          = &dra7xx_timer_hwmod_class,
2174         .clkdm_name     = "l4per_clkdm",
2175         .main_clk       = "timer3_gfclk_mux",
2176         .prcm = {
2177                 .omap4 = {
2178                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2179                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2180                         .modulemode   = MODULEMODE_SWCTRL,
2181                 },
2182         },
2183 };
2184
2185 /* timer4 */
2186 static struct omap_hwmod dra7xx_timer4_hwmod = {
2187         .name           = "timer4",
2188         .class          = &dra7xx_timer_hwmod_class,
2189         .clkdm_name     = "l4per_clkdm",
2190         .main_clk       = "timer4_gfclk_mux",
2191         .prcm = {
2192                 .omap4 = {
2193                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2194                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2195                         .modulemode   = MODULEMODE_SWCTRL,
2196                 },
2197         },
2198 };
2199
2200 /* timer5 */
2201 static struct omap_hwmod dra7xx_timer5_hwmod = {
2202         .name           = "timer5",
2203         .class          = &dra7xx_timer_hwmod_class,
2204         .clkdm_name     = "ipu_clkdm",
2205         .main_clk       = "timer5_gfclk_mux",
2206         .prcm = {
2207                 .omap4 = {
2208                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2209                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2210                         .modulemode   = MODULEMODE_SWCTRL,
2211                 },
2212         },
2213 };
2214
2215 /* timer6 */
2216 static struct omap_hwmod dra7xx_timer6_hwmod = {
2217         .name           = "timer6",
2218         .class          = &dra7xx_timer_hwmod_class,
2219         .clkdm_name     = "ipu_clkdm",
2220         .main_clk       = "timer6_gfclk_mux",
2221         .prcm = {
2222                 .omap4 = {
2223                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2224                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2225                         .modulemode   = MODULEMODE_SWCTRL,
2226                 },
2227         },
2228 };
2229
2230 /* timer7 */
2231 static struct omap_hwmod dra7xx_timer7_hwmod = {
2232         .name           = "timer7",
2233         .class          = &dra7xx_timer_hwmod_class,
2234         .clkdm_name     = "ipu_clkdm",
2235         .main_clk       = "timer7_gfclk_mux",
2236         .prcm = {
2237                 .omap4 = {
2238                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2239                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2240                         .modulemode   = MODULEMODE_SWCTRL,
2241                 },
2242         },
2243 };
2244
2245 /* timer8 */
2246 static struct omap_hwmod dra7xx_timer8_hwmod = {
2247         .name           = "timer8",
2248         .class          = &dra7xx_timer_hwmod_class,
2249         .clkdm_name     = "ipu_clkdm",
2250         .main_clk       = "timer8_gfclk_mux",
2251         .prcm = {
2252                 .omap4 = {
2253                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2254                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2255                         .modulemode   = MODULEMODE_SWCTRL,
2256                 },
2257         },
2258 };
2259
2260 /* timer9 */
2261 static struct omap_hwmod dra7xx_timer9_hwmod = {
2262         .name           = "timer9",
2263         .class          = &dra7xx_timer_hwmod_class,
2264         .clkdm_name     = "l4per_clkdm",
2265         .main_clk       = "timer9_gfclk_mux",
2266         .prcm = {
2267                 .omap4 = {
2268                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2269                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2270                         .modulemode   = MODULEMODE_SWCTRL,
2271                 },
2272         },
2273 };
2274
2275 /* timer10 */
2276 static struct omap_hwmod dra7xx_timer10_hwmod = {
2277         .name           = "timer10",
2278         .class          = &dra7xx_timer_1ms_hwmod_class,
2279         .clkdm_name     = "l4per_clkdm",
2280         .main_clk       = "timer10_gfclk_mux",
2281         .prcm = {
2282                 .omap4 = {
2283                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2284                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2285                         .modulemode   = MODULEMODE_SWCTRL,
2286                 },
2287         },
2288 };
2289
2290 /* timer11 */
2291 static struct omap_hwmod dra7xx_timer11_hwmod = {
2292         .name           = "timer11",
2293         .class          = &dra7xx_timer_hwmod_class,
2294         .clkdm_name     = "l4per_clkdm",
2295         .main_clk       = "timer11_gfclk_mux",
2296         .prcm = {
2297                 .omap4 = {
2298                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2299                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2300                         .modulemode   = MODULEMODE_SWCTRL,
2301                 },
2302         },
2303 };
2304
2305 /* timer12 */
2306 static struct omap_hwmod dra7xx_timer12_hwmod = {
2307         .name           = "timer12",
2308         .class          = &dra7xx_timer_hwmod_class,
2309         .clkdm_name     = "wkupaon_clkdm",
2310         .main_clk       = "secure_32k_clk_src_ck",
2311         .prcm = {
2312                 .omap4 = {
2313                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2314                         .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2315                 },
2316         },
2317 };
2318
2319 /* timer13 */
2320 static struct omap_hwmod dra7xx_timer13_hwmod = {
2321         .name           = "timer13",
2322         .class          = &dra7xx_timer_hwmod_class,
2323         .clkdm_name     = "l4per3_clkdm",
2324         .main_clk       = "timer13_gfclk_mux",
2325         .prcm = {
2326                 .omap4 = {
2327                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2328                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2329                         .modulemode   = MODULEMODE_SWCTRL,
2330                 },
2331         },
2332 };
2333
2334 /* timer14 */
2335 static struct omap_hwmod dra7xx_timer14_hwmod = {
2336         .name           = "timer14",
2337         .class          = &dra7xx_timer_hwmod_class,
2338         .clkdm_name     = "l4per3_clkdm",
2339         .main_clk       = "timer14_gfclk_mux",
2340         .prcm = {
2341                 .omap4 = {
2342                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2343                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2344                         .modulemode   = MODULEMODE_SWCTRL,
2345                 },
2346         },
2347 };
2348
2349 /* timer15 */
2350 static struct omap_hwmod dra7xx_timer15_hwmod = {
2351         .name           = "timer15",
2352         .class          = &dra7xx_timer_hwmod_class,
2353         .clkdm_name     = "l4per3_clkdm",
2354         .main_clk       = "timer15_gfclk_mux",
2355         .prcm = {
2356                 .omap4 = {
2357                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2358                         .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2359                         .modulemode   = MODULEMODE_SWCTRL,
2360                 },
2361         },
2362 };
2363
2364 /* timer16 */
2365 static struct omap_hwmod dra7xx_timer16_hwmod = {
2366         .name           = "timer16",
2367         .class          = &dra7xx_timer_hwmod_class,
2368         .clkdm_name     = "l4per3_clkdm",
2369         .main_clk       = "timer16_gfclk_mux",
2370         .prcm = {
2371                 .omap4 = {
2372                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2373                         .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2374                         .modulemode   = MODULEMODE_SWCTRL,
2375                 },
2376         },
2377 };
2378
2379 /*
2380  * 'uart' class
2381  *
2382  */
2383
2384 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2385         .rev_offs       = 0x0050,
2386         .sysc_offs      = 0x0054,
2387         .syss_offs      = 0x0058,
2388         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2389                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2390                            SYSS_HAS_RESET_STATUS),
2391         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2392                            SIDLE_SMART_WKUP),
2393         .sysc_fields    = &omap_hwmod_sysc_type1,
2394 };
2395
2396 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2397         .name   = "uart",
2398         .sysc   = &dra7xx_uart_sysc,
2399 };
2400
2401 /* uart1 */
2402 static struct omap_hwmod dra7xx_uart1_hwmod = {
2403         .name           = "uart1",
2404         .class          = &dra7xx_uart_hwmod_class,
2405         .clkdm_name     = "l4per_clkdm",
2406         .main_clk       = "uart1_gfclk_mux",
2407         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2408         .prcm = {
2409                 .omap4 = {
2410                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2411                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2412                         .modulemode   = MODULEMODE_SWCTRL,
2413                 },
2414         },
2415 };
2416
2417 /* uart2 */
2418 static struct omap_hwmod dra7xx_uart2_hwmod = {
2419         .name           = "uart2",
2420         .class          = &dra7xx_uart_hwmod_class,
2421         .clkdm_name     = "l4per_clkdm",
2422         .main_clk       = "uart2_gfclk_mux",
2423         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2424         .prcm = {
2425                 .omap4 = {
2426                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2427                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2428                         .modulemode   = MODULEMODE_SWCTRL,
2429                 },
2430         },
2431 };
2432
2433 /* uart3 */
2434 static struct omap_hwmod dra7xx_uart3_hwmod = {
2435         .name           = "uart3",
2436         .class          = &dra7xx_uart_hwmod_class,
2437         .clkdm_name     = "l4per_clkdm",
2438         .main_clk       = "uart3_gfclk_mux",
2439         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2440         .prcm = {
2441                 .omap4 = {
2442                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2443                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2444                         .modulemode   = MODULEMODE_SWCTRL,
2445                 },
2446         },
2447 };
2448
2449 /* uart4 */
2450 static struct omap_hwmod dra7xx_uart4_hwmod = {
2451         .name           = "uart4",
2452         .class          = &dra7xx_uart_hwmod_class,
2453         .clkdm_name     = "l4per_clkdm",
2454         .main_clk       = "uart4_gfclk_mux",
2455         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2456         .prcm = {
2457                 .omap4 = {
2458                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2459                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2460                         .modulemode   = MODULEMODE_SWCTRL,
2461                 },
2462         },
2463 };
2464
2465 /* uart5 */
2466 static struct omap_hwmod dra7xx_uart5_hwmod = {
2467         .name           = "uart5",
2468         .class          = &dra7xx_uart_hwmod_class,
2469         .clkdm_name     = "l4per_clkdm",
2470         .main_clk       = "uart5_gfclk_mux",
2471         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2472         .prcm = {
2473                 .omap4 = {
2474                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2475                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2476                         .modulemode   = MODULEMODE_SWCTRL,
2477                 },
2478         },
2479 };
2480
2481 /* uart6 */
2482 static struct omap_hwmod dra7xx_uart6_hwmod = {
2483         .name           = "uart6",
2484         .class          = &dra7xx_uart_hwmod_class,
2485         .clkdm_name     = "ipu_clkdm",
2486         .main_clk       = "uart6_gfclk_mux",
2487         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2488         .prcm = {
2489                 .omap4 = {
2490                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2491                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2492                         .modulemode   = MODULEMODE_SWCTRL,
2493                 },
2494         },
2495 };
2496
2497 /* uart7 */
2498 static struct omap_hwmod dra7xx_uart7_hwmod = {
2499         .name           = "uart7",
2500         .class          = &dra7xx_uart_hwmod_class,
2501         .clkdm_name     = "l4per2_clkdm",
2502         .main_clk       = "uart7_gfclk_mux",
2503         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2504         .prcm = {
2505                 .omap4 = {
2506                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2507                         .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2508                         .modulemode   = MODULEMODE_SWCTRL,
2509                 },
2510         },
2511 };
2512
2513 /* uart8 */
2514 static struct omap_hwmod dra7xx_uart8_hwmod = {
2515         .name           = "uart8",
2516         .class          = &dra7xx_uart_hwmod_class,
2517         .clkdm_name     = "l4per2_clkdm",
2518         .main_clk       = "uart8_gfclk_mux",
2519         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2520         .prcm = {
2521                 .omap4 = {
2522                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2523                         .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2524                         .modulemode   = MODULEMODE_SWCTRL,
2525                 },
2526         },
2527 };
2528
2529 /* uart9 */
2530 static struct omap_hwmod dra7xx_uart9_hwmod = {
2531         .name           = "uart9",
2532         .class          = &dra7xx_uart_hwmod_class,
2533         .clkdm_name     = "l4per2_clkdm",
2534         .main_clk       = "uart9_gfclk_mux",
2535         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2536         .prcm = {
2537                 .omap4 = {
2538                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2539                         .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2540                         .modulemode   = MODULEMODE_SWCTRL,
2541                 },
2542         },
2543 };
2544
2545 /* uart10 */
2546 static struct omap_hwmod dra7xx_uart10_hwmod = {
2547         .name           = "uart10",
2548         .class          = &dra7xx_uart_hwmod_class,
2549         .clkdm_name     = "wkupaon_clkdm",
2550         .main_clk       = "uart10_gfclk_mux",
2551         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2552         .prcm = {
2553                 .omap4 = {
2554                         .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2555                         .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2556                         .modulemode   = MODULEMODE_SWCTRL,
2557                 },
2558         },
2559 };
2560
2561 /* DES (the 'P' (public) device) */
2562 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2563         .rev_offs       = 0x0030,
2564         .sysc_offs      = 0x0034,
2565         .syss_offs      = 0x0038,
2566         .sysc_flags     = SYSS_HAS_RESET_STATUS,
2567 };
2568
2569 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2570         .name   = "des",
2571         .sysc   = &dra7xx_des_sysc,
2572 };
2573
2574 /* DES */
2575 static struct omap_hwmod dra7xx_des_hwmod = {
2576         .name           = "des",
2577         .class          = &dra7xx_des_hwmod_class,
2578         .clkdm_name     = "l4sec_clkdm",
2579         .main_clk       = "l3_iclk_div",
2580         .prcm = {
2581                 .omap4 = {
2582                         .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2583                         .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2584                         .modulemode   = MODULEMODE_HWCTRL,
2585                 },
2586         },
2587 };
2588
2589 /* rng */
2590 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2591         .rev_offs       = 0x1fe0,
2592         .sysc_offs      = 0x1fe4,
2593         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2594         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
2595         .sysc_fields    = &omap_hwmod_sysc_type1,
2596 };
2597
2598 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2599         .name           = "rng",
2600         .sysc           = &dra7xx_rng_sysc,
2601 };
2602
2603 static struct omap_hwmod dra7xx_rng_hwmod = {
2604         .name           = "rng",
2605         .class          = &dra7xx_rng_hwmod_class,
2606         .flags          = HWMOD_SWSUP_SIDLE,
2607         .clkdm_name     = "l4sec_clkdm",
2608         .prcm = {
2609                 .omap4 = {
2610                         .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2611                         .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2612                         .modulemode   = MODULEMODE_HWCTRL,
2613                 },
2614         },
2615 };
2616
2617 /*
2618  * 'usb_otg_ss' class
2619  *
2620  */
2621
2622 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2623         .rev_offs       = 0x0000,
2624         .sysc_offs      = 0x0010,
2625         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2626                            SYSC_HAS_SIDLEMODE),
2627         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2628                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2629                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2630         .sysc_fields    = &omap_hwmod_sysc_type2,
2631 };
2632
2633 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2634         .name   = "usb_otg_ss",
2635         .sysc   = &dra7xx_usb_otg_ss_sysc,
2636 };
2637
2638 /* usb_otg_ss1 */
2639 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2640         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2641 };
2642
2643 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2644         .name           = "usb_otg_ss1",
2645         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2646         .clkdm_name     = "l3init_clkdm",
2647         .main_clk       = "dpll_core_h13x2_ck",
2648         .flags          = HWMOD_CLKDM_NOAUTO,
2649         .prcm = {
2650                 .omap4 = {
2651                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2652                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2653                         .modulemode   = MODULEMODE_HWCTRL,
2654                 },
2655         },
2656         .opt_clks       = usb_otg_ss1_opt_clks,
2657         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2658 };
2659
2660 /* usb_otg_ss2 */
2661 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2662         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2663 };
2664
2665 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2666         .name           = "usb_otg_ss2",
2667         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2668         .clkdm_name     = "l3init_clkdm",
2669         .main_clk       = "dpll_core_h13x2_ck",
2670         .flags          = HWMOD_CLKDM_NOAUTO,
2671         .prcm = {
2672                 .omap4 = {
2673                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2674                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2675                         .modulemode   = MODULEMODE_HWCTRL,
2676                 },
2677         },
2678         .opt_clks       = usb_otg_ss2_opt_clks,
2679         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2680 };
2681
2682 /* usb_otg_ss3 */
2683 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2684         .name           = "usb_otg_ss3",
2685         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2686         .clkdm_name     = "l3init_clkdm",
2687         .main_clk       = "dpll_core_h13x2_ck",
2688         .prcm = {
2689                 .omap4 = {
2690                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2691                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2692                         .modulemode   = MODULEMODE_HWCTRL,
2693                 },
2694         },
2695 };
2696
2697 /* usb_otg_ss4 */
2698 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2699         .name           = "usb_otg_ss4",
2700         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2701         .clkdm_name     = "l3init_clkdm",
2702         .main_clk       = "dpll_core_h13x2_ck",
2703         .prcm = {
2704                 .omap4 = {
2705                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2706                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2707                         .modulemode   = MODULEMODE_HWCTRL,
2708                 },
2709         },
2710 };
2711
2712 /*
2713  * 'vcp' class
2714  *
2715  */
2716
2717 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2718         .name   = "vcp",
2719 };
2720
2721 /* vcp1 */
2722 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2723         .name           = "vcp1",
2724         .class          = &dra7xx_vcp_hwmod_class,
2725         .clkdm_name     = "l3main1_clkdm",
2726         .main_clk       = "l3_iclk_div",
2727         .prcm = {
2728                 .omap4 = {
2729                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2730                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2731                 },
2732         },
2733 };
2734
2735 /* vcp2 */
2736 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2737         .name           = "vcp2",
2738         .class          = &dra7xx_vcp_hwmod_class,
2739         .clkdm_name     = "l3main1_clkdm",
2740         .main_clk       = "l3_iclk_div",
2741         .prcm = {
2742                 .omap4 = {
2743                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2744                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2745                 },
2746         },
2747 };
2748
2749 /*
2750  * 'wd_timer' class
2751  *
2752  */
2753
2754 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2755         .rev_offs       = 0x0000,
2756         .sysc_offs      = 0x0010,
2757         .syss_offs      = 0x0014,
2758         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2759                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2760         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2761                            SIDLE_SMART_WKUP),
2762         .sysc_fields    = &omap_hwmod_sysc_type1,
2763 };
2764
2765 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2766         .name           = "wd_timer",
2767         .sysc           = &dra7xx_wd_timer_sysc,
2768         .pre_shutdown   = &omap2_wd_timer_disable,
2769         .reset          = &omap2_wd_timer_reset,
2770 };
2771
2772 /* wd_timer2 */
2773 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2774         .name           = "wd_timer2",
2775         .class          = &dra7xx_wd_timer_hwmod_class,
2776         .clkdm_name     = "wkupaon_clkdm",
2777         .main_clk       = "sys_32k_ck",
2778         .prcm = {
2779                 .omap4 = {
2780                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2781                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2782                         .modulemode   = MODULEMODE_SWCTRL,
2783                 },
2784         },
2785 };
2786
2787
2788 /*
2789  * Interfaces
2790  */
2791
2792 /* l3_main_1 -> dmm */
2793 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2794         .master         = &dra7xx_l3_main_1_hwmod,
2795         .slave          = &dra7xx_dmm_hwmod,
2796         .clk            = "l3_iclk_div",
2797         .user           = OCP_USER_SDMA,
2798 };
2799
2800 /* l3_main_2 -> l3_instr */
2801 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2802         .master         = &dra7xx_l3_main_2_hwmod,
2803         .slave          = &dra7xx_l3_instr_hwmod,
2804         .clk            = "l3_iclk_div",
2805         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2806 };
2807
2808 /* l4_cfg -> l3_main_1 */
2809 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2810         .master         = &dra7xx_l4_cfg_hwmod,
2811         .slave          = &dra7xx_l3_main_1_hwmod,
2812         .clk            = "l3_iclk_div",
2813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2814 };
2815
2816 /* mpu -> l3_main_1 */
2817 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2818         .master         = &dra7xx_mpu_hwmod,
2819         .slave          = &dra7xx_l3_main_1_hwmod,
2820         .clk            = "l3_iclk_div",
2821         .user           = OCP_USER_MPU,
2822 };
2823
2824 /* l3_main_1 -> l3_main_2 */
2825 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2826         .master         = &dra7xx_l3_main_1_hwmod,
2827         .slave          = &dra7xx_l3_main_2_hwmod,
2828         .clk            = "l3_iclk_div",
2829         .user           = OCP_USER_MPU,
2830 };
2831
2832 /* l4_cfg -> l3_main_2 */
2833 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2834         .master         = &dra7xx_l4_cfg_hwmod,
2835         .slave          = &dra7xx_l3_main_2_hwmod,
2836         .clk            = "l3_iclk_div",
2837         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2838 };
2839
2840 /* l3_main_1 -> l4_cfg */
2841 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2842         .master         = &dra7xx_l3_main_1_hwmod,
2843         .slave          = &dra7xx_l4_cfg_hwmod,
2844         .clk            = "l3_iclk_div",
2845         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2846 };
2847
2848 /* l3_main_1 -> l4_per1 */
2849 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2850         .master         = &dra7xx_l3_main_1_hwmod,
2851         .slave          = &dra7xx_l4_per1_hwmod,
2852         .clk            = "l3_iclk_div",
2853         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2854 };
2855
2856 /* l3_main_1 -> l4_per2 */
2857 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2858         .master         = &dra7xx_l3_main_1_hwmod,
2859         .slave          = &dra7xx_l4_per2_hwmod,
2860         .clk            = "l3_iclk_div",
2861         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2862 };
2863
2864 /* l3_main_1 -> l4_per3 */
2865 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2866         .master         = &dra7xx_l3_main_1_hwmod,
2867         .slave          = &dra7xx_l4_per3_hwmod,
2868         .clk            = "l3_iclk_div",
2869         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2870 };
2871
2872 /* l3_main_1 -> l4_wkup */
2873 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2874         .master         = &dra7xx_l3_main_1_hwmod,
2875         .slave          = &dra7xx_l4_wkup_hwmod,
2876         .clk            = "wkupaon_iclk_mux",
2877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2878 };
2879
2880 /* l4_per2 -> atl */
2881 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2882         .master         = &dra7xx_l4_per2_hwmod,
2883         .slave          = &dra7xx_atl_hwmod,
2884         .clk            = "l3_iclk_div",
2885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2886 };
2887
2888 /* l3_main_1 -> bb2d */
2889 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2890         .master         = &dra7xx_l3_main_1_hwmod,
2891         .slave          = &dra7xx_bb2d_hwmod,
2892         .clk            = "l3_iclk_div",
2893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2894 };
2895
2896 /* l4_wkup -> counter_32k */
2897 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2898         .master         = &dra7xx_l4_wkup_hwmod,
2899         .slave          = &dra7xx_counter_32k_hwmod,
2900         .clk            = "wkupaon_iclk_mux",
2901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2902 };
2903
2904 /* l4_wkup -> ctrl_module_wkup */
2905 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2906         .master         = &dra7xx_l4_wkup_hwmod,
2907         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
2908         .clk            = "wkupaon_iclk_mux",
2909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2910 };
2911
2912 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2913         .master         = &dra7xx_l4_per2_hwmod,
2914         .slave          = &dra7xx_gmac_hwmod,
2915         .clk            = "dpll_gmac_ck",
2916         .user           = OCP_USER_MPU,
2917 };
2918
2919 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2920         .master         = &dra7xx_gmac_hwmod,
2921         .slave          = &dra7xx_mdio_hwmod,
2922         .user           = OCP_USER_MPU,
2923 };
2924
2925 /* l4_wkup -> dcan1 */
2926 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2927         .master         = &dra7xx_l4_wkup_hwmod,
2928         .slave          = &dra7xx_dcan1_hwmod,
2929         .clk            = "wkupaon_iclk_mux",
2930         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2931 };
2932
2933 /* l4_per2 -> dcan2 */
2934 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2935         .master         = &dra7xx_l4_per2_hwmod,
2936         .slave          = &dra7xx_dcan2_hwmod,
2937         .clk            = "l3_iclk_div",
2938         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2939 };
2940
2941 /* l4_cfg -> dma_system */
2942 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2943         .master         = &dra7xx_l4_cfg_hwmod,
2944         .slave          = &dra7xx_dma_system_hwmod,
2945         .clk            = "l3_iclk_div",
2946         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2947 };
2948
2949 /* l3_main_1 -> tpcc */
2950 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2951         .master         = &dra7xx_l3_main_1_hwmod,
2952         .slave          = &dra7xx_tpcc_hwmod,
2953         .clk            = "l3_iclk_div",
2954         .user           = OCP_USER_MPU,
2955 };
2956
2957 /* l3_main_1 -> tptc0 */
2958 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
2959         .master         = &dra7xx_l3_main_1_hwmod,
2960         .slave          = &dra7xx_tptc0_hwmod,
2961         .clk            = "l3_iclk_div",
2962         .user           = OCP_USER_MPU,
2963 };
2964
2965 /* l3_main_1 -> tptc1 */
2966 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
2967         .master         = &dra7xx_l3_main_1_hwmod,
2968         .slave          = &dra7xx_tptc1_hwmod,
2969         .clk            = "l3_iclk_div",
2970         .user           = OCP_USER_MPU,
2971 };
2972
2973 /* l3_main_1 -> dss */
2974 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2975         .master         = &dra7xx_l3_main_1_hwmod,
2976         .slave          = &dra7xx_dss_hwmod,
2977         .clk            = "l3_iclk_div",
2978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2979 };
2980
2981 /* l3_main_1 -> dispc */
2982 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2983         .master         = &dra7xx_l3_main_1_hwmod,
2984         .slave          = &dra7xx_dss_dispc_hwmod,
2985         .clk            = "l3_iclk_div",
2986         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2987 };
2988
2989 /* l3_main_1 -> dispc */
2990 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2991         .master         = &dra7xx_l3_main_1_hwmod,
2992         .slave          = &dra7xx_dss_hdmi_hwmod,
2993         .clk            = "l3_iclk_div",
2994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2995 };
2996
2997 /* l3_main_1 -> aes1 */
2998 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
2999         .master         = &dra7xx_l3_main_1_hwmod,
3000         .slave          = &dra7xx_aes1_hwmod,
3001         .clk            = "l3_iclk_div",
3002         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3003 };
3004
3005 /* l3_main_1 -> aes2 */
3006 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3007         .master         = &dra7xx_l3_main_1_hwmod,
3008         .slave          = &dra7xx_aes2_hwmod,
3009         .clk            = "l3_iclk_div",
3010         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3011 };
3012
3013 /* l3_main_1 -> sha0 */
3014 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3015         .master         = &dra7xx_l3_main_1_hwmod,
3016         .slave          = &dra7xx_sha0_hwmod,
3017         .clk            = "l3_iclk_div",
3018         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3019 };
3020
3021 /* l4_per2 -> mcasp1 */
3022 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
3023         .master         = &dra7xx_l4_per2_hwmod,
3024         .slave          = &dra7xx_mcasp1_hwmod,
3025         .clk            = "l4_root_clk_div",
3026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3027 };
3028
3029 /* l3_main_1 -> mcasp1 */
3030 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
3031         .master         = &dra7xx_l3_main_1_hwmod,
3032         .slave          = &dra7xx_mcasp1_hwmod,
3033         .clk            = "l3_iclk_div",
3034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3035 };
3036
3037 /* l4_per2 -> mcasp2 */
3038 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3039         .master         = &dra7xx_l4_per2_hwmod,
3040         .slave          = &dra7xx_mcasp2_hwmod,
3041         .clk            = "l4_root_clk_div",
3042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3043 };
3044
3045 /* l3_main_1 -> mcasp2 */
3046 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
3047         .master         = &dra7xx_l3_main_1_hwmod,
3048         .slave          = &dra7xx_mcasp2_hwmod,
3049         .clk            = "l3_iclk_div",
3050         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3051 };
3052
3053 /* l4_per2 -> mcasp3 */
3054 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3055         .master         = &dra7xx_l4_per2_hwmod,
3056         .slave          = &dra7xx_mcasp3_hwmod,
3057         .clk            = "l4_root_clk_div",
3058         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3059 };
3060
3061 /* l3_main_1 -> mcasp3 */
3062 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
3063         .master         = &dra7xx_l3_main_1_hwmod,
3064         .slave          = &dra7xx_mcasp3_hwmod,
3065         .clk            = "l3_iclk_div",
3066         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3067 };
3068
3069 /* l4_per2 -> mcasp4 */
3070 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
3071         .master         = &dra7xx_l4_per2_hwmod,
3072         .slave          = &dra7xx_mcasp4_hwmod,
3073         .clk            = "l4_root_clk_div",
3074         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3075 };
3076
3077 /* l4_per2 -> mcasp5 */
3078 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
3079         .master         = &dra7xx_l4_per2_hwmod,
3080         .slave          = &dra7xx_mcasp5_hwmod,
3081         .clk            = "l4_root_clk_div",
3082         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3083 };
3084
3085 /* l4_per2 -> mcasp6 */
3086 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3087         .master         = &dra7xx_l4_per2_hwmod,
3088         .slave          = &dra7xx_mcasp6_hwmod,
3089         .clk            = "l4_root_clk_div",
3090         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3091 };
3092
3093 /* l4_per2 -> mcasp7 */
3094 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3095         .master         = &dra7xx_l4_per2_hwmod,
3096         .slave          = &dra7xx_mcasp7_hwmod,
3097         .clk            = "l4_root_clk_div",
3098         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3099 };
3100
3101 /* l4_per2 -> mcasp8 */
3102 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3103         .master         = &dra7xx_l4_per2_hwmod,
3104         .slave          = &dra7xx_mcasp8_hwmod,
3105         .clk            = "l4_root_clk_div",
3106         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3107 };
3108
3109 /* l4_per1 -> elm */
3110 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3111         .master         = &dra7xx_l4_per1_hwmod,
3112         .slave          = &dra7xx_elm_hwmod,
3113         .clk            = "l3_iclk_div",
3114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3115 };
3116
3117 /* l4_wkup -> gpio1 */
3118 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3119         .master         = &dra7xx_l4_wkup_hwmod,
3120         .slave          = &dra7xx_gpio1_hwmod,
3121         .clk            = "wkupaon_iclk_mux",
3122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3123 };
3124
3125 /* l4_per1 -> gpio2 */
3126 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3127         .master         = &dra7xx_l4_per1_hwmod,
3128         .slave          = &dra7xx_gpio2_hwmod,
3129         .clk            = "l3_iclk_div",
3130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3131 };
3132
3133 /* l4_per1 -> gpio3 */
3134 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3135         .master         = &dra7xx_l4_per1_hwmod,
3136         .slave          = &dra7xx_gpio3_hwmod,
3137         .clk            = "l3_iclk_div",
3138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3139 };
3140
3141 /* l4_per1 -> gpio4 */
3142 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3143         .master         = &dra7xx_l4_per1_hwmod,
3144         .slave          = &dra7xx_gpio4_hwmod,
3145         .clk            = "l3_iclk_div",
3146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3147 };
3148
3149 /* l4_per1 -> gpio5 */
3150 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3151         .master         = &dra7xx_l4_per1_hwmod,
3152         .slave          = &dra7xx_gpio5_hwmod,
3153         .clk            = "l3_iclk_div",
3154         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3155 };
3156
3157 /* l4_per1 -> gpio6 */
3158 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3159         .master         = &dra7xx_l4_per1_hwmod,
3160         .slave          = &dra7xx_gpio6_hwmod,
3161         .clk            = "l3_iclk_div",
3162         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3163 };
3164
3165 /* l4_per1 -> gpio7 */
3166 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3167         .master         = &dra7xx_l4_per1_hwmod,
3168         .slave          = &dra7xx_gpio7_hwmod,
3169         .clk            = "l3_iclk_div",
3170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3171 };
3172
3173 /* l4_per1 -> gpio8 */
3174 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3175         .master         = &dra7xx_l4_per1_hwmod,
3176         .slave          = &dra7xx_gpio8_hwmod,
3177         .clk            = "l3_iclk_div",
3178         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3179 };
3180
3181 /* l3_main_1 -> gpmc */
3182 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3183         .master         = &dra7xx_l3_main_1_hwmod,
3184         .slave          = &dra7xx_gpmc_hwmod,
3185         .clk            = "l3_iclk_div",
3186         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3187 };
3188
3189 /* l4_per1 -> hdq1w */
3190 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3191         .master         = &dra7xx_l4_per1_hwmod,
3192         .slave          = &dra7xx_hdq1w_hwmod,
3193         .clk            = "l3_iclk_div",
3194         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3195 };
3196
3197 /* l4_per1 -> i2c1 */
3198 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3199         .master         = &dra7xx_l4_per1_hwmod,
3200         .slave          = &dra7xx_i2c1_hwmod,
3201         .clk            = "l3_iclk_div",
3202         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3203 };
3204
3205 /* l4_per1 -> i2c2 */
3206 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3207         .master         = &dra7xx_l4_per1_hwmod,
3208         .slave          = &dra7xx_i2c2_hwmod,
3209         .clk            = "l3_iclk_div",
3210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3211 };
3212
3213 /* l4_per1 -> i2c3 */
3214 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3215         .master         = &dra7xx_l4_per1_hwmod,
3216         .slave          = &dra7xx_i2c3_hwmod,
3217         .clk            = "l3_iclk_div",
3218         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3219 };
3220
3221 /* l4_per1 -> i2c4 */
3222 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3223         .master         = &dra7xx_l4_per1_hwmod,
3224         .slave          = &dra7xx_i2c4_hwmod,
3225         .clk            = "l3_iclk_div",
3226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3227 };
3228
3229 /* l4_per1 -> i2c5 */
3230 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3231         .master         = &dra7xx_l4_per1_hwmod,
3232         .slave          = &dra7xx_i2c5_hwmod,
3233         .clk            = "l3_iclk_div",
3234         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3235 };
3236
3237 /* l4_cfg -> mailbox1 */
3238 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3239         .master         = &dra7xx_l4_cfg_hwmod,
3240         .slave          = &dra7xx_mailbox1_hwmod,
3241         .clk            = "l3_iclk_div",
3242         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3243 };
3244
3245 /* l4_per3 -> mailbox2 */
3246 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3247         .master         = &dra7xx_l4_per3_hwmod,
3248         .slave          = &dra7xx_mailbox2_hwmod,
3249         .clk            = "l3_iclk_div",
3250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3251 };
3252
3253 /* l4_per3 -> mailbox3 */
3254 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3255         .master         = &dra7xx_l4_per3_hwmod,
3256         .slave          = &dra7xx_mailbox3_hwmod,
3257         .clk            = "l3_iclk_div",
3258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3259 };
3260
3261 /* l4_per3 -> mailbox4 */
3262 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3263         .master         = &dra7xx_l4_per3_hwmod,
3264         .slave          = &dra7xx_mailbox4_hwmod,
3265         .clk            = "l3_iclk_div",
3266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3267 };
3268
3269 /* l4_per3 -> mailbox5 */
3270 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3271         .master         = &dra7xx_l4_per3_hwmod,
3272         .slave          = &dra7xx_mailbox5_hwmod,
3273         .clk            = "l3_iclk_div",
3274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3275 };
3276
3277 /* l4_per3 -> mailbox6 */
3278 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3279         .master         = &dra7xx_l4_per3_hwmod,
3280         .slave          = &dra7xx_mailbox6_hwmod,
3281         .clk            = "l3_iclk_div",
3282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3283 };
3284
3285 /* l4_per3 -> mailbox7 */
3286 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3287         .master         = &dra7xx_l4_per3_hwmod,
3288         .slave          = &dra7xx_mailbox7_hwmod,
3289         .clk            = "l3_iclk_div",
3290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3291 };
3292
3293 /* l4_per3 -> mailbox8 */
3294 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3295         .master         = &dra7xx_l4_per3_hwmod,
3296         .slave          = &dra7xx_mailbox8_hwmod,
3297         .clk            = "l3_iclk_div",
3298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3299 };
3300
3301 /* l4_per3 -> mailbox9 */
3302 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3303         .master         = &dra7xx_l4_per3_hwmod,
3304         .slave          = &dra7xx_mailbox9_hwmod,
3305         .clk            = "l3_iclk_div",
3306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3307 };
3308
3309 /* l4_per3 -> mailbox10 */
3310 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3311         .master         = &dra7xx_l4_per3_hwmod,
3312         .slave          = &dra7xx_mailbox10_hwmod,
3313         .clk            = "l3_iclk_div",
3314         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3315 };
3316
3317 /* l4_per3 -> mailbox11 */
3318 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3319         .master         = &dra7xx_l4_per3_hwmod,
3320         .slave          = &dra7xx_mailbox11_hwmod,
3321         .clk            = "l3_iclk_div",
3322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3323 };
3324
3325 /* l4_per3 -> mailbox12 */
3326 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3327         .master         = &dra7xx_l4_per3_hwmod,
3328         .slave          = &dra7xx_mailbox12_hwmod,
3329         .clk            = "l3_iclk_div",
3330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3331 };
3332
3333 /* l4_per3 -> mailbox13 */
3334 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3335         .master         = &dra7xx_l4_per3_hwmod,
3336         .slave          = &dra7xx_mailbox13_hwmod,
3337         .clk            = "l3_iclk_div",
3338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3339 };
3340
3341 /* l4_per1 -> mcspi1 */
3342 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3343         .master         = &dra7xx_l4_per1_hwmod,
3344         .slave          = &dra7xx_mcspi1_hwmod,
3345         .clk            = "l3_iclk_div",
3346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3347 };
3348
3349 /* l4_per1 -> mcspi2 */
3350 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3351         .master         = &dra7xx_l4_per1_hwmod,
3352         .slave          = &dra7xx_mcspi2_hwmod,
3353         .clk            = "l3_iclk_div",
3354         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3355 };
3356
3357 /* l4_per1 -> mcspi3 */
3358 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3359         .master         = &dra7xx_l4_per1_hwmod,
3360         .slave          = &dra7xx_mcspi3_hwmod,
3361         .clk            = "l3_iclk_div",
3362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3363 };
3364
3365 /* l4_per1 -> mcspi4 */
3366 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3367         .master         = &dra7xx_l4_per1_hwmod,
3368         .slave          = &dra7xx_mcspi4_hwmod,
3369         .clk            = "l3_iclk_div",
3370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3371 };
3372
3373 /* l4_per1 -> mmc1 */
3374 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3375         .master         = &dra7xx_l4_per1_hwmod,
3376         .slave          = &dra7xx_mmc1_hwmod,
3377         .clk            = "l3_iclk_div",
3378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3379 };
3380
3381 /* l4_per1 -> mmc2 */
3382 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3383         .master         = &dra7xx_l4_per1_hwmod,
3384         .slave          = &dra7xx_mmc2_hwmod,
3385         .clk            = "l3_iclk_div",
3386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3387 };
3388
3389 /* l4_per1 -> mmc3 */
3390 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3391         .master         = &dra7xx_l4_per1_hwmod,
3392         .slave          = &dra7xx_mmc3_hwmod,
3393         .clk            = "l3_iclk_div",
3394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3395 };
3396
3397 /* l4_per1 -> mmc4 */
3398 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3399         .master         = &dra7xx_l4_per1_hwmod,
3400         .slave          = &dra7xx_mmc4_hwmod,
3401         .clk            = "l3_iclk_div",
3402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3403 };
3404
3405 /* l4_cfg -> mpu */
3406 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3407         .master         = &dra7xx_l4_cfg_hwmod,
3408         .slave          = &dra7xx_mpu_hwmod,
3409         .clk            = "l3_iclk_div",
3410         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3411 };
3412
3413 /* l4_cfg -> ocp2scp1 */
3414 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3415         .master         = &dra7xx_l4_cfg_hwmod,
3416         .slave          = &dra7xx_ocp2scp1_hwmod,
3417         .clk            = "l4_root_clk_div",
3418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3419 };
3420
3421 /* l4_cfg -> ocp2scp3 */
3422 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3423         .master         = &dra7xx_l4_cfg_hwmod,
3424         .slave          = &dra7xx_ocp2scp3_hwmod,
3425         .clk            = "l4_root_clk_div",
3426         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3427 };
3428
3429 /* l3_main_1 -> pciess1 */
3430 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3431         .master         = &dra7xx_l3_main_1_hwmod,
3432         .slave          = &dra7xx_pciess1_hwmod,
3433         .clk            = "l3_iclk_div",
3434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3435 };
3436
3437 /* l4_cfg -> pciess1 */
3438 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3439         .master         = &dra7xx_l4_cfg_hwmod,
3440         .slave          = &dra7xx_pciess1_hwmod,
3441         .clk            = "l4_root_clk_div",
3442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3443 };
3444
3445 /* l3_main_1 -> pciess2 */
3446 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3447         .master         = &dra7xx_l3_main_1_hwmod,
3448         .slave          = &dra7xx_pciess2_hwmod,
3449         .clk            = "l3_iclk_div",
3450         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3451 };
3452
3453 /* l4_cfg -> pciess2 */
3454 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3455         .master         = &dra7xx_l4_cfg_hwmod,
3456         .slave          = &dra7xx_pciess2_hwmod,
3457         .clk            = "l4_root_clk_div",
3458         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3459 };
3460
3461 /* l3_main_1 -> qspi */
3462 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3463         .master         = &dra7xx_l3_main_1_hwmod,
3464         .slave          = &dra7xx_qspi_hwmod,
3465         .clk            = "l3_iclk_div",
3466         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3467 };
3468
3469 /* l4_per3 -> rtcss */
3470 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3471         .master         = &dra7xx_l4_per3_hwmod,
3472         .slave          = &dra7xx_rtcss_hwmod,
3473         .clk            = "l4_root_clk_div",
3474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3475 };
3476
3477 /* l4_cfg -> sata */
3478 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3479         .master         = &dra7xx_l4_cfg_hwmod,
3480         .slave          = &dra7xx_sata_hwmod,
3481         .clk            = "l3_iclk_div",
3482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3483 };
3484
3485 /* l4_cfg -> smartreflex_core */
3486 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3487         .master         = &dra7xx_l4_cfg_hwmod,
3488         .slave          = &dra7xx_smartreflex_core_hwmod,
3489         .clk            = "l4_root_clk_div",
3490         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3491 };
3492
3493 /* l4_cfg -> smartreflex_mpu */
3494 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3495         .master         = &dra7xx_l4_cfg_hwmod,
3496         .slave          = &dra7xx_smartreflex_mpu_hwmod,
3497         .clk            = "l4_root_clk_div",
3498         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3499 };
3500
3501 /* l4_cfg -> spinlock */
3502 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3503         .master         = &dra7xx_l4_cfg_hwmod,
3504         .slave          = &dra7xx_spinlock_hwmod,
3505         .clk            = "l3_iclk_div",
3506         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3507 };
3508
3509 /* l4_wkup -> timer1 */
3510 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3511         .master         = &dra7xx_l4_wkup_hwmod,
3512         .slave          = &dra7xx_timer1_hwmod,
3513         .clk            = "wkupaon_iclk_mux",
3514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3515 };
3516
3517 /* l4_per1 -> timer2 */
3518 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3519         .master         = &dra7xx_l4_per1_hwmod,
3520         .slave          = &dra7xx_timer2_hwmod,
3521         .clk            = "l3_iclk_div",
3522         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3523 };
3524
3525 /* l4_per1 -> timer3 */
3526 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3527         .master         = &dra7xx_l4_per1_hwmod,
3528         .slave          = &dra7xx_timer3_hwmod,
3529         .clk            = "l3_iclk_div",
3530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3531 };
3532
3533 /* l4_per1 -> timer4 */
3534 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3535         .master         = &dra7xx_l4_per1_hwmod,
3536         .slave          = &dra7xx_timer4_hwmod,
3537         .clk            = "l3_iclk_div",
3538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3539 };
3540
3541 /* l4_per3 -> timer5 */
3542 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3543         .master         = &dra7xx_l4_per3_hwmod,
3544         .slave          = &dra7xx_timer5_hwmod,
3545         .clk            = "l3_iclk_div",
3546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3547 };
3548
3549 /* l4_per3 -> timer6 */
3550 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3551         .master         = &dra7xx_l4_per3_hwmod,
3552         .slave          = &dra7xx_timer6_hwmod,
3553         .clk            = "l3_iclk_div",
3554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3555 };
3556
3557 /* l4_per3 -> timer7 */
3558 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3559         .master         = &dra7xx_l4_per3_hwmod,
3560         .slave          = &dra7xx_timer7_hwmod,
3561         .clk            = "l3_iclk_div",
3562         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3563 };
3564
3565 /* l4_per3 -> timer8 */
3566 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3567         .master         = &dra7xx_l4_per3_hwmod,
3568         .slave          = &dra7xx_timer8_hwmod,
3569         .clk            = "l3_iclk_div",
3570         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3571 };
3572
3573 /* l4_per1 -> timer9 */
3574 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3575         .master         = &dra7xx_l4_per1_hwmod,
3576         .slave          = &dra7xx_timer9_hwmod,
3577         .clk            = "l3_iclk_div",
3578         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3579 };
3580
3581 /* l4_per1 -> timer10 */
3582 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3583         .master         = &dra7xx_l4_per1_hwmod,
3584         .slave          = &dra7xx_timer10_hwmod,
3585         .clk            = "l3_iclk_div",
3586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3587 };
3588
3589 /* l4_per1 -> timer11 */
3590 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3591         .master         = &dra7xx_l4_per1_hwmod,
3592         .slave          = &dra7xx_timer11_hwmod,
3593         .clk            = "l3_iclk_div",
3594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3595 };
3596
3597 /* l4_wkup -> timer12 */
3598 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3599         .master         = &dra7xx_l4_wkup_hwmod,
3600         .slave          = &dra7xx_timer12_hwmod,
3601         .clk            = "wkupaon_iclk_mux",
3602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3603 };
3604
3605 /* l4_per3 -> timer13 */
3606 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3607         .master         = &dra7xx_l4_per3_hwmod,
3608         .slave          = &dra7xx_timer13_hwmod,
3609         .clk            = "l3_iclk_div",
3610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3611 };
3612
3613 /* l4_per3 -> timer14 */
3614 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3615         .master         = &dra7xx_l4_per3_hwmod,
3616         .slave          = &dra7xx_timer14_hwmod,
3617         .clk            = "l3_iclk_div",
3618         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3619 };
3620
3621 /* l4_per3 -> timer15 */
3622 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3623         .master         = &dra7xx_l4_per3_hwmod,
3624         .slave          = &dra7xx_timer15_hwmod,
3625         .clk            = "l3_iclk_div",
3626         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3627 };
3628
3629 /* l4_per3 -> timer16 */
3630 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3631         .master         = &dra7xx_l4_per3_hwmod,
3632         .slave          = &dra7xx_timer16_hwmod,
3633         .clk            = "l3_iclk_div",
3634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3635 };
3636
3637 /* l4_per1 -> uart1 */
3638 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3639         .master         = &dra7xx_l4_per1_hwmod,
3640         .slave          = &dra7xx_uart1_hwmod,
3641         .clk            = "l3_iclk_div",
3642         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3643 };
3644
3645 /* l4_per1 -> uart2 */
3646 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3647         .master         = &dra7xx_l4_per1_hwmod,
3648         .slave          = &dra7xx_uart2_hwmod,
3649         .clk            = "l3_iclk_div",
3650         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3651 };
3652
3653 /* l4_per1 -> uart3 */
3654 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3655         .master         = &dra7xx_l4_per1_hwmod,
3656         .slave          = &dra7xx_uart3_hwmod,
3657         .clk            = "l3_iclk_div",
3658         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3659 };
3660
3661 /* l4_per1 -> uart4 */
3662 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3663         .master         = &dra7xx_l4_per1_hwmod,
3664         .slave          = &dra7xx_uart4_hwmod,
3665         .clk            = "l3_iclk_div",
3666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3667 };
3668
3669 /* l4_per1 -> uart5 */
3670 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3671         .master         = &dra7xx_l4_per1_hwmod,
3672         .slave          = &dra7xx_uart5_hwmod,
3673         .clk            = "l3_iclk_div",
3674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3675 };
3676
3677 /* l4_per1 -> uart6 */
3678 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3679         .master         = &dra7xx_l4_per1_hwmod,
3680         .slave          = &dra7xx_uart6_hwmod,
3681         .clk            = "l3_iclk_div",
3682         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3683 };
3684
3685 /* l4_per2 -> uart7 */
3686 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3687         .master         = &dra7xx_l4_per2_hwmod,
3688         .slave          = &dra7xx_uart7_hwmod,
3689         .clk            = "l3_iclk_div",
3690         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3691 };
3692
3693 /* l4_per1 -> des */
3694 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3695         .master         = &dra7xx_l4_per1_hwmod,
3696         .slave          = &dra7xx_des_hwmod,
3697         .clk            = "l3_iclk_div",
3698         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3699 };
3700
3701 /* l4_per2 -> uart8 */
3702 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3703         .master         = &dra7xx_l4_per2_hwmod,
3704         .slave          = &dra7xx_uart8_hwmod,
3705         .clk            = "l3_iclk_div",
3706         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3707 };
3708
3709 /* l4_per2 -> uart9 */
3710 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3711         .master         = &dra7xx_l4_per2_hwmod,
3712         .slave          = &dra7xx_uart9_hwmod,
3713         .clk            = "l3_iclk_div",
3714         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3715 };
3716
3717 /* l4_wkup -> uart10 */
3718 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3719         .master         = &dra7xx_l4_wkup_hwmod,
3720         .slave          = &dra7xx_uart10_hwmod,
3721         .clk            = "wkupaon_iclk_mux",
3722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3723 };
3724
3725 /* l4_per1 -> rng */
3726 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3727         .master         = &dra7xx_l4_per1_hwmod,
3728         .slave          = &dra7xx_rng_hwmod,
3729         .user           = OCP_USER_MPU,
3730 };
3731
3732 /* l4_per3 -> usb_otg_ss1 */
3733 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3734         .master         = &dra7xx_l4_per3_hwmod,
3735         .slave          = &dra7xx_usb_otg_ss1_hwmod,
3736         .clk            = "dpll_core_h13x2_ck",
3737         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3738 };
3739
3740 /* l4_per3 -> usb_otg_ss2 */
3741 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3742         .master         = &dra7xx_l4_per3_hwmod,
3743         .slave          = &dra7xx_usb_otg_ss2_hwmod,
3744         .clk            = "dpll_core_h13x2_ck",
3745         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3746 };
3747
3748 /* l4_per3 -> usb_otg_ss3 */
3749 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3750         .master         = &dra7xx_l4_per3_hwmod,
3751         .slave          = &dra7xx_usb_otg_ss3_hwmod,
3752         .clk            = "dpll_core_h13x2_ck",
3753         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3754 };
3755
3756 /* l4_per3 -> usb_otg_ss4 */
3757 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3758         .master         = &dra7xx_l4_per3_hwmod,
3759         .slave          = &dra7xx_usb_otg_ss4_hwmod,
3760         .clk            = "dpll_core_h13x2_ck",
3761         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3762 };
3763
3764 /* l3_main_1 -> vcp1 */
3765 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3766         .master         = &dra7xx_l3_main_1_hwmod,
3767         .slave          = &dra7xx_vcp1_hwmod,
3768         .clk            = "l3_iclk_div",
3769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3770 };
3771
3772 /* l4_per2 -> vcp1 */
3773 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3774         .master         = &dra7xx_l4_per2_hwmod,
3775         .slave          = &dra7xx_vcp1_hwmod,
3776         .clk            = "l3_iclk_div",
3777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3778 };
3779
3780 /* l3_main_1 -> vcp2 */
3781 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3782         .master         = &dra7xx_l3_main_1_hwmod,
3783         .slave          = &dra7xx_vcp2_hwmod,
3784         .clk            = "l3_iclk_div",
3785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3786 };
3787
3788 /* l4_per2 -> vcp2 */
3789 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3790         .master         = &dra7xx_l4_per2_hwmod,
3791         .slave          = &dra7xx_vcp2_hwmod,
3792         .clk            = "l3_iclk_div",
3793         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3794 };
3795
3796 /* l4_wkup -> wd_timer2 */
3797 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3798         .master         = &dra7xx_l4_wkup_hwmod,
3799         .slave          = &dra7xx_wd_timer2_hwmod,
3800         .clk            = "wkupaon_iclk_mux",
3801         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3802 };
3803
3804 /* l4_per2 -> epwmss0 */
3805 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3806         .master         = &dra7xx_l4_per2_hwmod,
3807         .slave          = &dra7xx_epwmss0_hwmod,
3808         .clk            = "l4_root_clk_div",
3809         .user           = OCP_USER_MPU,
3810 };
3811
3812 /* l4_per2 -> epwmss1 */
3813 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3814         .master         = &dra7xx_l4_per2_hwmod,
3815         .slave          = &dra7xx_epwmss1_hwmod,
3816         .clk            = "l4_root_clk_div",
3817         .user           = OCP_USER_MPU,
3818 };
3819
3820 /* l4_per2 -> epwmss2 */
3821 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3822         .master         = &dra7xx_l4_per2_hwmod,
3823         .slave          = &dra7xx_epwmss2_hwmod,
3824         .clk            = "l4_root_clk_div",
3825         .user           = OCP_USER_MPU,
3826 };
3827
3828 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3829         &dra7xx_l3_main_1__dmm,
3830         &dra7xx_l3_main_2__l3_instr,
3831         &dra7xx_l4_cfg__l3_main_1,
3832         &dra7xx_mpu__l3_main_1,
3833         &dra7xx_l3_main_1__l3_main_2,
3834         &dra7xx_l4_cfg__l3_main_2,
3835         &dra7xx_l3_main_1__l4_cfg,
3836         &dra7xx_l3_main_1__l4_per1,
3837         &dra7xx_l3_main_1__l4_per2,
3838         &dra7xx_l3_main_1__l4_per3,
3839         &dra7xx_l3_main_1__l4_wkup,
3840         &dra7xx_l4_per2__atl,
3841         &dra7xx_l3_main_1__bb2d,
3842         &dra7xx_l4_wkup__counter_32k,
3843         &dra7xx_l4_wkup__ctrl_module_wkup,
3844         &dra7xx_l4_wkup__dcan1,
3845         &dra7xx_l4_per2__dcan2,
3846         &dra7xx_l4_per2__cpgmac0,
3847         &dra7xx_l4_per2__mcasp1,
3848         &dra7xx_l3_main_1__mcasp1,
3849         &dra7xx_l4_per2__mcasp2,
3850         &dra7xx_l3_main_1__mcasp2,
3851         &dra7xx_l4_per2__mcasp3,
3852         &dra7xx_l3_main_1__mcasp3,
3853         &dra7xx_l4_per2__mcasp4,
3854         &dra7xx_l4_per2__mcasp5,
3855         &dra7xx_l4_per2__mcasp6,
3856         &dra7xx_l4_per2__mcasp7,
3857         &dra7xx_l4_per2__mcasp8,
3858         &dra7xx_gmac__mdio,
3859         &dra7xx_l4_cfg__dma_system,
3860         &dra7xx_l3_main_1__tpcc,
3861         &dra7xx_l3_main_1__tptc0,
3862         &dra7xx_l3_main_1__tptc1,
3863         &dra7xx_l3_main_1__dss,
3864         &dra7xx_l3_main_1__dispc,
3865         &dra7xx_l3_main_1__hdmi,
3866         &dra7xx_l3_main_1__aes1,
3867         &dra7xx_l3_main_1__aes2,
3868         &dra7xx_l3_main_1__sha0,
3869         &dra7xx_l4_per1__elm,
3870         &dra7xx_l4_wkup__gpio1,
3871         &dra7xx_l4_per1__gpio2,
3872         &dra7xx_l4_per1__gpio3,
3873         &dra7xx_l4_per1__gpio4,
3874         &dra7xx_l4_per1__gpio5,
3875         &dra7xx_l4_per1__gpio6,
3876         &dra7xx_l4_per1__gpio7,
3877         &dra7xx_l4_per1__gpio8,
3878         &dra7xx_l3_main_1__gpmc,
3879         &dra7xx_l4_per1__hdq1w,
3880         &dra7xx_l4_per1__i2c1,
3881         &dra7xx_l4_per1__i2c2,
3882         &dra7xx_l4_per1__i2c3,
3883         &dra7xx_l4_per1__i2c4,
3884         &dra7xx_l4_per1__i2c5,
3885         &dra7xx_l4_cfg__mailbox1,
3886         &dra7xx_l4_per3__mailbox2,
3887         &dra7xx_l4_per3__mailbox3,
3888         &dra7xx_l4_per3__mailbox4,
3889         &dra7xx_l4_per3__mailbox5,
3890         &dra7xx_l4_per3__mailbox6,
3891         &dra7xx_l4_per3__mailbox7,
3892         &dra7xx_l4_per3__mailbox8,
3893         &dra7xx_l4_per3__mailbox9,
3894         &dra7xx_l4_per3__mailbox10,
3895         &dra7xx_l4_per3__mailbox11,
3896         &dra7xx_l4_per3__mailbox12,
3897         &dra7xx_l4_per3__mailbox13,
3898         &dra7xx_l4_per1__mcspi1,
3899         &dra7xx_l4_per1__mcspi2,
3900         &dra7xx_l4_per1__mcspi3,
3901         &dra7xx_l4_per1__mcspi4,
3902         &dra7xx_l4_per1__mmc1,
3903         &dra7xx_l4_per1__mmc2,
3904         &dra7xx_l4_per1__mmc3,
3905         &dra7xx_l4_per1__mmc4,
3906         &dra7xx_l4_cfg__mpu,
3907         &dra7xx_l4_cfg__ocp2scp1,
3908         &dra7xx_l4_cfg__ocp2scp3,
3909         &dra7xx_l3_main_1__pciess1,
3910         &dra7xx_l4_cfg__pciess1,
3911         &dra7xx_l3_main_1__pciess2,
3912         &dra7xx_l4_cfg__pciess2,
3913         &dra7xx_l3_main_1__qspi,
3914         &dra7xx_l4_cfg__sata,
3915         &dra7xx_l4_cfg__smartreflex_core,
3916         &dra7xx_l4_cfg__smartreflex_mpu,
3917         &dra7xx_l4_cfg__spinlock,
3918         &dra7xx_l4_wkup__timer1,
3919         &dra7xx_l4_per1__timer2,
3920         &dra7xx_l4_per1__timer3,
3921         &dra7xx_l4_per1__timer4,
3922         &dra7xx_l4_per3__timer5,
3923         &dra7xx_l4_per3__timer6,
3924         &dra7xx_l4_per3__timer7,
3925         &dra7xx_l4_per3__timer8,
3926         &dra7xx_l4_per1__timer9,
3927         &dra7xx_l4_per1__timer10,
3928         &dra7xx_l4_per1__timer11,
3929         &dra7xx_l4_per3__timer13,
3930         &dra7xx_l4_per3__timer14,
3931         &dra7xx_l4_per3__timer15,
3932         &dra7xx_l4_per3__timer16,
3933         &dra7xx_l4_per1__uart1,
3934         &dra7xx_l4_per1__uart2,
3935         &dra7xx_l4_per1__uart3,
3936         &dra7xx_l4_per1__uart4,
3937         &dra7xx_l4_per1__uart5,
3938         &dra7xx_l4_per1__uart6,
3939         &dra7xx_l4_per2__uart7,
3940         &dra7xx_l4_per2__uart8,
3941         &dra7xx_l4_per2__uart9,
3942         &dra7xx_l4_wkup__uart10,
3943         &dra7xx_l4_per1__des,
3944         &dra7xx_l4_per3__usb_otg_ss1,
3945         &dra7xx_l4_per3__usb_otg_ss2,
3946         &dra7xx_l4_per3__usb_otg_ss3,
3947         &dra7xx_l3_main_1__vcp1,
3948         &dra7xx_l4_per2__vcp1,
3949         &dra7xx_l3_main_1__vcp2,
3950         &dra7xx_l4_per2__vcp2,
3951         &dra7xx_l4_wkup__wd_timer2,
3952         &dra7xx_l4_per2__epwmss0,
3953         &dra7xx_l4_per2__epwmss1,
3954         &dra7xx_l4_per2__epwmss2,
3955         NULL,
3956 };
3957
3958 /* GP-only hwmod links */
3959 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
3960         &dra7xx_l4_wkup__timer12,
3961         &dra7xx_l4_per1__rng,
3962         NULL,
3963 };
3964
3965 /* SoC variant specific hwmod links */
3966 static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
3967         &dra7xx_l4_per3__usb_otg_ss4,
3968         NULL,
3969 };
3970
3971 static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = {
3972         NULL,
3973 };
3974
3975 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3976         &dra7xx_l4_per3__usb_otg_ss4,
3977         NULL,
3978 };
3979
3980 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3981         NULL,
3982 };
3983
3984 static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
3985         &dra7xx_l4_per3__rtcss,
3986         NULL,
3987 };
3988
3989 int __init dra7xx_hwmod_init(void)
3990 {
3991         int ret;
3992
3993         omap_hwmod_init();
3994         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3995
3996         if (!ret && soc_is_dra74x()) {
3997                 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3998                 if (!ret)
3999                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
4000         } else if (!ret && soc_is_dra72x()) {
4001                 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4002                 if (!ret && !of_machine_is_compatible("ti,dra718"))
4003                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
4004         } else if (!ret && soc_is_dra76x()) {
4005                 ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
4006
4007                 if (!ret && soc_is_dra76x_acd()) {
4008                         ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs);
4009                 } else if (!ret && soc_is_dra76x_abz()) {
4010                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
4011                 }
4012         }
4013
4014         if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
4015                 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
4016
4017         return ret;
4018 }