arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 /*
   2  * Hardware modules present on the DRA7xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/platform_data/hsmmc-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_7xx.h"
  34 #include "cm2_7xx.h"
  35 #include "prm7xx.h"
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "soc.h"
  39
  40 /* Base offset for all DRA7XX interrupts external to MPUSS */
  41 #define DRA7XX_IRQ_GIC_START    32
  42
  43 /* Base offset for all DRA7XX dma requests */
  44 #define DRA7XX_DMA_REQ_START    1
  45
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'dmm' class
  53  * instance(s): dmm
  54  */
  55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
  56         .name   = "dmm",
  57 };
  58
  59 /* dmm */
  60 static struct omap_hwmod dra7xx_dmm_hwmod = {
  61         .name           = "dmm",
  62         .class          = &dra7xx_dmm_hwmod_class,
  63         .clkdm_name     = "emif_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  67                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'l3' class
  74  * instance(s): l3_instr, l3_main_1, l3_main_2
  75  */
  76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  77         .name   = "l3",
  78 };
  79
  80 /* l3_instr */
  81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  82         .name           = "l3_instr",
  83         .class          = &dra7xx_l3_hwmod_class,
  84         .clkdm_name     = "l3instr_clkdm",
  85         .prcm = {
  86                 .omap4 = {
  87                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  88                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  89                         .modulemode   = MODULEMODE_HWCTRL,
  90                 },
  91         },
  92 };
  93
  94 /* l3_main_1 */
  95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  96         .name           = "l3_main_1",
  97         .class          = &dra7xx_l3_hwmod_class,
  98         .clkdm_name     = "l3main1_clkdm",
  99         .prcm = {
 100                 .omap4 = {
 101                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 102                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 103                 },
 104         },
 105 };
 106
 107 /* l3_main_2 */
 108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
 109         .name           = "l3_main_2",
 110         .class          = &dra7xx_l3_hwmod_class,
 111         .clkdm_name     = "l3instr_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
 115                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
 116                         .modulemode   = MODULEMODE_HWCTRL,
 117                 },
 118         },
 119 };
 120
 121 /*
 122  * 'l4' class
 123  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 124  */
 125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 126         .name   = "l4",
 127 };
 128
 129 /* l4_cfg */
 130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 131         .name           = "l4_cfg",
 132         .class          = &dra7xx_l4_hwmod_class,
 133         .clkdm_name     = "l4cfg_clkdm",
 134         .prcm = {
 135                 .omap4 = {
 136                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 137                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 138                 },
 139         },
 140 };
 141
 142 /* l4_per1 */
 143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 144         .name           = "l4_per1",
 145         .class          = &dra7xx_l4_hwmod_class,
 146         .clkdm_name     = "l4per_clkdm",
 147         .prcm = {
 148                 .omap4 = {
 149                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 150                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 151                 },
 152         },
 153 };
 154
 155 /* l4_per2 */
 156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 157         .name           = "l4_per2",
 158         .class          = &dra7xx_l4_hwmod_class,
 159         .clkdm_name     = "l4per2_clkdm",
 160         .prcm = {
 161                 .omap4 = {
 162                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 163                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 164                 },
 165         },
 166 };
 167
 168 /* l4_per3 */
 169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 170         .name           = "l4_per3",
 171         .class          = &dra7xx_l4_hwmod_class,
 172         .clkdm_name     = "l4per3_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 176                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 177                 },
 178         },
 179 };
 180
 181 /* l4_wkup */
 182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 183         .name           = "l4_wkup",
 184         .class          = &dra7xx_l4_hwmod_class,
 185         .clkdm_name     = "wkupaon_clkdm",
 186         .prcm = {
 187                 .omap4 = {
 188                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 189                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 190                 },
 191         },
 192 };
 193
 194 /*
 195  * 'atl' class
 196  *
 197  */
 198
 199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 200         .name   = "atl",
 201 };
 202
 203 /* atl */
 204 static struct omap_hwmod dra7xx_atl_hwmod = {
 205         .name           = "atl",
 206         .class          = &dra7xx_atl_hwmod_class,
 207         .clkdm_name     = "atl_clkdm",
 208         .main_clk       = "atl_gfclk_mux",
 209         .prcm = {
 210                 .omap4 = {
 211                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 212                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 213                         .modulemode   = MODULEMODE_SWCTRL,
 214                 },
 215         },
 216 };
 217
 218 /*
 219  * 'bb2d' class
 220  *
 221  */
 222
 223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 224         .name   = "bb2d",
 225 };
 226
 227 /* bb2d */
 228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 229         .name           = "bb2d",
 230         .class          = &dra7xx_bb2d_hwmod_class,
 231         .clkdm_name     = "dss_clkdm",
 232         .main_clk       = "dpll_core_h24x2_ck",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 236                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 237                         .modulemode   = MODULEMODE_SWCTRL,
 238                 },
 239         },
 240 };
 241
 242 /*
 243  * 'counter' class
 244  *
 245  */
 246
 247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 248         .rev_offs       = 0x0000,
 249         .sysc_offs      = 0x0010,
 250         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 251         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 252                            SIDLE_SMART_WKUP),
 253         .sysc_fields    = &omap_hwmod_sysc_type1,
 254 };
 255
 256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 257         .name   = "counter",
 258         .sysc   = &dra7xx_counter_sysc,
 259 };
 260
 261 /* counter_32k */
 262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 263         .name           = "counter_32k",
 264         .class          = &dra7xx_counter_hwmod_class,
 265         .clkdm_name     = "wkupaon_clkdm",
 266         .flags          = HWMOD_SWSUP_SIDLE,
 267         .main_clk       = "wkupaon_iclk_mux",
 268         .prcm = {
 269                 .omap4 = {
 270                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 271                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 272                 },
 273         },
 274 };
 275
 276 /*
 277  * 'ctrl_module' class
 278  *
 279  */
 280
 281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 282         .name   = "ctrl_module",
 283 };
 284
 285 /* ctrl_module_wkup */
 286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 287         .name           = "ctrl_module_wkup",
 288         .class          = &dra7xx_ctrl_module_hwmod_class,
 289         .clkdm_name     = "wkupaon_clkdm",
 290         .prcm = {
 291                 .omap4 = {
 292                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 293                 },
 294         },
 295 };
 296
 297 /*
 298  * 'gmac' class
 299  * cpsw/gmac sub system
 300  */
 301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
 302         .rev_offs       = 0x0,
 303         .sysc_offs      = 0x8,
 304         .syss_offs      = 0x4,
 305         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 306                            SYSS_HAS_RESET_STATUS),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 308                            MSTANDBY_NO),
 309         .sysc_fields    = &omap_hwmod_sysc_type3,
 310 };
 311
 312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
 313         .name           = "gmac",
 314         .sysc           = &dra7xx_gmac_sysc,
 315 };
 316
 317 static struct omap_hwmod dra7xx_gmac_hwmod = {
 318         .name           = "gmac",
 319         .class          = &dra7xx_gmac_hwmod_class,
 320         .clkdm_name     = "gmac_clkdm",
 321         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 322         .main_clk       = "dpll_gmac_ck",
 323         .mpu_rt_idx     = 1,
 324         .prcm           = {
 325                 .omap4  = {
 326                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
 327                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
 328                         .modulemode     = MODULEMODE_SWCTRL,
 329                 },
 330         },
 331 };
 332
 333 /*
 334  * 'mdio' class
 335  */
 336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
 337         .name           = "davinci_mdio",
 338 };
 339
 340 static struct omap_hwmod dra7xx_mdio_hwmod = {
 341         .name           = "davinci_mdio",
 342         .class          = &dra7xx_mdio_hwmod_class,
 343         .clkdm_name     = "gmac_clkdm",
 344         .main_clk       = "dpll_gmac_ck",
 345 };
 346
 347 /*
 348  * 'dcan' class
 349  *
 350  */
 351
 352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 353         .name   = "dcan",
 354 };
 355
 356 /* dcan1 */
 357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 358         .name           = "dcan1",
 359         .class          = &dra7xx_dcan_hwmod_class,
 360         .clkdm_name     = "wkupaon_clkdm",
 361         .main_clk       = "dcan1_sys_clk_mux",
 362         .flags          = HWMOD_CLKDM_NOAUTO,
 363         .prcm = {
 364                 .omap4 = {
 365                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 366                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 367                         .modulemode   = MODULEMODE_SWCTRL,
 368                 },
 369         },
 370 };
 371
 372 /* dcan2 */
 373 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 374         .name           = "dcan2",
 375         .class          = &dra7xx_dcan_hwmod_class,
 376         .clkdm_name     = "l4per2_clkdm",
 377         .main_clk       = "sys_clkin1",
 378         .flags          = HWMOD_CLKDM_NOAUTO,
 379         .prcm = {
 380                 .omap4 = {
 381                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 382                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 383                         .modulemode   = MODULEMODE_SWCTRL,
 384                 },
 385         },
 386 };
 387
 388 /* pwmss  */
 389 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
 390         .rev_offs       = 0x0,
 391         .sysc_offs      = 0x4,
 392         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 393                           SYSC_HAS_RESET_STATUS,
 394         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 395         .sysc_fields    = &omap_hwmod_sysc_type2,
 396 };
 397
 398 /*
 399  * epwmss class
 400  */
 401 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
 402         .name           = "epwmss",
 403         .sysc           = &dra7xx_epwmss_sysc,
 404 };
 405
 406 /* epwmss0 */
 407 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
 408         .name           = "epwmss0",
 409         .class          = &dra7xx_epwmss_hwmod_class,
 410         .clkdm_name     = "l4per2_clkdm",
 411         .main_clk       = "l4_root_clk_div",
 412         .prcm           = {
 413                 .omap4  = {
 414                         .modulemode     = MODULEMODE_SWCTRL,
 415                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
 416                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
 417                 },
 418         },
 419 };
 420
 421 /* epwmss1 */
 422 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
 423         .name           = "epwmss1",
 424         .class          = &dra7xx_epwmss_hwmod_class,
 425         .clkdm_name     = "l4per2_clkdm",
 426         .main_clk       = "l4_root_clk_div",
 427         .prcm           = {
 428                 .omap4  = {
 429                         .modulemode     = MODULEMODE_SWCTRL,
 430                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
 431                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
 432                 },
 433         },
 434 };
 435
 436 /* epwmss2 */
 437 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
 438         .name           = "epwmss2",
 439         .class          = &dra7xx_epwmss_hwmod_class,
 440         .clkdm_name     = "l4per2_clkdm",
 441         .main_clk       = "l4_root_clk_div",
 442         .prcm           = {
 443                 .omap4  = {
 444                         .modulemode     = MODULEMODE_SWCTRL,
 445                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
 446                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
 447                 },
 448         },
 449 };
 450
 451 /*
 452  * 'dma' class
 453  *
 454  */
 455
 456 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 457         .rev_offs       = 0x0000,
 458         .sysc_offs      = 0x002c,
 459         .syss_offs      = 0x0028,
 460         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 461                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 462                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 463                            SYSS_HAS_RESET_STATUS),
 464         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 465                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 466                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 467         .sysc_fields    = &omap_hwmod_sysc_type1,
 468 };
 469
 470 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 471         .name   = "dma",
 472         .sysc   = &dra7xx_dma_sysc,
 473 };
 474
 475 /* dma dev_attr */
 476 static struct omap_dma_dev_attr dma_dev_attr = {
 477         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 478                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 479         .lch_count      = 32,
 480 };
 481
 482 /* dma_system */
 483 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 484         .name           = "dma_system",
 485         .class          = &dra7xx_dma_hwmod_class,
 486         .clkdm_name     = "dma_clkdm",
 487         .main_clk       = "l3_iclk_div",
 488         .prcm = {
 489                 .omap4 = {
 490                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 491                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 492                 },
 493         },
 494         .dev_attr       = &dma_dev_attr,
 495 };
 496
 497 /*
 498  * 'tpcc' class
 499  *
 500  */
 501 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
 502         .name           = "tpcc",
 503 };
 504
 505 static struct omap_hwmod dra7xx_tpcc_hwmod = {
 506         .name           = "tpcc",
 507         .class          = &dra7xx_tpcc_hwmod_class,
 508         .clkdm_name     = "l3main1_clkdm",
 509         .main_clk       = "l3_iclk_div",
 510         .prcm           = {
 511                 .omap4  = {
 512                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
 513                         .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
 514                 },
 515         },
 516 };
 517
 518 /*
 519  * 'tptc' class
 520  *
 521  */
 522 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
 523         .name           = "tptc",
 524 };
 525
 526 /* tptc0 */
 527 static struct omap_hwmod dra7xx_tptc0_hwmod = {
 528         .name           = "tptc0",
 529         .class          = &dra7xx_tptc_hwmod_class,
 530         .clkdm_name     = "l3main1_clkdm",
 531         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 532         .main_clk       = "l3_iclk_div",
 533         .prcm           = {
 534                 .omap4  = {
 535                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
 536                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
 537                         .modulemode   = MODULEMODE_HWCTRL,
 538                 },
 539         },
 540 };
 541
 542 /* tptc1 */
 543 static struct omap_hwmod dra7xx_tptc1_hwmod = {
 544         .name           = "tptc1",
 545         .class          = &dra7xx_tptc_hwmod_class,
 546         .clkdm_name     = "l3main1_clkdm",
 547         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 548         .main_clk       = "l3_iclk_div",
 549         .prcm           = {
 550                 .omap4  = {
 551                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
 552                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
 553                         .modulemode   = MODULEMODE_HWCTRL,
 554                 },
 555         },
 556 };
 557
 558 /*
 559  * 'dss' class
 560  *
 561  */
 562
 563 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 564         .rev_offs       = 0x0000,
 565         .syss_offs      = 0x0014,
 566         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 567 };
 568
 569 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 570         .name   = "dss",
 571         .sysc   = &dra7xx_dss_sysc,
 572         .reset  = omap_dss_reset,
 573 };
 574
 575 /* dss */
 576 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
 577         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
 578         { .dma_req = -1 }
 579 };
 580
 581 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 582         { .role = "dss_clk", .clk = "dss_dss_clk" },
 583         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 584         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 585         { .role = "video2_clk", .clk = "dss_video2_clk" },
 586         { .role = "video1_clk", .clk = "dss_video1_clk" },
 587         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 588         { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
 589 };
 590
 591 static struct omap_hwmod dra7xx_dss_hwmod = {
 592         .name           = "dss_core",
 593         .class          = &dra7xx_dss_hwmod_class,
 594         .clkdm_name     = "dss_clkdm",
 595         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 596         .sdma_reqs      = dra7xx_dss_sdma_reqs,
 597         .main_clk       = "dss_dss_clk",
 598         .prcm = {
 599                 .omap4 = {
 600                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 601                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 602                         .modulemode   = MODULEMODE_SWCTRL,
 603                 },
 604         },
 605         .opt_clks       = dss_opt_clks,
 606         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 607 };
 608
 609 /*
 610  * 'dispc' class
 611  * display controller
 612  */
 613
 614 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 615         .rev_offs       = 0x0000,
 616         .sysc_offs      = 0x0010,
 617         .syss_offs      = 0x0014,
 618         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 619                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 620                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 621                            SYSS_HAS_RESET_STATUS),
 622         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 623                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 624         .sysc_fields    = &omap_hwmod_sysc_type1,
 625 };
 626
 627 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 628         .name   = "dispc",
 629         .sysc   = &dra7xx_dispc_sysc,
 630 };
 631
 632 /* dss_dispc */
 633 /* dss_dispc dev_attr */
 634 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 635         .has_framedonetv_irq    = 1,
 636         .manager_count          = 4,
 637 };
 638
 639 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 640         .name           = "dss_dispc",
 641         .class          = &dra7xx_dispc_hwmod_class,
 642         .clkdm_name     = "dss_clkdm",
 643         .main_clk       = "dss_dss_clk",
 644         .prcm = {
 645                 .omap4 = {
 646                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 647                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 648                 },
 649         },
 650         .dev_attr       = &dss_dispc_dev_attr,
 651         .parent_hwmod   = &dra7xx_dss_hwmod,
 652 };
 653
 654 /*
 655  * 'hdmi' class
 656  * hdmi controller
 657  */
 658
 659 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 660         .rev_offs       = 0x0000,
 661         .sysc_offs      = 0x0010,
 662         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 663                            SYSC_HAS_SOFTRESET),
 664         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 665                            SIDLE_SMART_WKUP),
 666         .sysc_fields    = &omap_hwmod_sysc_type2,
 667 };
 668
 669 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 670         .name   = "hdmi",
 671         .sysc   = &dra7xx_hdmi_sysc,
 672 };
 673
 674 /* dss_hdmi */
 675
 676 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 677         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 678 };
 679
 680 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 681         .name           = "dss_hdmi",
 682         .class          = &dra7xx_hdmi_hwmod_class,
 683         .clkdm_name     = "dss_clkdm",
 684         .main_clk       = "dss_48mhz_clk",
 685         .prcm = {
 686                 .omap4 = {
 687                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 688                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 689                 },
 690         },
 691         .opt_clks       = dss_hdmi_opt_clks,
 692         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 693         .parent_hwmod   = &dra7xx_dss_hwmod,
 694 };
 695
 696 /* AES (the 'P' (public) device) */
 697 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
 698         .rev_offs       = 0x0080,
 699         .sysc_offs      = 0x0084,
 700         .syss_offs      = 0x0088,
 701         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 702 };
 703
 704 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
 705         .name   = "aes",
 706         .sysc   = &dra7xx_aes_sysc,
 707         .rev    = 2,
 708 };
 709
 710 /* AES1 */
 711 static struct omap_hwmod dra7xx_aes1_hwmod = {
 712         .name           = "aes1",
 713         .class          = &dra7xx_aes_hwmod_class,
 714         .clkdm_name     = "l4sec_clkdm",
 715         .main_clk       = "l3_iclk_div",
 716         .prcm = {
 717                 .omap4 = {
 718                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 719                         .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
 720                         .modulemode   = MODULEMODE_HWCTRL,
 721                 },
 722         },
 723 };
 724
 725 /* AES2 */
 726 static struct omap_hwmod dra7xx_aes2_hwmod = {
 727         .name           = "aes2",
 728         .class          = &dra7xx_aes_hwmod_class,
 729         .clkdm_name     = "l4sec_clkdm",
 730         .main_clk       = "l3_iclk_div",
 731         .prcm = {
 732                 .omap4 = {
 733                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 734                         .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
 735                         .modulemode   = MODULEMODE_HWCTRL,
 736                 },
 737         },
 738 };
 739
 740 /* sha0 HIB2 (the 'P' (public) device) */
 741 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
 742         .rev_offs       = 0x100,
 743         .sysc_offs      = 0x110,
 744         .syss_offs      = 0x114,
 745         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 746 };
 747
 748 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
 749         .name           = "sham",
 750         .sysc           = &dra7xx_sha0_sysc,
 751         .rev            = 2,
 752 };
 753
 754 struct omap_hwmod dra7xx_sha0_hwmod = {
 755         .name           = "sham",
 756         .class          = &dra7xx_sha0_hwmod_class,
 757         .clkdm_name     = "l4sec_clkdm",
 758         .main_clk       = "l3_iclk_div",
 759         .prcm           = {
 760                 .omap4 = {
 761                         .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 762                         .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 763                         .modulemode   = MODULEMODE_HWCTRL,
 764                 },
 765         },
 766 };
 767
 768 /*
 769  * 'elm' class
 770  *
 771  */
 772
 773 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 774         .rev_offs       = 0x0000,
 775         .sysc_offs      = 0x0010,
 776         .syss_offs      = 0x0014,
 777         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 778                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 779                            SYSS_HAS_RESET_STATUS),
 780         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 781                            SIDLE_SMART_WKUP),
 782         .sysc_fields    = &omap_hwmod_sysc_type1,
 783 };
 784
 785 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 786         .name   = "elm",
 787         .sysc   = &dra7xx_elm_sysc,
 788 };
 789
 790 /* elm */
 791
 792 static struct omap_hwmod dra7xx_elm_hwmod = {
 793         .name           = "elm",
 794         .class          = &dra7xx_elm_hwmod_class,
 795         .clkdm_name     = "l4per_clkdm",
 796         .main_clk       = "l3_iclk_div",
 797         .prcm = {
 798                 .omap4 = {
 799                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 800                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 801                 },
 802         },
 803 };
 804
 805 /*
 806  * 'gpio' class
 807  *
 808  */
 809
 810 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
 811         .rev_offs       = 0x0000,
 812         .sysc_offs      = 0x0010,
 813         .syss_offs      = 0x0114,
 814         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 815                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 816                            SYSS_HAS_RESET_STATUS),
 817         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 818                            SIDLE_SMART_WKUP),
 819         .sysc_fields    = &omap_hwmod_sysc_type1,
 820 };
 821
 822 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 823         .name   = "gpio",
 824         .sysc   = &dra7xx_gpio_sysc,
 825         .rev    = 2,
 826 };
 827
 828 /* gpio dev_attr */
 829 static struct omap_gpio_dev_attr gpio_dev_attr = {
 830         .bank_width     = 32,
 831         .dbck_flag      = true,
 832 };
 833
 834 /* gpio1 */
 835 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 836         { .role = "dbclk", .clk = "gpio1_dbclk" },
 837 };
 838
 839 static struct omap_hwmod dra7xx_gpio1_hwmod = {
 840         .name           = "gpio1",
 841         .class          = &dra7xx_gpio_hwmod_class,
 842         .clkdm_name     = "wkupaon_clkdm",
 843         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 844         .main_clk       = "wkupaon_iclk_mux",
 845         .prcm = {
 846                 .omap4 = {
 847                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 848                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 849                         .modulemode   = MODULEMODE_HWCTRL,
 850                 },
 851         },
 852         .opt_clks       = gpio1_opt_clks,
 853         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 854         .dev_attr       = &gpio_dev_attr,
 855 };
 856
 857 /* gpio2 */
 858 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 859         { .role = "dbclk", .clk = "gpio2_dbclk" },
 860 };
 861
 862 static struct omap_hwmod dra7xx_gpio2_hwmod = {
 863         .name           = "gpio2",
 864         .class          = &dra7xx_gpio_hwmod_class,
 865         .clkdm_name     = "l4per_clkdm",
 866         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 867         .main_clk       = "l3_iclk_div",
 868         .prcm = {
 869                 .omap4 = {
 870                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 871                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 872                         .modulemode   = MODULEMODE_HWCTRL,
 873                 },
 874         },
 875         .opt_clks       = gpio2_opt_clks,
 876         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 877         .dev_attr       = &gpio_dev_attr,
 878 };
 879
 880 /* gpio3 */
 881 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 882         { .role = "dbclk", .clk = "gpio3_dbclk" },
 883 };
 884
 885 static struct omap_hwmod dra7xx_gpio3_hwmod = {
 886         .name           = "gpio3",
 887         .class          = &dra7xx_gpio_hwmod_class,
 888         .clkdm_name     = "l4per_clkdm",
 889         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 890         .main_clk       = "l3_iclk_div",
 891         .prcm = {
 892                 .omap4 = {
 893                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 894                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 895                         .modulemode   = MODULEMODE_HWCTRL,
 896                 },
 897         },
 898         .opt_clks       = gpio3_opt_clks,
 899         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 900         .dev_attr       = &gpio_dev_attr,
 901 };
 902
 903 /* gpio4 */
 904 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 905         { .role = "dbclk", .clk = "gpio4_dbclk" },
 906 };
 907
 908 static struct omap_hwmod dra7xx_gpio4_hwmod = {
 909         .name           = "gpio4",
 910         .class          = &dra7xx_gpio_hwmod_class,
 911         .clkdm_name     = "l4per_clkdm",
 912         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 913         .main_clk       = "l3_iclk_div",
 914         .prcm = {
 915                 .omap4 = {
 916                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 917                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 918                         .modulemode   = MODULEMODE_HWCTRL,
 919                 },
 920         },
 921         .opt_clks       = gpio4_opt_clks,
 922         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 923         .dev_attr       = &gpio_dev_attr,
 924 };
 925
 926 /* gpio5 */
 927 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 928         { .role = "dbclk", .clk = "gpio5_dbclk" },
 929 };
 930
 931 static struct omap_hwmod dra7xx_gpio5_hwmod = {
 932         .name           = "gpio5",
 933         .class          = &dra7xx_gpio_hwmod_class,
 934         .clkdm_name     = "l4per_clkdm",
 935         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 936         .main_clk       = "l3_iclk_div",
 937         .prcm = {
 938                 .omap4 = {
 939                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 940                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 941                         .modulemode   = MODULEMODE_HWCTRL,
 942                 },
 943         },
 944         .opt_clks       = gpio5_opt_clks,
 945         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 946         .dev_attr       = &gpio_dev_attr,
 947 };
 948
 949 /* gpio6 */
 950 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 951         { .role = "dbclk", .clk = "gpio6_dbclk" },
 952 };
 953
 954 static struct omap_hwmod dra7xx_gpio6_hwmod = {
 955         .name           = "gpio6",
 956         .class          = &dra7xx_gpio_hwmod_class,
 957         .clkdm_name     = "l4per_clkdm",
 958         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 959         .main_clk       = "l3_iclk_div",
 960         .prcm = {
 961                 .omap4 = {
 962                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 963                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 964                         .modulemode   = MODULEMODE_HWCTRL,
 965                 },
 966         },
 967         .opt_clks       = gpio6_opt_clks,
 968         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 969         .dev_attr       = &gpio_dev_attr,
 970 };
 971
 972 /* gpio7 */
 973 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 974         { .role = "dbclk", .clk = "gpio7_dbclk" },
 975 };
 976
 977 static struct omap_hwmod dra7xx_gpio7_hwmod = {
 978         .name           = "gpio7",
 979         .class          = &dra7xx_gpio_hwmod_class,
 980         .clkdm_name     = "l4per_clkdm",
 981         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 982         .main_clk       = "l3_iclk_div",
 983         .prcm = {
 984                 .omap4 = {
 985                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 986                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 987                         .modulemode   = MODULEMODE_HWCTRL,
 988                 },
 989         },
 990         .opt_clks       = gpio7_opt_clks,
 991         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 992         .dev_attr       = &gpio_dev_attr,
 993 };
 994
 995 /* gpio8 */
 996 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 997         { .role = "dbclk", .clk = "gpio8_dbclk" },
 998 };
 999
1000 static struct omap_hwmod dra7xx_gpio8_hwmod = {
1001         .name           = "gpio8",
1002         .class          = &dra7xx_gpio_hwmod_class,
1003         .clkdm_name     = "l4per_clkdm",
1004         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1005         .main_clk       = "l3_iclk_div",
1006         .prcm = {
1007                 .omap4 = {
1008                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1009                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1010                         .modulemode   = MODULEMODE_HWCTRL,
1011                 },
1012         },
1013         .opt_clks       = gpio8_opt_clks,
1014         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
1015         .dev_attr       = &gpio_dev_attr,
1016 };
1017
1018 /*
1019  * 'gpmc' class
1020  *
1021  */
1022
1023 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1024         .rev_offs       = 0x0000,
1025         .sysc_offs      = 0x0010,
1026         .syss_offs      = 0x0014,
1027         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1028                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1029         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1030         .sysc_fields    = &omap_hwmod_sysc_type1,
1031 };
1032
1033 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1034         .name   = "gpmc",
1035         .sysc   = &dra7xx_gpmc_sysc,
1036 };
1037
1038 /* gpmc */
1039
1040 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1041         .name           = "gpmc",
1042         .class          = &dra7xx_gpmc_hwmod_class,
1043         .clkdm_name     = "l3main1_clkdm",
1044         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1045         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1046         .main_clk       = "l3_iclk_div",
1047         .prcm = {
1048                 .omap4 = {
1049                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1050                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1051                         .modulemode   = MODULEMODE_HWCTRL,
1052                 },
1053         },
1054 };
1055
1056 /*
1057  * 'hdq1w' class
1058  *
1059  */
1060
1061 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1062         .rev_offs       = 0x0000,
1063         .sysc_offs      = 0x0014,
1064         .syss_offs      = 0x0018,
1065         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1066                            SYSS_HAS_RESET_STATUS),
1067         .sysc_fields    = &omap_hwmod_sysc_type1,
1068 };
1069
1070 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1071         .name   = "hdq1w",
1072         .sysc   = &dra7xx_hdq1w_sysc,
1073 };
1074
1075 /* hdq1w */
1076
1077 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1078         .name           = "hdq1w",
1079         .class          = &dra7xx_hdq1w_hwmod_class,
1080         .clkdm_name     = "l4per_clkdm",
1081         .flags          = HWMOD_INIT_NO_RESET,
1082         .main_clk       = "func_12m_fclk",
1083         .prcm = {
1084                 .omap4 = {
1085                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1086                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1087                         .modulemode   = MODULEMODE_SWCTRL,
1088                 },
1089         },
1090 };
1091
1092 /*
1093  * 'i2c' class
1094  *
1095  */
1096
1097 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1098         .sysc_offs      = 0x0010,
1099         .syss_offs      = 0x0090,
1100         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1101                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1102                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1103         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1104                            SIDLE_SMART_WKUP),
1105         .sysc_fields    = &omap_hwmod_sysc_type1,
1106 };
1107
1108 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1109         .name   = "i2c",
1110         .sysc   = &dra7xx_i2c_sysc,
1111         .reset  = &omap_i2c_reset,
1112         .rev    = OMAP_I2C_IP_VERSION_2,
1113 };
1114
1115 /* i2c dev_attr */
1116 static struct omap_i2c_dev_attr i2c_dev_attr = {
1117         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1118 };
1119
1120 /* i2c1 */
1121 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1122         .name           = "i2c1",
1123         .class          = &dra7xx_i2c_hwmod_class,
1124         .clkdm_name     = "l4per_clkdm",
1125         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1126         .main_clk       = "func_96m_fclk",
1127         .prcm = {
1128                 .omap4 = {
1129                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1130                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1131                         .modulemode   = MODULEMODE_SWCTRL,
1132                 },
1133         },
1134         .dev_attr       = &i2c_dev_attr,
1135 };
1136
1137 /* i2c2 */
1138 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1139         .name           = "i2c2",
1140         .class          = &dra7xx_i2c_hwmod_class,
1141         .clkdm_name     = "l4per_clkdm",
1142         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1143         .main_clk       = "func_96m_fclk",
1144         .prcm = {
1145                 .omap4 = {
1146                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1147                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1148                         .modulemode   = MODULEMODE_SWCTRL,
1149                 },
1150         },
1151         .dev_attr       = &i2c_dev_attr,
1152 };
1153
1154 /* i2c3 */
1155 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1156         .name           = "i2c3",
1157         .class          = &dra7xx_i2c_hwmod_class,
1158         .clkdm_name     = "l4per_clkdm",
1159         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1160         .main_clk       = "func_96m_fclk",
1161         .prcm = {
1162                 .omap4 = {
1163                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1164                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1165                         .modulemode   = MODULEMODE_SWCTRL,
1166                 },
1167         },
1168         .dev_attr       = &i2c_dev_attr,
1169 };
1170
1171 /* i2c4 */
1172 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1173         .name           = "i2c4",
1174         .class          = &dra7xx_i2c_hwmod_class,
1175         .clkdm_name     = "l4per_clkdm",
1176         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1177         .main_clk       = "func_96m_fclk",
1178         .prcm = {
1179                 .omap4 = {
1180                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1181                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1182                         .modulemode   = MODULEMODE_SWCTRL,
1183                 },
1184         },
1185         .dev_attr       = &i2c_dev_attr,
1186 };
1187
1188 /* i2c5 */
1189 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1190         .name           = "i2c5",
1191         .class          = &dra7xx_i2c_hwmod_class,
1192         .clkdm_name     = "ipu_clkdm",
1193         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1194         .main_clk       = "func_96m_fclk",
1195         .prcm = {
1196                 .omap4 = {
1197                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1198                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1199                         .modulemode   = MODULEMODE_SWCTRL,
1200                 },
1201         },
1202         .dev_attr       = &i2c_dev_attr,
1203 };
1204
1205 /*
1206  * 'mailbox' class
1207  *
1208  */
1209
1210 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1211         .rev_offs       = 0x0000,
1212         .sysc_offs      = 0x0010,
1213         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1214                            SYSC_HAS_SOFTRESET),
1215         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1216         .sysc_fields    = &omap_hwmod_sysc_type2,
1217 };
1218
1219 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1220         .name   = "mailbox",
1221         .sysc   = &dra7xx_mailbox_sysc,
1222 };
1223
1224 /* mailbox1 */
1225 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1226         .name           = "mailbox1",
1227         .class          = &dra7xx_mailbox_hwmod_class,
1228         .clkdm_name     = "l4cfg_clkdm",
1229         .prcm = {
1230                 .omap4 = {
1231                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1232                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1233                 },
1234         },
1235 };
1236
1237 /* mailbox2 */
1238 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1239         .name           = "mailbox2",
1240         .class          = &dra7xx_mailbox_hwmod_class,
1241         .clkdm_name     = "l4cfg_clkdm",
1242         .prcm = {
1243                 .omap4 = {
1244                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1245                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1246                 },
1247         },
1248 };
1249
1250 /* mailbox3 */
1251 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1252         .name           = "mailbox3",
1253         .class          = &dra7xx_mailbox_hwmod_class,
1254         .clkdm_name     = "l4cfg_clkdm",
1255         .prcm = {
1256                 .omap4 = {
1257                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1258                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1259                 },
1260         },
1261 };
1262
1263 /* mailbox4 */
1264 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1265         .name           = "mailbox4",
1266         .class          = &dra7xx_mailbox_hwmod_class,
1267         .clkdm_name     = "l4cfg_clkdm",
1268         .prcm = {
1269                 .omap4 = {
1270                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1271                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1272                 },
1273         },
1274 };
1275
1276 /* mailbox5 */
1277 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1278         .name           = "mailbox5",
1279         .class          = &dra7xx_mailbox_hwmod_class,
1280         .clkdm_name     = "l4cfg_clkdm",
1281         .prcm = {
1282                 .omap4 = {
1283                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1284                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1285                 },
1286         },
1287 };
1288
1289 /* mailbox6 */
1290 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1291         .name           = "mailbox6",
1292         .class          = &dra7xx_mailbox_hwmod_class,
1293         .clkdm_name     = "l4cfg_clkdm",
1294         .prcm = {
1295                 .omap4 = {
1296                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1297                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1298                 },
1299         },
1300 };
1301
1302 /* mailbox7 */
1303 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1304         .name           = "mailbox7",
1305         .class          = &dra7xx_mailbox_hwmod_class,
1306         .clkdm_name     = "l4cfg_clkdm",
1307         .prcm = {
1308                 .omap4 = {
1309                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1310                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1311                 },
1312         },
1313 };
1314
1315 /* mailbox8 */
1316 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1317         .name           = "mailbox8",
1318         .class          = &dra7xx_mailbox_hwmod_class,
1319         .clkdm_name     = "l4cfg_clkdm",
1320         .prcm = {
1321                 .omap4 = {
1322                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1323                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1324                 },
1325         },
1326 };
1327
1328 /* mailbox9 */
1329 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1330         .name           = "mailbox9",
1331         .class          = &dra7xx_mailbox_hwmod_class,
1332         .clkdm_name     = "l4cfg_clkdm",
1333         .prcm = {
1334                 .omap4 = {
1335                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1336                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1337                 },
1338         },
1339 };
1340
1341 /* mailbox10 */
1342 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1343         .name           = "mailbox10",
1344         .class          = &dra7xx_mailbox_hwmod_class,
1345         .clkdm_name     = "l4cfg_clkdm",
1346         .prcm = {
1347                 .omap4 = {
1348                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1349                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1350                 },
1351         },
1352 };
1353
1354 /* mailbox11 */
1355 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1356         .name           = "mailbox11",
1357         .class          = &dra7xx_mailbox_hwmod_class,
1358         .clkdm_name     = "l4cfg_clkdm",
1359         .prcm = {
1360                 .omap4 = {
1361                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1362                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1363                 },
1364         },
1365 };
1366
1367 /* mailbox12 */
1368 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1369         .name           = "mailbox12",
1370         .class          = &dra7xx_mailbox_hwmod_class,
1371         .clkdm_name     = "l4cfg_clkdm",
1372         .prcm = {
1373                 .omap4 = {
1374                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1375                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1376                 },
1377         },
1378 };
1379
1380 /* mailbox13 */
1381 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1382         .name           = "mailbox13",
1383         .class          = &dra7xx_mailbox_hwmod_class,
1384         .clkdm_name     = "l4cfg_clkdm",
1385         .prcm = {
1386                 .omap4 = {
1387                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1388                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1389                 },
1390         },
1391 };
1392
1393 /*
1394  * 'mcspi' class
1395  *
1396  */
1397
1398 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1399         .rev_offs       = 0x0000,
1400         .sysc_offs      = 0x0010,
1401         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1402                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1403         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1404                            SIDLE_SMART_WKUP),
1405         .sysc_fields    = &omap_hwmod_sysc_type2,
1406 };
1407
1408 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1409         .name   = "mcspi",
1410         .sysc   = &dra7xx_mcspi_sysc,
1411         .rev    = OMAP4_MCSPI_REV,
1412 };
1413
1414 /* mcspi1 */
1415 /* mcspi1 dev_attr */
1416 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1417         .num_chipselect = 4,
1418 };
1419
1420 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1421         .name           = "mcspi1",
1422         .class          = &dra7xx_mcspi_hwmod_class,
1423         .clkdm_name     = "l4per_clkdm",
1424         .main_clk       = "func_48m_fclk",
1425         .prcm = {
1426                 .omap4 = {
1427                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1428                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1429                         .modulemode   = MODULEMODE_SWCTRL,
1430                 },
1431         },
1432         .dev_attr       = &mcspi1_dev_attr,
1433 };
1434
1435 /* mcspi2 */
1436 /* mcspi2 dev_attr */
1437 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1438         .num_chipselect = 2,
1439 };
1440
1441 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1442         .name           = "mcspi2",
1443         .class          = &dra7xx_mcspi_hwmod_class,
1444         .clkdm_name     = "l4per_clkdm",
1445         .main_clk       = "func_48m_fclk",
1446         .prcm = {
1447                 .omap4 = {
1448                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1449                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1450                         .modulemode   = MODULEMODE_SWCTRL,
1451                 },
1452         },
1453         .dev_attr       = &mcspi2_dev_attr,
1454 };
1455
1456 /* mcspi3 */
1457 /* mcspi3 dev_attr */
1458 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1459         .num_chipselect = 2,
1460 };
1461
1462 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1463         .name           = "mcspi3",
1464         .class          = &dra7xx_mcspi_hwmod_class,
1465         .clkdm_name     = "l4per_clkdm",
1466         .main_clk       = "func_48m_fclk",
1467         .prcm = {
1468                 .omap4 = {
1469                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1470                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1471                         .modulemode   = MODULEMODE_SWCTRL,
1472                 },
1473         },
1474         .dev_attr       = &mcspi3_dev_attr,
1475 };
1476
1477 /* mcspi4 */
1478 /* mcspi4 dev_attr */
1479 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1480         .num_chipselect = 1,
1481 };
1482
1483 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1484         .name           = "mcspi4",
1485         .class          = &dra7xx_mcspi_hwmod_class,
1486         .clkdm_name     = "l4per_clkdm",
1487         .main_clk       = "func_48m_fclk",
1488         .prcm = {
1489                 .omap4 = {
1490                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1491                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1492                         .modulemode   = MODULEMODE_SWCTRL,
1493                 },
1494         },
1495         .dev_attr       = &mcspi4_dev_attr,
1496 };
1497
1498 /*
1499  * 'mcasp' class
1500  *
1501  */
1502 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1503         .sysc_offs      = 0x0004,
1504         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1505         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1506         .sysc_fields    = &omap_hwmod_sysc_type3,
1507 };
1508
1509 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1510         .name   = "mcasp",
1511         .sysc   = &dra7xx_mcasp_sysc,
1512 };
1513
1514 /* mcasp1 */
1515 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1516         { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1517         { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1518 };
1519
1520 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1521         .name           = "mcasp1",
1522         .class          = &dra7xx_mcasp_hwmod_class,
1523         .clkdm_name     = "ipu_clkdm",
1524         .main_clk       = "mcasp1_aux_gfclk_mux",
1525         .flags          = HWMOD_OPT_CLKS_NEEDED,
1526         .prcm = {
1527                 .omap4 = {
1528                         .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1529                         .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1530                         .modulemode   = MODULEMODE_SWCTRL,
1531                 },
1532         },
1533         .opt_clks       = mcasp1_opt_clks,
1534         .opt_clks_cnt   = ARRAY_SIZE(mcasp1_opt_clks),
1535 };
1536
1537 /* mcasp2 */
1538 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1539         { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1540         { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1541 };
1542
1543 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1544         .name           = "mcasp2",
1545         .class          = &dra7xx_mcasp_hwmod_class,
1546         .clkdm_name     = "l4per2_clkdm",
1547         .main_clk       = "mcasp2_aux_gfclk_mux",
1548         .flags          = HWMOD_OPT_CLKS_NEEDED,
1549         .prcm = {
1550                 .omap4 = {
1551                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1552                         .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1553                         .modulemode   = MODULEMODE_SWCTRL,
1554                 },
1555         },
1556         .opt_clks       = mcasp2_opt_clks,
1557         .opt_clks_cnt   = ARRAY_SIZE(mcasp2_opt_clks),
1558 };
1559
1560 /* mcasp3 */
1561 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1562         { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1563 };
1564
1565 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1566         .name           = "mcasp3",
1567         .class          = &dra7xx_mcasp_hwmod_class,
1568         .clkdm_name     = "l4per2_clkdm",
1569         .main_clk       = "mcasp3_aux_gfclk_mux",
1570         .flags          = HWMOD_OPT_CLKS_NEEDED,
1571         .prcm = {
1572                 .omap4 = {
1573                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1574                         .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1575                         .modulemode   = MODULEMODE_SWCTRL,
1576                 },
1577         },
1578         .opt_clks       = mcasp3_opt_clks,
1579         .opt_clks_cnt   = ARRAY_SIZE(mcasp3_opt_clks),
1580 };
1581
1582 /* mcasp4 */
1583 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1584         { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1585 };
1586
1587 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1588         .name           = "mcasp4",
1589         .class          = &dra7xx_mcasp_hwmod_class,
1590         .clkdm_name     = "l4per2_clkdm",
1591         .main_clk       = "mcasp4_aux_gfclk_mux",
1592         .flags          = HWMOD_OPT_CLKS_NEEDED,
1593         .prcm = {
1594                 .omap4 = {
1595                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1596                         .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1597                         .modulemode   = MODULEMODE_SWCTRL,
1598                 },
1599         },
1600         .opt_clks       = mcasp4_opt_clks,
1601         .opt_clks_cnt   = ARRAY_SIZE(mcasp4_opt_clks),
1602 };
1603
1604 /* mcasp5 */
1605 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1606         { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1607 };
1608
1609 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1610         .name           = "mcasp5",
1611         .class          = &dra7xx_mcasp_hwmod_class,
1612         .clkdm_name     = "l4per2_clkdm",
1613         .main_clk       = "mcasp5_aux_gfclk_mux",
1614         .flags          = HWMOD_OPT_CLKS_NEEDED,
1615         .prcm = {
1616                 .omap4 = {
1617                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1618                         .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1619                         .modulemode   = MODULEMODE_SWCTRL,
1620                 },
1621         },
1622         .opt_clks       = mcasp5_opt_clks,
1623         .opt_clks_cnt   = ARRAY_SIZE(mcasp5_opt_clks),
1624 };
1625
1626 /* mcasp6 */
1627 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1628         { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1629 };
1630
1631 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1632         .name           = "mcasp6",
1633         .class          = &dra7xx_mcasp_hwmod_class,
1634         .clkdm_name     = "l4per2_clkdm",
1635         .main_clk       = "mcasp6_aux_gfclk_mux",
1636         .flags          = HWMOD_OPT_CLKS_NEEDED,
1637         .prcm = {
1638                 .omap4 = {
1639                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1640                         .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1641                         .modulemode   = MODULEMODE_SWCTRL,
1642                 },
1643         },
1644         .opt_clks       = mcasp6_opt_clks,
1645         .opt_clks_cnt   = ARRAY_SIZE(mcasp6_opt_clks),
1646 };
1647
1648 /* mcasp7 */
1649 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1650         { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1651 };
1652
1653 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1654         .name           = "mcasp7",
1655         .class          = &dra7xx_mcasp_hwmod_class,
1656         .clkdm_name     = "l4per2_clkdm",
1657         .main_clk       = "mcasp7_aux_gfclk_mux",
1658         .flags          = HWMOD_OPT_CLKS_NEEDED,
1659         .prcm = {
1660                 .omap4 = {
1661                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1662                         .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1663                         .modulemode   = MODULEMODE_SWCTRL,
1664                 },
1665         },
1666         .opt_clks       = mcasp7_opt_clks,
1667         .opt_clks_cnt   = ARRAY_SIZE(mcasp7_opt_clks),
1668 };
1669
1670 /* mcasp8 */
1671 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1672         { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1673 };
1674
1675 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1676         .name           = "mcasp8",
1677         .class          = &dra7xx_mcasp_hwmod_class,
1678         .clkdm_name     = "l4per2_clkdm",
1679         .main_clk       = "mcasp8_aux_gfclk_mux",
1680         .flags          = HWMOD_OPT_CLKS_NEEDED,
1681         .prcm = {
1682                 .omap4 = {
1683                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1684                         .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1685                         .modulemode   = MODULEMODE_SWCTRL,
1686                 },
1687         },
1688         .opt_clks       = mcasp8_opt_clks,
1689         .opt_clks_cnt   = ARRAY_SIZE(mcasp8_opt_clks),
1690 };
1691
1692 /*
1693  * 'mmc' class
1694  *
1695  */
1696
1697 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1698         .rev_offs       = 0x0000,
1699         .sysc_offs      = 0x0010,
1700         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1701                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1702                            SYSC_HAS_SOFTRESET),
1703         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1704                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1705                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1706         .sysc_fields    = &omap_hwmod_sysc_type2,
1707 };
1708
1709 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1710         .name   = "mmc",
1711         .sysc   = &dra7xx_mmc_sysc,
1712 };
1713
1714 /* mmc1 */
1715 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1716         { .role = "clk32k", .clk = "mmc1_clk32k" },
1717 };
1718
1719 /* mmc1 dev_attr */
1720 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1721         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1722 };
1723
1724 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1725         .name           = "mmc1",
1726         .class          = &dra7xx_mmc_hwmod_class,
1727         .clkdm_name     = "l3init_clkdm",
1728         .main_clk       = "mmc1_fclk_div",
1729         .prcm = {
1730                 .omap4 = {
1731                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1732                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1733                         .modulemode   = MODULEMODE_SWCTRL,
1734                 },
1735         },
1736         .opt_clks       = mmc1_opt_clks,
1737         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1738         .dev_attr       = &mmc1_dev_attr,
1739 };
1740
1741 /* mmc2 */
1742 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1743         { .role = "clk32k", .clk = "mmc2_clk32k" },
1744 };
1745
1746 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1747         .name           = "mmc2",
1748         .class          = &dra7xx_mmc_hwmod_class,
1749         .clkdm_name     = "l3init_clkdm",
1750         .main_clk       = "mmc2_fclk_div",
1751         .prcm = {
1752                 .omap4 = {
1753                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1754                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1755                         .modulemode   = MODULEMODE_SWCTRL,
1756                 },
1757         },
1758         .opt_clks       = mmc2_opt_clks,
1759         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1760 };
1761
1762 /* mmc3 */
1763 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1764         { .role = "clk32k", .clk = "mmc3_clk32k" },
1765 };
1766
1767 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1768         .name           = "mmc3",
1769         .class          = &dra7xx_mmc_hwmod_class,
1770         .clkdm_name     = "l4per_clkdm",
1771         .main_clk       = "mmc3_gfclk_div",
1772         .prcm = {
1773                 .omap4 = {
1774                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1775                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1776                         .modulemode   = MODULEMODE_SWCTRL,
1777                 },
1778         },
1779         .opt_clks       = mmc3_opt_clks,
1780         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1781 };
1782
1783 /* mmc4 */
1784 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1785         { .role = "clk32k", .clk = "mmc4_clk32k" },
1786 };
1787
1788 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1789         .name           = "mmc4",
1790         .class          = &dra7xx_mmc_hwmod_class,
1791         .clkdm_name     = "l4per_clkdm",
1792         .main_clk       = "mmc4_gfclk_div",
1793         .prcm = {
1794                 .omap4 = {
1795                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1796                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1797                         .modulemode   = MODULEMODE_SWCTRL,
1798                 },
1799         },
1800         .opt_clks       = mmc4_opt_clks,
1801         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1802 };
1803
1804 /*
1805  * 'mpu' class
1806  *
1807  */
1808
1809 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1810         .name   = "mpu",
1811 };
1812
1813 /* mpu */
1814 static struct omap_hwmod dra7xx_mpu_hwmod = {
1815         .name           = "mpu",
1816         .class          = &dra7xx_mpu_hwmod_class,
1817         .clkdm_name     = "mpu_clkdm",
1818         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1819         .main_clk       = "dpll_mpu_m2_ck",
1820         .prcm = {
1821                 .omap4 = {
1822                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1823                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1824                 },
1825         },
1826 };
1827
1828 /*
1829  * 'ocp2scp' class
1830  *
1831  */
1832
1833 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1834         .rev_offs       = 0x0000,
1835         .sysc_offs      = 0x0010,
1836         .syss_offs      = 0x0014,
1837         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1838                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1839         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1840         .sysc_fields    = &omap_hwmod_sysc_type1,
1841 };
1842
1843 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1844         .name   = "ocp2scp",
1845         .sysc   = &dra7xx_ocp2scp_sysc,
1846 };
1847
1848 /* ocp2scp1 */
1849 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1850         .name           = "ocp2scp1",
1851         .class          = &dra7xx_ocp2scp_hwmod_class,
1852         .clkdm_name     = "l3init_clkdm",
1853         .main_clk       = "l4_root_clk_div",
1854         .prcm = {
1855                 .omap4 = {
1856                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1857                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1858                         .modulemode   = MODULEMODE_HWCTRL,
1859                 },
1860         },
1861 };
1862
1863 /* ocp2scp3 */
1864 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1865         .name           = "ocp2scp3",
1866         .class          = &dra7xx_ocp2scp_hwmod_class,
1867         .clkdm_name     = "l3init_clkdm",
1868         .main_clk       = "l4_root_clk_div",
1869         .prcm = {
1870                 .omap4 = {
1871                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1872                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1873                         .modulemode   = MODULEMODE_HWCTRL,
1874                 },
1875         },
1876 };
1877
1878 /*
1879  * 'PCIE' class
1880  *
1881  */
1882
1883 /*
1884  * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1885  * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1886  * associated with an IP automatically leaving the driver to handle that
1887  * by itself. This does not work for PCIeSS which needs the reset lines
1888  * deasserted for the driver to start accessing registers.
1889  *
1890  * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1891  * lines after asserting them.
1892  */
1893 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1894 {
1895         int i;
1896
1897         for (i = 0; i < oh->rst_lines_cnt; i++) {
1898                 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1899                 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1900         }
1901
1902         return 0;
1903 }
1904
1905 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1906         .name   = "pcie",
1907         .reset  = dra7xx_pciess_reset,
1908 };
1909
1910 /* pcie1 */
1911 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1912         { .name = "pcie", .rst_shift = 0 },
1913 };
1914
1915 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1916         .name           = "pcie1",
1917         .class          = &dra7xx_pciess_hwmod_class,
1918         .clkdm_name     = "pcie_clkdm",
1919         .rst_lines      = dra7xx_pciess1_resets,
1920         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess1_resets),
1921         .main_clk       = "l4_root_clk_div",
1922         .prcm = {
1923                 .omap4 = {
1924                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1925                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1926                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1927                         .modulemode   = MODULEMODE_SWCTRL,
1928                 },
1929         },
1930 };
1931
1932 /* pcie2 */
1933 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1934         { .name = "pcie", .rst_shift = 1 },
1935 };
1936
1937 /* pcie2 */
1938 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1939         .name           = "pcie2",
1940         .class          = &dra7xx_pciess_hwmod_class,
1941         .clkdm_name     = "pcie_clkdm",
1942         .rst_lines      = dra7xx_pciess2_resets,
1943         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess2_resets),
1944         .main_clk       = "l4_root_clk_div",
1945         .prcm = {
1946                 .omap4 = {
1947                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1948                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1949                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1950                         .modulemode   = MODULEMODE_SWCTRL,
1951                 },
1952         },
1953 };
1954
1955 /*
1956  * 'qspi' class
1957  *
1958  */
1959
1960 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1961         .sysc_offs      = 0x0010,
1962         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1963         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1964                            SIDLE_SMART_WKUP),
1965         .sysc_fields    = &omap_hwmod_sysc_type2,
1966 };
1967
1968 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1969         .name   = "qspi",
1970         .sysc   = &dra7xx_qspi_sysc,
1971 };
1972
1973 /* qspi */
1974 static struct omap_hwmod dra7xx_qspi_hwmod = {
1975         .name           = "qspi",
1976         .class          = &dra7xx_qspi_hwmod_class,
1977         .clkdm_name     = "l4per2_clkdm",
1978         .main_clk       = "qspi_gfclk_div",
1979         .prcm = {
1980                 .omap4 = {
1981                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1982                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1983                         .modulemode   = MODULEMODE_SWCTRL,
1984                 },
1985         },
1986 };
1987
1988 /*
1989  * 'rtcss' class
1990  *
1991  */
1992 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1993         .sysc_offs      = 0x0078,
1994         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1995         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1996                            SIDLE_SMART_WKUP),
1997         .sysc_fields    = &omap_hwmod_sysc_type3,
1998 };
1999
2000 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
2001         .name   = "rtcss",
2002         .sysc   = &dra7xx_rtcss_sysc,
2003         .unlock = &omap_hwmod_rtc_unlock,
2004         .lock   = &omap_hwmod_rtc_lock,
2005 };
2006
2007 /* rtcss */
2008 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2009         .name           = "rtcss",
2010         .class          = &dra7xx_rtcss_hwmod_class,
2011         .clkdm_name     = "rtc_clkdm",
2012         .main_clk       = "sys_32k_ck",
2013         .prcm = {
2014                 .omap4 = {
2015                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2016                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2017                         .modulemode   = MODULEMODE_SWCTRL,
2018                 },
2019         },
2020 };
2021
2022 /*
2023  * 'sata' class
2024  *
2025  */
2026
2027 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2028         .sysc_offs      = 0x0000,
2029         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2030         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2031                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2032                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2033         .sysc_fields    = &omap_hwmod_sysc_type2,
2034 };
2035
2036 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2037         .name   = "sata",
2038         .sysc   = &dra7xx_sata_sysc,
2039 };
2040
2041 /* sata */
2042
2043 static struct omap_hwmod dra7xx_sata_hwmod = {
2044         .name           = "sata",
2045         .class          = &dra7xx_sata_hwmod_class,
2046         .clkdm_name     = "l3init_clkdm",
2047         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2048         .main_clk       = "func_48m_fclk",
2049         .mpu_rt_idx     = 1,
2050         .prcm = {
2051                 .omap4 = {
2052                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2053                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2054                         .modulemode   = MODULEMODE_SWCTRL,
2055                 },
2056         },
2057 };
2058
2059 /*
2060  * 'smartreflex' class
2061  *
2062  */
2063
2064 /* The IP is not compliant to type1 / type2 scheme */
2065 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2066         .sidle_shift    = 24,
2067         .enwkup_shift   = 26,
2068 };
2069
2070 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2071         .sysc_offs      = 0x0038,
2072         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2073         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2074                            SIDLE_SMART_WKUP),
2075         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2076 };
2077
2078 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2079         .name   = "smartreflex",
2080         .sysc   = &dra7xx_smartreflex_sysc,
2081         .rev    = 2,
2082 };
2083
2084 /* smartreflex_core */
2085 /* smartreflex_core dev_attr */
2086 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2087         .sensor_voltdm_name     = "core",
2088 };
2089
2090 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2091         .name           = "smartreflex_core",
2092         .class          = &dra7xx_smartreflex_hwmod_class,
2093         .clkdm_name     = "coreaon_clkdm",
2094         .main_clk       = "wkupaon_iclk_mux",
2095         .prcm = {
2096                 .omap4 = {
2097                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2098                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2099                         .modulemode   = MODULEMODE_SWCTRL,
2100                 },
2101         },
2102         .dev_attr       = &smartreflex_core_dev_attr,
2103 };
2104
2105 /* smartreflex_mpu */
2106 /* smartreflex_mpu dev_attr */
2107 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2108         .sensor_voltdm_name     = "mpu",
2109 };
2110
2111 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2112         .name           = "smartreflex_mpu",
2113         .class          = &dra7xx_smartreflex_hwmod_class,
2114         .clkdm_name     = "coreaon_clkdm",
2115         .main_clk       = "wkupaon_iclk_mux",
2116         .prcm = {
2117                 .omap4 = {
2118                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2119                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2120                         .modulemode   = MODULEMODE_SWCTRL,
2121                 },
2122         },
2123         .dev_attr       = &smartreflex_mpu_dev_attr,
2124 };
2125
2126 /*
2127  * 'spinlock' class
2128  *
2129  */
2130
2131 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2132         .rev_offs       = 0x0000,
2133         .sysc_offs      = 0x0010,
2134         .syss_offs      = 0x0014,
2135         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2136                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2137                            SYSS_HAS_RESET_STATUS),
2138         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2139         .sysc_fields    = &omap_hwmod_sysc_type1,
2140 };
2141
2142 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2143         .name   = "spinlock",
2144         .sysc   = &dra7xx_spinlock_sysc,
2145 };
2146
2147 /* spinlock */
2148 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2149         .name           = "spinlock",
2150         .class          = &dra7xx_spinlock_hwmod_class,
2151         .clkdm_name     = "l4cfg_clkdm",
2152         .main_clk       = "l3_iclk_div",
2153         .prcm = {
2154                 .omap4 = {
2155                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2156                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2157                 },
2158         },
2159 };
2160
2161 /*
2162  * 'timer' class
2163  *
2164  * This class contains several variants: ['timer_1ms', 'timer_secure',
2165  * 'timer']
2166  */
2167
2168 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2169         .rev_offs       = 0x0000,
2170         .sysc_offs      = 0x0010,
2171         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2172                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2173         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2174                            SIDLE_SMART_WKUP),
2175         .sysc_fields    = &omap_hwmod_sysc_type2,
2176 };
2177
2178 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2179         .name   = "timer",
2180         .sysc   = &dra7xx_timer_1ms_sysc,
2181 };
2182
2183 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2184         .rev_offs       = 0x0000,
2185         .sysc_offs      = 0x0010,
2186         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2187                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2188         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2189                            SIDLE_SMART_WKUP),
2190         .sysc_fields    = &omap_hwmod_sysc_type2,
2191 };
2192
2193 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2194         .name   = "timer",
2195         .sysc   = &dra7xx_timer_sysc,
2196 };
2197
2198 /* timer1 */
2199 static struct omap_hwmod dra7xx_timer1_hwmod = {
2200         .name           = "timer1",
2201         .class          = &dra7xx_timer_1ms_hwmod_class,
2202         .clkdm_name     = "wkupaon_clkdm",
2203         .main_clk       = "timer1_gfclk_mux",
2204         .prcm = {
2205                 .omap4 = {
2206                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2207                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2208                         .modulemode   = MODULEMODE_SWCTRL,
2209                 },
2210         },
2211 };
2212
2213 /* timer2 */
2214 static struct omap_hwmod dra7xx_timer2_hwmod = {
2215         .name           = "timer2",
2216         .class          = &dra7xx_timer_1ms_hwmod_class,
2217         .clkdm_name     = "l4per_clkdm",
2218         .main_clk       = "timer2_gfclk_mux",
2219         .prcm = {
2220                 .omap4 = {
2221                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2222                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2223                         .modulemode   = MODULEMODE_SWCTRL,
2224                 },
2225         },
2226 };
2227
2228 /* timer3 */
2229 static struct omap_hwmod dra7xx_timer3_hwmod = {
2230         .name           = "timer3",
2231         .class          = &dra7xx_timer_hwmod_class,
2232         .clkdm_name     = "l4per_clkdm",
2233         .main_clk       = "timer3_gfclk_mux",
2234         .prcm = {
2235                 .omap4 = {
2236                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2237                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2238                         .modulemode   = MODULEMODE_SWCTRL,
2239                 },
2240         },
2241 };
2242
2243 /* timer4 */
2244 static struct omap_hwmod dra7xx_timer4_hwmod = {
2245         .name           = "timer4",
2246         .class          = &dra7xx_timer_hwmod_class,
2247         .clkdm_name     = "l4per_clkdm",
2248         .main_clk       = "timer4_gfclk_mux",
2249         .prcm = {
2250                 .omap4 = {
2251                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2252                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2253                         .modulemode   = MODULEMODE_SWCTRL,
2254                 },
2255         },
2256 };
2257
2258 /* timer5 */
2259 static struct omap_hwmod dra7xx_timer5_hwmod = {
2260         .name           = "timer5",
2261         .class          = &dra7xx_timer_hwmod_class,
2262         .clkdm_name     = "ipu_clkdm",
2263         .main_clk       = "timer5_gfclk_mux",
2264         .prcm = {
2265                 .omap4 = {
2266                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2267                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2268                         .modulemode   = MODULEMODE_SWCTRL,
2269                 },
2270         },
2271 };
2272
2273 /* timer6 */
2274 static struct omap_hwmod dra7xx_timer6_hwmod = {
2275         .name           = "timer6",
2276         .class          = &dra7xx_timer_hwmod_class,
2277         .clkdm_name     = "ipu_clkdm",
2278         .main_clk       = "timer6_gfclk_mux",
2279         .prcm = {
2280                 .omap4 = {
2281                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2282                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2283                         .modulemode   = MODULEMODE_SWCTRL,
2284                 },
2285         },
2286 };
2287
2288 /* timer7 */
2289 static struct omap_hwmod dra7xx_timer7_hwmod = {
2290         .name           = "timer7",
2291         .class          = &dra7xx_timer_hwmod_class,
2292         .clkdm_name     = "ipu_clkdm",
2293         .main_clk       = "timer7_gfclk_mux",
2294         .prcm = {
2295                 .omap4 = {
2296                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2297                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2298                         .modulemode   = MODULEMODE_SWCTRL,
2299                 },
2300         },
2301 };
2302
2303 /* timer8 */
2304 static struct omap_hwmod dra7xx_timer8_hwmod = {
2305         .name           = "timer8",
2306         .class          = &dra7xx_timer_hwmod_class,
2307         .clkdm_name     = "ipu_clkdm",
2308         .main_clk       = "timer8_gfclk_mux",
2309         .prcm = {
2310                 .omap4 = {
2311                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2312                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2313                         .modulemode   = MODULEMODE_SWCTRL,
2314                 },
2315         },
2316 };
2317
2318 /* timer9 */
2319 static struct omap_hwmod dra7xx_timer9_hwmod = {
2320         .name           = "timer9",
2321         .class          = &dra7xx_timer_hwmod_class,
2322         .clkdm_name     = "l4per_clkdm",
2323         .main_clk       = "timer9_gfclk_mux",
2324         .prcm = {
2325                 .omap4 = {
2326                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2327                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2328                         .modulemode   = MODULEMODE_SWCTRL,
2329                 },
2330         },
2331 };
2332
2333 /* timer10 */
2334 static struct omap_hwmod dra7xx_timer10_hwmod = {
2335         .name           = "timer10",
2336         .class          = &dra7xx_timer_1ms_hwmod_class,
2337         .clkdm_name     = "l4per_clkdm",
2338         .main_clk       = "timer10_gfclk_mux",
2339         .prcm = {
2340                 .omap4 = {
2341                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2342                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2343                         .modulemode   = MODULEMODE_SWCTRL,
2344                 },
2345         },
2346 };
2347
2348 /* timer11 */
2349 static struct omap_hwmod dra7xx_timer11_hwmod = {
2350         .name           = "timer11",
2351         .class          = &dra7xx_timer_hwmod_class,
2352         .clkdm_name     = "l4per_clkdm",
2353         .main_clk       = "timer11_gfclk_mux",
2354         .prcm = {
2355                 .omap4 = {
2356                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2357                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2358                         .modulemode   = MODULEMODE_SWCTRL,
2359                 },
2360         },
2361 };
2362
2363 /* timer12 */
2364 static struct omap_hwmod dra7xx_timer12_hwmod = {
2365         .name           = "timer12",
2366         .class          = &dra7xx_timer_hwmod_class,
2367         .clkdm_name     = "wkupaon_clkdm",
2368         .main_clk       = "secure_32k_clk_src_ck",
2369         .prcm = {
2370                 .omap4 = {
2371                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2372                         .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2373                 },
2374         },
2375 };
2376
2377 /* timer13 */
2378 static struct omap_hwmod dra7xx_timer13_hwmod = {
2379         .name           = "timer13",
2380         .class          = &dra7xx_timer_hwmod_class,
2381         .clkdm_name     = "l4per3_clkdm",
2382         .main_clk       = "timer13_gfclk_mux",
2383         .prcm = {
2384                 .omap4 = {
2385                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2386                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2387                         .modulemode   = MODULEMODE_SWCTRL,
2388                 },
2389         },
2390 };
2391
2392 /* timer14 */
2393 static struct omap_hwmod dra7xx_timer14_hwmod = {
2394         .name           = "timer14",
2395         .class          = &dra7xx_timer_hwmod_class,
2396         .clkdm_name     = "l4per3_clkdm",
2397         .main_clk       = "timer14_gfclk_mux",
2398         .prcm = {
2399                 .omap4 = {
2400                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2401                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2402                         .modulemode   = MODULEMODE_SWCTRL,
2403                 },
2404         },
2405 };
2406
2407 /* timer15 */
2408 static struct omap_hwmod dra7xx_timer15_hwmod = {
2409         .name           = "timer15",
2410         .class          = &dra7xx_timer_hwmod_class,
2411         .clkdm_name     = "l4per3_clkdm",
2412         .main_clk       = "timer15_gfclk_mux",
2413         .prcm = {
2414                 .omap4 = {
2415                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2416                         .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2417                         .modulemode   = MODULEMODE_SWCTRL,
2418                 },
2419         },
2420 };
2421
2422 /* timer16 */
2423 static struct omap_hwmod dra7xx_timer16_hwmod = {
2424         .name           = "timer16",
2425         .class          = &dra7xx_timer_hwmod_class,
2426         .clkdm_name     = "l4per3_clkdm",
2427         .main_clk       = "timer16_gfclk_mux",
2428         .prcm = {
2429                 .omap4 = {
2430                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2431                         .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2432                         .modulemode   = MODULEMODE_SWCTRL,
2433                 },
2434         },
2435 };
2436
2437 /*
2438  * 'uart' class
2439  *
2440  */
2441
2442 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2443         .rev_offs       = 0x0050,
2444         .sysc_offs      = 0x0054,
2445         .syss_offs      = 0x0058,
2446         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2447                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2448                            SYSS_HAS_RESET_STATUS),
2449         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2450                            SIDLE_SMART_WKUP),
2451         .sysc_fields    = &omap_hwmod_sysc_type1,
2452 };
2453
2454 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2455         .name   = "uart",
2456         .sysc   = &dra7xx_uart_sysc,
2457 };
2458
2459 /* uart1 */
2460 static struct omap_hwmod dra7xx_uart1_hwmod = {
2461         .name           = "uart1",
2462         .class          = &dra7xx_uart_hwmod_class,
2463         .clkdm_name     = "l4per_clkdm",
2464         .main_clk       = "uart1_gfclk_mux",
2465         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2466         .prcm = {
2467                 .omap4 = {
2468                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2469                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2470                         .modulemode   = MODULEMODE_SWCTRL,
2471                 },
2472         },
2473 };
2474
2475 /* uart2 */
2476 static struct omap_hwmod dra7xx_uart2_hwmod = {
2477         .name           = "uart2",
2478         .class          = &dra7xx_uart_hwmod_class,
2479         .clkdm_name     = "l4per_clkdm",
2480         .main_clk       = "uart2_gfclk_mux",
2481         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2482         .prcm = {
2483                 .omap4 = {
2484                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2485                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2486                         .modulemode   = MODULEMODE_SWCTRL,
2487                 },
2488         },
2489 };
2490
2491 /* uart3 */
2492 static struct omap_hwmod dra7xx_uart3_hwmod = {
2493         .name           = "uart3",
2494         .class          = &dra7xx_uart_hwmod_class,
2495         .clkdm_name     = "l4per_clkdm",
2496         .main_clk       = "uart3_gfclk_mux",
2497         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2498         .prcm = {
2499                 .omap4 = {
2500                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2501                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2502                         .modulemode   = MODULEMODE_SWCTRL,
2503                 },
2504         },
2505 };
2506
2507 /* uart4 */
2508 static struct omap_hwmod dra7xx_uart4_hwmod = {
2509         .name           = "uart4",
2510         .class          = &dra7xx_uart_hwmod_class,
2511         .clkdm_name     = "l4per_clkdm",
2512         .main_clk       = "uart4_gfclk_mux",
2513         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2514         .prcm = {
2515                 .omap4 = {
2516                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2517                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2518                         .modulemode   = MODULEMODE_SWCTRL,
2519                 },
2520         },
2521 };
2522
2523 /* uart5 */
2524 static struct omap_hwmod dra7xx_uart5_hwmod = {
2525         .name           = "uart5",
2526         .class          = &dra7xx_uart_hwmod_class,
2527         .clkdm_name     = "l4per_clkdm",
2528         .main_clk       = "uart5_gfclk_mux",
2529         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2530         .prcm = {
2531                 .omap4 = {
2532                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2533                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2534                         .modulemode   = MODULEMODE_SWCTRL,
2535                 },
2536         },
2537 };
2538
2539 /* uart6 */
2540 static struct omap_hwmod dra7xx_uart6_hwmod = {
2541         .name           = "uart6",
2542         .class          = &dra7xx_uart_hwmod_class,
2543         .clkdm_name     = "ipu_clkdm",
2544         .main_clk       = "uart6_gfclk_mux",
2545         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2546         .prcm = {
2547                 .omap4 = {
2548                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2549                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2550                         .modulemode   = MODULEMODE_SWCTRL,
2551                 },
2552         },
2553 };
2554
2555 /* uart7 */
2556 static struct omap_hwmod dra7xx_uart7_hwmod = {
2557         .name           = "uart7",
2558         .class          = &dra7xx_uart_hwmod_class,
2559         .clkdm_name     = "l4per2_clkdm",
2560         .main_clk       = "uart7_gfclk_mux",
2561         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2562         .prcm = {
2563                 .omap4 = {
2564                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2565                         .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2566                         .modulemode   = MODULEMODE_SWCTRL,
2567                 },
2568         },
2569 };
2570
2571 /* uart8 */
2572 static struct omap_hwmod dra7xx_uart8_hwmod = {
2573         .name           = "uart8",
2574         .class          = &dra7xx_uart_hwmod_class,
2575         .clkdm_name     = "l4per2_clkdm",
2576         .main_clk       = "uart8_gfclk_mux",
2577         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2578         .prcm = {
2579                 .omap4 = {
2580                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2581                         .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2582                         .modulemode   = MODULEMODE_SWCTRL,
2583                 },
2584         },
2585 };
2586
2587 /* uart9 */
2588 static struct omap_hwmod dra7xx_uart9_hwmod = {
2589         .name           = "uart9",
2590         .class          = &dra7xx_uart_hwmod_class,
2591         .clkdm_name     = "l4per2_clkdm",
2592         .main_clk       = "uart9_gfclk_mux",
2593         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2594         .prcm = {
2595                 .omap4 = {
2596                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2597                         .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2598                         .modulemode   = MODULEMODE_SWCTRL,
2599                 },
2600         },
2601 };
2602
2603 /* uart10 */
2604 static struct omap_hwmod dra7xx_uart10_hwmod = {
2605         .name           = "uart10",
2606         .class          = &dra7xx_uart_hwmod_class,
2607         .clkdm_name     = "wkupaon_clkdm",
2608         .main_clk       = "uart10_gfclk_mux",
2609         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2610         .prcm = {
2611                 .omap4 = {
2612                         .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2613                         .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2614                         .modulemode   = MODULEMODE_SWCTRL,
2615                 },
2616         },
2617 };
2618
2619 /* DES (the 'P' (public) device) */
2620 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2621         .rev_offs       = 0x0030,
2622         .sysc_offs      = 0x0034,
2623         .syss_offs      = 0x0038,
2624         .sysc_flags     = SYSS_HAS_RESET_STATUS,
2625 };
2626
2627 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2628         .name   = "des",
2629         .sysc   = &dra7xx_des_sysc,
2630 };
2631
2632 /* DES */
2633 static struct omap_hwmod dra7xx_des_hwmod = {
2634         .name           = "des",
2635         .class          = &dra7xx_des_hwmod_class,
2636         .clkdm_name     = "l4sec_clkdm",
2637         .main_clk       = "l3_iclk_div",
2638         .prcm = {
2639                 .omap4 = {
2640                         .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2641                         .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2642                         .modulemode   = MODULEMODE_HWCTRL,
2643                 },
2644         },
2645 };
2646
2647 /* rng */
2648 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2649         .rev_offs       = 0x1fe0,
2650         .sysc_offs      = 0x1fe4,
2651         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2652         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
2653         .sysc_fields    = &omap_hwmod_sysc_type1,
2654 };
2655
2656 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2657         .name           = "rng",
2658         .sysc           = &dra7xx_rng_sysc,
2659 };
2660
2661 static struct omap_hwmod dra7xx_rng_hwmod = {
2662         .name           = "rng",
2663         .class          = &dra7xx_rng_hwmod_class,
2664         .flags          = HWMOD_SWSUP_SIDLE,
2665         .clkdm_name     = "l4sec_clkdm",
2666         .prcm = {
2667                 .omap4 = {
2668                         .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2669                         .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2670                         .modulemode   = MODULEMODE_HWCTRL,
2671                 },
2672         },
2673 };
2674
2675 /*
2676  * 'usb_otg_ss' class
2677  *
2678  */
2679
2680 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2681         .rev_offs       = 0x0000,
2682         .sysc_offs      = 0x0010,
2683         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2684                            SYSC_HAS_SIDLEMODE),
2685         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2686                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2687                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2688         .sysc_fields    = &omap_hwmod_sysc_type2,
2689 };
2690
2691 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2692         .name   = "usb_otg_ss",
2693         .sysc   = &dra7xx_usb_otg_ss_sysc,
2694 };
2695
2696 /* usb_otg_ss1 */
2697 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2698         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2699 };
2700
2701 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2702         .name           = "usb_otg_ss1",
2703         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2704         .clkdm_name     = "l3init_clkdm",
2705         .main_clk       = "dpll_core_h13x2_ck",
2706         .flags          = HWMOD_CLKDM_NOAUTO,
2707         .prcm = {
2708                 .omap4 = {
2709                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2710                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2711                         .modulemode   = MODULEMODE_HWCTRL,
2712                 },
2713         },
2714         .opt_clks       = usb_otg_ss1_opt_clks,
2715         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2716 };
2717
2718 /* usb_otg_ss2 */
2719 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2720         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2721 };
2722
2723 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2724         .name           = "usb_otg_ss2",
2725         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2726         .clkdm_name     = "l3init_clkdm",
2727         .main_clk       = "dpll_core_h13x2_ck",
2728         .flags          = HWMOD_CLKDM_NOAUTO,
2729         .prcm = {
2730                 .omap4 = {
2731                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2732                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2733                         .modulemode   = MODULEMODE_HWCTRL,
2734                 },
2735         },
2736         .opt_clks       = usb_otg_ss2_opt_clks,
2737         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2738 };
2739
2740 /* usb_otg_ss3 */
2741 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2742         .name           = "usb_otg_ss3",
2743         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2744         .clkdm_name     = "l3init_clkdm",
2745         .main_clk       = "dpll_core_h13x2_ck",
2746         .prcm = {
2747                 .omap4 = {
2748                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2749                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2750                         .modulemode   = MODULEMODE_HWCTRL,
2751                 },
2752         },
2753 };
2754
2755 /* usb_otg_ss4 */
2756 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2757         .name           = "usb_otg_ss4",
2758         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2759         .clkdm_name     = "l3init_clkdm",
2760         .main_clk       = "dpll_core_h13x2_ck",
2761         .prcm = {
2762                 .omap4 = {
2763                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2764                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2765                         .modulemode   = MODULEMODE_HWCTRL,
2766                 },
2767         },
2768 };
2769
2770 /*
2771  * 'vcp' class
2772  *
2773  */
2774
2775 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2776         .name   = "vcp",
2777 };
2778
2779 /* vcp1 */
2780 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2781         .name           = "vcp1",
2782         .class          = &dra7xx_vcp_hwmod_class,
2783         .clkdm_name     = "l3main1_clkdm",
2784         .main_clk       = "l3_iclk_div",
2785         .prcm = {
2786                 .omap4 = {
2787                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2788                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2789                 },
2790         },
2791 };
2792
2793 /* vcp2 */
2794 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2795         .name           = "vcp2",
2796         .class          = &dra7xx_vcp_hwmod_class,
2797         .clkdm_name     = "l3main1_clkdm",
2798         .main_clk       = "l3_iclk_div",
2799         .prcm = {
2800                 .omap4 = {
2801                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2802                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2803                 },
2804         },
2805 };
2806
2807 /*
2808  * 'wd_timer' class
2809  *
2810  */
2811
2812 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2813         .rev_offs       = 0x0000,
2814         .sysc_offs      = 0x0010,
2815         .syss_offs      = 0x0014,
2816         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2817                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2818         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2819                            SIDLE_SMART_WKUP),
2820         .sysc_fields    = &omap_hwmod_sysc_type1,
2821 };
2822
2823 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2824         .name           = "wd_timer",
2825         .sysc           = &dra7xx_wd_timer_sysc,
2826         .pre_shutdown   = &omap2_wd_timer_disable,
2827         .reset          = &omap2_wd_timer_reset,
2828 };
2829
2830 /* wd_timer2 */
2831 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2832         .name           = "wd_timer2",
2833         .class          = &dra7xx_wd_timer_hwmod_class,
2834         .clkdm_name     = "wkupaon_clkdm",
2835         .main_clk       = "sys_32k_ck",
2836         .prcm = {
2837                 .omap4 = {
2838                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2839                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2840                         .modulemode   = MODULEMODE_SWCTRL,
2841                 },
2842         },
2843 };
2844
2845
2846 /*
2847  * Interfaces
2848  */
2849
2850 /* l3_main_1 -> dmm */
2851 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2852         .master         = &dra7xx_l3_main_1_hwmod,
2853         .slave          = &dra7xx_dmm_hwmod,
2854         .clk            = "l3_iclk_div",
2855         .user           = OCP_USER_SDMA,
2856 };
2857
2858 /* l3_main_2 -> l3_instr */
2859 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2860         .master         = &dra7xx_l3_main_2_hwmod,
2861         .slave          = &dra7xx_l3_instr_hwmod,
2862         .clk            = "l3_iclk_div",
2863         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2864 };
2865
2866 /* l4_cfg -> l3_main_1 */
2867 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2868         .master         = &dra7xx_l4_cfg_hwmod,
2869         .slave          = &dra7xx_l3_main_1_hwmod,
2870         .clk            = "l3_iclk_div",
2871         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2872 };
2873
2874 /* mpu -> l3_main_1 */
2875 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2876         .master         = &dra7xx_mpu_hwmod,
2877         .slave          = &dra7xx_l3_main_1_hwmod,
2878         .clk            = "l3_iclk_div",
2879         .user           = OCP_USER_MPU,
2880 };
2881
2882 /* l3_main_1 -> l3_main_2 */
2883 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2884         .master         = &dra7xx_l3_main_1_hwmod,
2885         .slave          = &dra7xx_l3_main_2_hwmod,
2886         .clk            = "l3_iclk_div",
2887         .user           = OCP_USER_MPU,
2888 };
2889
2890 /* l4_cfg -> l3_main_2 */
2891 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2892         .master         = &dra7xx_l4_cfg_hwmod,
2893         .slave          = &dra7xx_l3_main_2_hwmod,
2894         .clk            = "l3_iclk_div",
2895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2896 };
2897
2898 /* l3_main_1 -> l4_cfg */
2899 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2900         .master         = &dra7xx_l3_main_1_hwmod,
2901         .slave          = &dra7xx_l4_cfg_hwmod,
2902         .clk            = "l3_iclk_div",
2903         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2904 };
2905
2906 /* l3_main_1 -> l4_per1 */
2907 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2908         .master         = &dra7xx_l3_main_1_hwmod,
2909         .slave          = &dra7xx_l4_per1_hwmod,
2910         .clk            = "l3_iclk_div",
2911         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2912 };
2913
2914 /* l3_main_1 -> l4_per2 */
2915 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2916         .master         = &dra7xx_l3_main_1_hwmod,
2917         .slave          = &dra7xx_l4_per2_hwmod,
2918         .clk            = "l3_iclk_div",
2919         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2920 };
2921
2922 /* l3_main_1 -> l4_per3 */
2923 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2924         .master         = &dra7xx_l3_main_1_hwmod,
2925         .slave          = &dra7xx_l4_per3_hwmod,
2926         .clk            = "l3_iclk_div",
2927         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2928 };
2929
2930 /* l3_main_1 -> l4_wkup */
2931 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2932         .master         = &dra7xx_l3_main_1_hwmod,
2933         .slave          = &dra7xx_l4_wkup_hwmod,
2934         .clk            = "wkupaon_iclk_mux",
2935         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2936 };
2937
2938 /* l4_per2 -> atl */
2939 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2940         .master         = &dra7xx_l4_per2_hwmod,
2941         .slave          = &dra7xx_atl_hwmod,
2942         .clk            = "l3_iclk_div",
2943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2944 };
2945
2946 /* l3_main_1 -> bb2d */
2947 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2948         .master         = &dra7xx_l3_main_1_hwmod,
2949         .slave          = &dra7xx_bb2d_hwmod,
2950         .clk            = "l3_iclk_div",
2951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2952 };
2953
2954 /* l4_wkup -> counter_32k */
2955 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2956         .master         = &dra7xx_l4_wkup_hwmod,
2957         .slave          = &dra7xx_counter_32k_hwmod,
2958         .clk            = "wkupaon_iclk_mux",
2959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2960 };
2961
2962 /* l4_wkup -> ctrl_module_wkup */
2963 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2964         .master         = &dra7xx_l4_wkup_hwmod,
2965         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
2966         .clk            = "wkupaon_iclk_mux",
2967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2968 };
2969
2970 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2971         .master         = &dra7xx_l4_per2_hwmod,
2972         .slave          = &dra7xx_gmac_hwmod,
2973         .clk            = "dpll_gmac_ck",
2974         .user           = OCP_USER_MPU,
2975 };
2976
2977 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2978         .master         = &dra7xx_gmac_hwmod,
2979         .slave          = &dra7xx_mdio_hwmod,
2980         .user           = OCP_USER_MPU,
2981 };
2982
2983 /* l4_wkup -> dcan1 */
2984 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2985         .master         = &dra7xx_l4_wkup_hwmod,
2986         .slave          = &dra7xx_dcan1_hwmod,
2987         .clk            = "wkupaon_iclk_mux",
2988         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2989 };
2990
2991 /* l4_per2 -> dcan2 */
2992 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2993         .master         = &dra7xx_l4_per2_hwmod,
2994         .slave          = &dra7xx_dcan2_hwmod,
2995         .clk            = "l3_iclk_div",
2996         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2997 };
2998
2999 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
3000         {
3001                 .pa_start       = 0x4a056000,
3002                 .pa_end         = 0x4a056fff,
3003                 .flags          = ADDR_TYPE_RT
3004         },
3005         { }
3006 };
3007
3008 /* l4_cfg -> dma_system */
3009 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
3010         .master         = &dra7xx_l4_cfg_hwmod,
3011         .slave          = &dra7xx_dma_system_hwmod,
3012         .clk            = "l3_iclk_div",
3013         .addr           = dra7xx_dma_system_addrs,
3014         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3015 };
3016
3017 /* l3_main_1 -> tpcc */
3018 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
3019         .master         = &dra7xx_l3_main_1_hwmod,
3020         .slave          = &dra7xx_tpcc_hwmod,
3021         .clk            = "l3_iclk_div",
3022         .user           = OCP_USER_MPU,
3023 };
3024
3025 /* l3_main_1 -> tptc0 */
3026 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
3027         .master         = &dra7xx_l3_main_1_hwmod,
3028         .slave          = &dra7xx_tptc0_hwmod,
3029         .clk            = "l3_iclk_div",
3030         .user           = OCP_USER_MPU,
3031 };
3032
3033 /* l3_main_1 -> tptc1 */
3034 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
3035         .master         = &dra7xx_l3_main_1_hwmod,
3036         .slave          = &dra7xx_tptc1_hwmod,
3037         .clk            = "l3_iclk_div",
3038         .user           = OCP_USER_MPU,
3039 };
3040
3041 /* l3_main_1 -> dss */
3042 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3043         .master         = &dra7xx_l3_main_1_hwmod,
3044         .slave          = &dra7xx_dss_hwmod,
3045         .clk            = "l3_iclk_div",
3046         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3047 };
3048
3049 /* l3_main_1 -> dispc */
3050 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3051         .master         = &dra7xx_l3_main_1_hwmod,
3052         .slave          = &dra7xx_dss_dispc_hwmod,
3053         .clk            = "l3_iclk_div",
3054         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3055 };
3056
3057 /* l3_main_1 -> dispc */
3058 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3059         .master         = &dra7xx_l3_main_1_hwmod,
3060         .slave          = &dra7xx_dss_hdmi_hwmod,
3061         .clk            = "l3_iclk_div",
3062         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3063 };
3064
3065 /* l3_main_1 -> aes1 */
3066 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
3067         .master         = &dra7xx_l3_main_1_hwmod,
3068         .slave          = &dra7xx_aes1_hwmod,
3069         .clk            = "l3_iclk_div",
3070         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3071 };
3072
3073 /* l3_main_1 -> aes2 */
3074 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3075         .master         = &dra7xx_l3_main_1_hwmod,
3076         .slave          = &dra7xx_aes2_hwmod,
3077         .clk            = "l3_iclk_div",
3078         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3079 };
3080
3081 /* l3_main_1 -> sha0 */
3082 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3083         .master         = &dra7xx_l3_main_1_hwmod,
3084         .slave          = &dra7xx_sha0_hwmod,
3085         .clk            = "l3_iclk_div",
3086         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3087 };
3088
3089 /* l4_per2 -> mcasp1 */
3090 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
3091         .master         = &dra7xx_l4_per2_hwmod,
3092         .slave          = &dra7xx_mcasp1_hwmod,
3093         .clk            = "l4_root_clk_div",
3094         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3095 };
3096
3097 /* l3_main_1 -> mcasp1 */
3098 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
3099         .master         = &dra7xx_l3_main_1_hwmod,
3100         .slave          = &dra7xx_mcasp1_hwmod,
3101         .clk            = "l3_iclk_div",
3102         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3103 };
3104
3105 /* l4_per2 -> mcasp2 */
3106 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3107         .master         = &dra7xx_l4_per2_hwmod,
3108         .slave          = &dra7xx_mcasp2_hwmod,
3109         .clk            = "l4_root_clk_div",
3110         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3111 };
3112
3113 /* l3_main_1 -> mcasp2 */
3114 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
3115         .master         = &dra7xx_l3_main_1_hwmod,
3116         .slave          = &dra7xx_mcasp2_hwmod,
3117         .clk            = "l3_iclk_div",
3118         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3119 };
3120
3121 /* l4_per2 -> mcasp3 */
3122 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3123         .master         = &dra7xx_l4_per2_hwmod,
3124         .slave          = &dra7xx_mcasp3_hwmod,
3125         .clk            = "l4_root_clk_div",
3126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3127 };
3128
3129 /* l3_main_1 -> mcasp3 */
3130 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
3131         .master         = &dra7xx_l3_main_1_hwmod,
3132         .slave          = &dra7xx_mcasp3_hwmod,
3133         .clk            = "l3_iclk_div",
3134         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3135 };
3136
3137 /* l4_per2 -> mcasp4 */
3138 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
3139         .master         = &dra7xx_l4_per2_hwmod,
3140         .slave          = &dra7xx_mcasp4_hwmod,
3141         .clk            = "l4_root_clk_div",
3142         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3143 };
3144
3145 /* l4_per2 -> mcasp5 */
3146 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
3147         .master         = &dra7xx_l4_per2_hwmod,
3148         .slave          = &dra7xx_mcasp5_hwmod,
3149         .clk            = "l4_root_clk_div",
3150         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3151 };
3152
3153 /* l4_per2 -> mcasp6 */
3154 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3155         .master         = &dra7xx_l4_per2_hwmod,
3156         .slave          = &dra7xx_mcasp6_hwmod,
3157         .clk            = "l4_root_clk_div",
3158         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3159 };
3160
3161 /* l4_per2 -> mcasp7 */
3162 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3163         .master         = &dra7xx_l4_per2_hwmod,
3164         .slave          = &dra7xx_mcasp7_hwmod,
3165         .clk            = "l4_root_clk_div",
3166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3167 };
3168
3169 /* l4_per2 -> mcasp8 */
3170 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3171         .master         = &dra7xx_l4_per2_hwmod,
3172         .slave          = &dra7xx_mcasp8_hwmod,
3173         .clk            = "l4_root_clk_div",
3174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3175 };
3176
3177 /* l4_per1 -> elm */
3178 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3179         .master         = &dra7xx_l4_per1_hwmod,
3180         .slave          = &dra7xx_elm_hwmod,
3181         .clk            = "l3_iclk_div",
3182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3183 };
3184
3185 /* l4_wkup -> gpio1 */
3186 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3187         .master         = &dra7xx_l4_wkup_hwmod,
3188         .slave          = &dra7xx_gpio1_hwmod,
3189         .clk            = "wkupaon_iclk_mux",
3190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3191 };
3192
3193 /* l4_per1 -> gpio2 */
3194 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3195         .master         = &dra7xx_l4_per1_hwmod,
3196         .slave          = &dra7xx_gpio2_hwmod,
3197         .clk            = "l3_iclk_div",
3198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3199 };
3200
3201 /* l4_per1 -> gpio3 */
3202 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3203         .master         = &dra7xx_l4_per1_hwmod,
3204         .slave          = &dra7xx_gpio3_hwmod,
3205         .clk            = "l3_iclk_div",
3206         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3207 };
3208
3209 /* l4_per1 -> gpio4 */
3210 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3211         .master         = &dra7xx_l4_per1_hwmod,
3212         .slave          = &dra7xx_gpio4_hwmod,
3213         .clk            = "l3_iclk_div",
3214         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3215 };
3216
3217 /* l4_per1 -> gpio5 */
3218 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3219         .master         = &dra7xx_l4_per1_hwmod,
3220         .slave          = &dra7xx_gpio5_hwmod,
3221         .clk            = "l3_iclk_div",
3222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3223 };
3224
3225 /* l4_per1 -> gpio6 */
3226 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3227         .master         = &dra7xx_l4_per1_hwmod,
3228         .slave          = &dra7xx_gpio6_hwmod,
3229         .clk            = "l3_iclk_div",
3230         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3231 };
3232
3233 /* l4_per1 -> gpio7 */
3234 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3235         .master         = &dra7xx_l4_per1_hwmod,
3236         .slave          = &dra7xx_gpio7_hwmod,
3237         .clk            = "l3_iclk_div",
3238         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3239 };
3240
3241 /* l4_per1 -> gpio8 */
3242 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3243         .master         = &dra7xx_l4_per1_hwmod,
3244         .slave          = &dra7xx_gpio8_hwmod,
3245         .clk            = "l3_iclk_div",
3246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3247 };
3248
3249 /* l3_main_1 -> gpmc */
3250 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3251         .master         = &dra7xx_l3_main_1_hwmod,
3252         .slave          = &dra7xx_gpmc_hwmod,
3253         .clk            = "l3_iclk_div",
3254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3255 };
3256
3257 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3258         {
3259                 .pa_start       = 0x480b2000,
3260                 .pa_end         = 0x480b201f,
3261                 .flags          = ADDR_TYPE_RT
3262         },
3263         { }
3264 };
3265
3266 /* l4_per1 -> hdq1w */
3267 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3268         .master         = &dra7xx_l4_per1_hwmod,
3269         .slave          = &dra7xx_hdq1w_hwmod,
3270         .clk            = "l3_iclk_div",
3271         .addr           = dra7xx_hdq1w_addrs,
3272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3273 };
3274
3275 /* l4_per1 -> i2c1 */
3276 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3277         .master         = &dra7xx_l4_per1_hwmod,
3278         .slave          = &dra7xx_i2c1_hwmod,
3279         .clk            = "l3_iclk_div",
3280         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3281 };
3282
3283 /* l4_per1 -> i2c2 */
3284 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3285         .master         = &dra7xx_l4_per1_hwmod,
3286         .slave          = &dra7xx_i2c2_hwmod,
3287         .clk            = "l3_iclk_div",
3288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3289 };
3290
3291 /* l4_per1 -> i2c3 */
3292 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3293         .master         = &dra7xx_l4_per1_hwmod,
3294         .slave          = &dra7xx_i2c3_hwmod,
3295         .clk            = "l3_iclk_div",
3296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3297 };
3298
3299 /* l4_per1 -> i2c4 */
3300 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3301         .master         = &dra7xx_l4_per1_hwmod,
3302         .slave          = &dra7xx_i2c4_hwmod,
3303         .clk            = "l3_iclk_div",
3304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3305 };
3306
3307 /* l4_per1 -> i2c5 */
3308 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3309         .master         = &dra7xx_l4_per1_hwmod,
3310         .slave          = &dra7xx_i2c5_hwmod,
3311         .clk            = "l3_iclk_div",
3312         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3313 };
3314
3315 /* l4_cfg -> mailbox1 */
3316 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3317         .master         = &dra7xx_l4_cfg_hwmod,
3318         .slave          = &dra7xx_mailbox1_hwmod,
3319         .clk            = "l3_iclk_div",
3320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3321 };
3322
3323 /* l4_per3 -> mailbox2 */
3324 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3325         .master         = &dra7xx_l4_per3_hwmod,
3326         .slave          = &dra7xx_mailbox2_hwmod,
3327         .clk            = "l3_iclk_div",
3328         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3329 };
3330
3331 /* l4_per3 -> mailbox3 */
3332 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3333         .master         = &dra7xx_l4_per3_hwmod,
3334         .slave          = &dra7xx_mailbox3_hwmod,
3335         .clk            = "l3_iclk_div",
3336         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3337 };
3338
3339 /* l4_per3 -> mailbox4 */
3340 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3341         .master         = &dra7xx_l4_per3_hwmod,
3342         .slave          = &dra7xx_mailbox4_hwmod,
3343         .clk            = "l3_iclk_div",
3344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3345 };
3346
3347 /* l4_per3 -> mailbox5 */
3348 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3349         .master         = &dra7xx_l4_per3_hwmod,
3350         .slave          = &dra7xx_mailbox5_hwmod,
3351         .clk            = "l3_iclk_div",
3352         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3353 };
3354
3355 /* l4_per3 -> mailbox6 */
3356 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3357         .master         = &dra7xx_l4_per3_hwmod,
3358         .slave          = &dra7xx_mailbox6_hwmod,
3359         .clk            = "l3_iclk_div",
3360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3361 };
3362
3363 /* l4_per3 -> mailbox7 */
3364 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3365         .master         = &dra7xx_l4_per3_hwmod,
3366         .slave          = &dra7xx_mailbox7_hwmod,
3367         .clk            = "l3_iclk_div",
3368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3369 };
3370
3371 /* l4_per3 -> mailbox8 */
3372 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3373         .master         = &dra7xx_l4_per3_hwmod,
3374         .slave          = &dra7xx_mailbox8_hwmod,
3375         .clk            = "l3_iclk_div",
3376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3377 };
3378
3379 /* l4_per3 -> mailbox9 */
3380 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3381         .master         = &dra7xx_l4_per3_hwmod,
3382         .slave          = &dra7xx_mailbox9_hwmod,
3383         .clk            = "l3_iclk_div",
3384         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3385 };
3386
3387 /* l4_per3 -> mailbox10 */
3388 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3389         .master         = &dra7xx_l4_per3_hwmod,
3390         .slave          = &dra7xx_mailbox10_hwmod,
3391         .clk            = "l3_iclk_div",
3392         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3393 };
3394
3395 /* l4_per3 -> mailbox11 */
3396 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3397         .master         = &dra7xx_l4_per3_hwmod,
3398         .slave          = &dra7xx_mailbox11_hwmod,
3399         .clk            = "l3_iclk_div",
3400         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3401 };
3402
3403 /* l4_per3 -> mailbox12 */
3404 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3405         .master         = &dra7xx_l4_per3_hwmod,
3406         .slave          = &dra7xx_mailbox12_hwmod,
3407         .clk            = "l3_iclk_div",
3408         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3409 };
3410
3411 /* l4_per3 -> mailbox13 */
3412 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3413         .master         = &dra7xx_l4_per3_hwmod,
3414         .slave          = &dra7xx_mailbox13_hwmod,
3415         .clk            = "l3_iclk_div",
3416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3417 };
3418
3419 /* l4_per1 -> mcspi1 */
3420 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3421         .master         = &dra7xx_l4_per1_hwmod,
3422         .slave          = &dra7xx_mcspi1_hwmod,
3423         .clk            = "l3_iclk_div",
3424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3425 };
3426
3427 /* l4_per1 -> mcspi2 */
3428 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3429         .master         = &dra7xx_l4_per1_hwmod,
3430         .slave          = &dra7xx_mcspi2_hwmod,
3431         .clk            = "l3_iclk_div",
3432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3433 };
3434
3435 /* l4_per1 -> mcspi3 */
3436 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3437         .master         = &dra7xx_l4_per1_hwmod,
3438         .slave          = &dra7xx_mcspi3_hwmod,
3439         .clk            = "l3_iclk_div",
3440         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3441 };
3442
3443 /* l4_per1 -> mcspi4 */
3444 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3445         .master         = &dra7xx_l4_per1_hwmod,
3446         .slave          = &dra7xx_mcspi4_hwmod,
3447         .clk            = "l3_iclk_div",
3448         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3449 };
3450
3451 /* l4_per1 -> mmc1 */
3452 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3453         .master         = &dra7xx_l4_per1_hwmod,
3454         .slave          = &dra7xx_mmc1_hwmod,
3455         .clk            = "l3_iclk_div",
3456         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3457 };
3458
3459 /* l4_per1 -> mmc2 */
3460 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3461         .master         = &dra7xx_l4_per1_hwmod,
3462         .slave          = &dra7xx_mmc2_hwmod,
3463         .clk            = "l3_iclk_div",
3464         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3465 };
3466
3467 /* l4_per1 -> mmc3 */
3468 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3469         .master         = &dra7xx_l4_per1_hwmod,
3470         .slave          = &dra7xx_mmc3_hwmod,
3471         .clk            = "l3_iclk_div",
3472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3473 };
3474
3475 /* l4_per1 -> mmc4 */
3476 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3477         .master         = &dra7xx_l4_per1_hwmod,
3478         .slave          = &dra7xx_mmc4_hwmod,
3479         .clk            = "l3_iclk_div",
3480         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3481 };
3482
3483 /* l4_cfg -> mpu */
3484 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3485         .master         = &dra7xx_l4_cfg_hwmod,
3486         .slave          = &dra7xx_mpu_hwmod,
3487         .clk            = "l3_iclk_div",
3488         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3489 };
3490
3491 /* l4_cfg -> ocp2scp1 */
3492 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3493         .master         = &dra7xx_l4_cfg_hwmod,
3494         .slave          = &dra7xx_ocp2scp1_hwmod,
3495         .clk            = "l4_root_clk_div",
3496         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3497 };
3498
3499 /* l4_cfg -> ocp2scp3 */
3500 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3501         .master         = &dra7xx_l4_cfg_hwmod,
3502         .slave          = &dra7xx_ocp2scp3_hwmod,
3503         .clk            = "l4_root_clk_div",
3504         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3505 };
3506
3507 /* l3_main_1 -> pciess1 */
3508 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3509         .master         = &dra7xx_l3_main_1_hwmod,
3510         .slave          = &dra7xx_pciess1_hwmod,
3511         .clk            = "l3_iclk_div",
3512         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3513 };
3514
3515 /* l4_cfg -> pciess1 */
3516 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3517         .master         = &dra7xx_l4_cfg_hwmod,
3518         .slave          = &dra7xx_pciess1_hwmod,
3519         .clk            = "l4_root_clk_div",
3520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3521 };
3522
3523 /* l3_main_1 -> pciess2 */
3524 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3525         .master         = &dra7xx_l3_main_1_hwmod,
3526         .slave          = &dra7xx_pciess2_hwmod,
3527         .clk            = "l3_iclk_div",
3528         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3529 };
3530
3531 /* l4_cfg -> pciess2 */
3532 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3533         .master         = &dra7xx_l4_cfg_hwmod,
3534         .slave          = &dra7xx_pciess2_hwmod,
3535         .clk            = "l4_root_clk_div",
3536         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3537 };
3538
3539 /* l3_main_1 -> qspi */
3540 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3541         .master         = &dra7xx_l3_main_1_hwmod,
3542         .slave          = &dra7xx_qspi_hwmod,
3543         .clk            = "l3_iclk_div",
3544         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3545 };
3546
3547 /* l4_per3 -> rtcss */
3548 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3549         .master         = &dra7xx_l4_per3_hwmod,
3550         .slave          = &dra7xx_rtcss_hwmod,
3551         .clk            = "l4_root_clk_div",
3552         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3553 };
3554
3555 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3556         {
3557                 .name           = "sysc",
3558                 .pa_start       = 0x4a141100,
3559                 .pa_end         = 0x4a141107,
3560                 .flags          = ADDR_TYPE_RT
3561         },
3562         { }
3563 };
3564
3565 /* l4_cfg -> sata */
3566 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3567         .master         = &dra7xx_l4_cfg_hwmod,
3568         .slave          = &dra7xx_sata_hwmod,
3569         .clk            = "l3_iclk_div",
3570         .addr           = dra7xx_sata_addrs,
3571         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3572 };
3573
3574 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3575         {
3576                 .pa_start       = 0x4a0dd000,
3577                 .pa_end         = 0x4a0dd07f,
3578                 .flags          = ADDR_TYPE_RT
3579         },
3580         { }
3581 };
3582
3583 /* l4_cfg -> smartreflex_core */
3584 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3585         .master         = &dra7xx_l4_cfg_hwmod,
3586         .slave          = &dra7xx_smartreflex_core_hwmod,
3587         .clk            = "l4_root_clk_div",
3588         .addr           = dra7xx_smartreflex_core_addrs,
3589         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3590 };
3591
3592 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3593         {
3594                 .pa_start       = 0x4a0d9000,
3595                 .pa_end         = 0x4a0d907f,
3596                 .flags          = ADDR_TYPE_RT
3597         },
3598         { }
3599 };
3600
3601 /* l4_cfg -> smartreflex_mpu */
3602 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3603         .master         = &dra7xx_l4_cfg_hwmod,
3604         .slave          = &dra7xx_smartreflex_mpu_hwmod,
3605         .clk            = "l4_root_clk_div",
3606         .addr           = dra7xx_smartreflex_mpu_addrs,
3607         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3608 };
3609
3610 /* l4_cfg -> spinlock */
3611 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3612         .master         = &dra7xx_l4_cfg_hwmod,
3613         .slave          = &dra7xx_spinlock_hwmod,
3614         .clk            = "l3_iclk_div",
3615         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3616 };
3617
3618 /* l4_wkup -> timer1 */
3619 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3620         .master         = &dra7xx_l4_wkup_hwmod,
3621         .slave          = &dra7xx_timer1_hwmod,
3622         .clk            = "wkupaon_iclk_mux",
3623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3624 };
3625
3626 /* l4_per1 -> timer2 */
3627 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3628         .master         = &dra7xx_l4_per1_hwmod,
3629         .slave          = &dra7xx_timer2_hwmod,
3630         .clk            = "l3_iclk_div",
3631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3632 };
3633
3634 /* l4_per1 -> timer3 */
3635 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3636         .master         = &dra7xx_l4_per1_hwmod,
3637         .slave          = &dra7xx_timer3_hwmod,
3638         .clk            = "l3_iclk_div",
3639         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3640 };
3641
3642 /* l4_per1 -> timer4 */
3643 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3644         .master         = &dra7xx_l4_per1_hwmod,
3645         .slave          = &dra7xx_timer4_hwmod,
3646         .clk            = "l3_iclk_div",
3647         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3648 };
3649
3650 /* l4_per3 -> timer5 */
3651 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3652         .master         = &dra7xx_l4_per3_hwmod,
3653         .slave          = &dra7xx_timer5_hwmod,
3654         .clk            = "l3_iclk_div",
3655         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3656 };
3657
3658 /* l4_per3 -> timer6 */
3659 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3660         .master         = &dra7xx_l4_per3_hwmod,
3661         .slave          = &dra7xx_timer6_hwmod,
3662         .clk            = "l3_iclk_div",
3663         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3664 };
3665
3666 /* l4_per3 -> timer7 */
3667 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3668         .master         = &dra7xx_l4_per3_hwmod,
3669         .slave          = &dra7xx_timer7_hwmod,
3670         .clk            = "l3_iclk_div",
3671         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3672 };
3673
3674 /* l4_per3 -> timer8 */
3675 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3676         .master         = &dra7xx_l4_per3_hwmod,
3677         .slave          = &dra7xx_timer8_hwmod,
3678         .clk            = "l3_iclk_div",
3679         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3680 };
3681
3682 /* l4_per1 -> timer9 */
3683 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3684         .master         = &dra7xx_l4_per1_hwmod,
3685         .slave          = &dra7xx_timer9_hwmod,
3686         .clk            = "l3_iclk_div",
3687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3688 };
3689
3690 /* l4_per1 -> timer10 */
3691 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3692         .master         = &dra7xx_l4_per1_hwmod,
3693         .slave          = &dra7xx_timer10_hwmod,
3694         .clk            = "l3_iclk_div",
3695         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3696 };
3697
3698 /* l4_per1 -> timer11 */
3699 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3700         .master         = &dra7xx_l4_per1_hwmod,
3701         .slave          = &dra7xx_timer11_hwmod,
3702         .clk            = "l3_iclk_div",
3703         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3704 };
3705
3706 /* l4_wkup -> timer12 */
3707 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3708         .master         = &dra7xx_l4_wkup_hwmod,
3709         .slave          = &dra7xx_timer12_hwmod,
3710         .clk            = "wkupaon_iclk_mux",
3711         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3712 };
3713
3714 /* l4_per3 -> timer13 */
3715 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3716         .master         = &dra7xx_l4_per3_hwmod,
3717         .slave          = &dra7xx_timer13_hwmod,
3718         .clk            = "l3_iclk_div",
3719         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3720 };
3721
3722 /* l4_per3 -> timer14 */
3723 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3724         .master         = &dra7xx_l4_per3_hwmod,
3725         .slave          = &dra7xx_timer14_hwmod,
3726         .clk            = "l3_iclk_div",
3727         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3728 };
3729
3730 /* l4_per3 -> timer15 */
3731 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3732         .master         = &dra7xx_l4_per3_hwmod,
3733         .slave          = &dra7xx_timer15_hwmod,
3734         .clk            = "l3_iclk_div",
3735         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3736 };
3737
3738 /* l4_per3 -> timer16 */
3739 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3740         .master         = &dra7xx_l4_per3_hwmod,
3741         .slave          = &dra7xx_timer16_hwmod,
3742         .clk            = "l3_iclk_div",
3743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3744 };
3745
3746 /* l4_per1 -> uart1 */
3747 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3748         .master         = &dra7xx_l4_per1_hwmod,
3749         .slave          = &dra7xx_uart1_hwmod,
3750         .clk            = "l3_iclk_div",
3751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3752 };
3753
3754 /* l4_per1 -> uart2 */
3755 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3756         .master         = &dra7xx_l4_per1_hwmod,
3757         .slave          = &dra7xx_uart2_hwmod,
3758         .clk            = "l3_iclk_div",
3759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3760 };
3761
3762 /* l4_per1 -> uart3 */
3763 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3764         .master         = &dra7xx_l4_per1_hwmod,
3765         .slave          = &dra7xx_uart3_hwmod,
3766         .clk            = "l3_iclk_div",
3767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3768 };
3769
3770 /* l4_per1 -> uart4 */
3771 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3772         .master         = &dra7xx_l4_per1_hwmod,
3773         .slave          = &dra7xx_uart4_hwmod,
3774         .clk            = "l3_iclk_div",
3775         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3776 };
3777
3778 /* l4_per1 -> uart5 */
3779 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3780         .master         = &dra7xx_l4_per1_hwmod,
3781         .slave          = &dra7xx_uart5_hwmod,
3782         .clk            = "l3_iclk_div",
3783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3784 };
3785
3786 /* l4_per1 -> uart6 */
3787 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3788         .master         = &dra7xx_l4_per1_hwmod,
3789         .slave          = &dra7xx_uart6_hwmod,
3790         .clk            = "l3_iclk_div",
3791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3792 };
3793
3794 /* l4_per2 -> uart7 */
3795 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3796         .master         = &dra7xx_l4_per2_hwmod,
3797         .slave          = &dra7xx_uart7_hwmod,
3798         .clk            = "l3_iclk_div",
3799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3800 };
3801
3802 /* l4_per1 -> des */
3803 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3804         .master         = &dra7xx_l4_per1_hwmod,
3805         .slave          = &dra7xx_des_hwmod,
3806         .clk            = "l3_iclk_div",
3807         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3808 };
3809
3810 /* l4_per2 -> uart8 */
3811 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3812         .master         = &dra7xx_l4_per2_hwmod,
3813         .slave          = &dra7xx_uart8_hwmod,
3814         .clk            = "l3_iclk_div",
3815         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3816 };
3817
3818 /* l4_per2 -> uart9 */
3819 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3820         .master         = &dra7xx_l4_per2_hwmod,
3821         .slave          = &dra7xx_uart9_hwmod,
3822         .clk            = "l3_iclk_div",
3823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3824 };
3825
3826 /* l4_wkup -> uart10 */
3827 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3828         .master         = &dra7xx_l4_wkup_hwmod,
3829         .slave          = &dra7xx_uart10_hwmod,
3830         .clk            = "wkupaon_iclk_mux",
3831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3832 };
3833
3834 /* l4_per1 -> rng */
3835 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3836         .master         = &dra7xx_l4_per1_hwmod,
3837         .slave          = &dra7xx_rng_hwmod,
3838         .user           = OCP_USER_MPU,
3839 };
3840
3841 /* l4_per3 -> usb_otg_ss1 */
3842 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3843         .master         = &dra7xx_l4_per3_hwmod,
3844         .slave          = &dra7xx_usb_otg_ss1_hwmod,
3845         .clk            = "dpll_core_h13x2_ck",
3846         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3847 };
3848
3849 /* l4_per3 -> usb_otg_ss2 */
3850 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3851         .master         = &dra7xx_l4_per3_hwmod,
3852         .slave          = &dra7xx_usb_otg_ss2_hwmod,
3853         .clk            = "dpll_core_h13x2_ck",
3854         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3855 };
3856
3857 /* l4_per3 -> usb_otg_ss3 */
3858 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3859         .master         = &dra7xx_l4_per3_hwmod,
3860         .slave          = &dra7xx_usb_otg_ss3_hwmod,
3861         .clk            = "dpll_core_h13x2_ck",
3862         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3863 };
3864
3865 /* l4_per3 -> usb_otg_ss4 */
3866 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3867         .master         = &dra7xx_l4_per3_hwmod,
3868         .slave          = &dra7xx_usb_otg_ss4_hwmod,
3869         .clk            = "dpll_core_h13x2_ck",
3870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3871 };
3872
3873 /* l3_main_1 -> vcp1 */
3874 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3875         .master         = &dra7xx_l3_main_1_hwmod,
3876         .slave          = &dra7xx_vcp1_hwmod,
3877         .clk            = "l3_iclk_div",
3878         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3879 };
3880
3881 /* l4_per2 -> vcp1 */
3882 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3883         .master         = &dra7xx_l4_per2_hwmod,
3884         .slave          = &dra7xx_vcp1_hwmod,
3885         .clk            = "l3_iclk_div",
3886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3887 };
3888
3889 /* l3_main_1 -> vcp2 */
3890 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3891         .master         = &dra7xx_l3_main_1_hwmod,
3892         .slave          = &dra7xx_vcp2_hwmod,
3893         .clk            = "l3_iclk_div",
3894         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3895 };
3896
3897 /* l4_per2 -> vcp2 */
3898 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3899         .master         = &dra7xx_l4_per2_hwmod,
3900         .slave          = &dra7xx_vcp2_hwmod,
3901         .clk            = "l3_iclk_div",
3902         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3903 };
3904
3905 /* l4_wkup -> wd_timer2 */
3906 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3907         .master         = &dra7xx_l4_wkup_hwmod,
3908         .slave          = &dra7xx_wd_timer2_hwmod,
3909         .clk            = "wkupaon_iclk_mux",
3910         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3911 };
3912
3913 /* l4_per2 -> epwmss0 */
3914 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3915         .master         = &dra7xx_l4_per2_hwmod,
3916         .slave          = &dra7xx_epwmss0_hwmod,
3917         .clk            = "l4_root_clk_div",
3918         .user           = OCP_USER_MPU,
3919 };
3920
3921 /* l4_per2 -> epwmss1 */
3922 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3923         .master         = &dra7xx_l4_per2_hwmod,
3924         .slave          = &dra7xx_epwmss1_hwmod,
3925         .clk            = "l4_root_clk_div",
3926         .user           = OCP_USER_MPU,
3927 };
3928
3929 /* l4_per2 -> epwmss2 */
3930 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3931         .master         = &dra7xx_l4_per2_hwmod,
3932         .slave          = &dra7xx_epwmss2_hwmod,
3933         .clk            = "l4_root_clk_div",
3934         .user           = OCP_USER_MPU,
3935 };
3936
3937 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3938         &dra7xx_l3_main_1__dmm,
3939         &dra7xx_l3_main_2__l3_instr,
3940         &dra7xx_l4_cfg__l3_main_1,
3941         &dra7xx_mpu__l3_main_1,
3942         &dra7xx_l3_main_1__l3_main_2,
3943         &dra7xx_l4_cfg__l3_main_2,
3944         &dra7xx_l3_main_1__l4_cfg,
3945         &dra7xx_l3_main_1__l4_per1,
3946         &dra7xx_l3_main_1__l4_per2,
3947         &dra7xx_l3_main_1__l4_per3,
3948         &dra7xx_l3_main_1__l4_wkup,
3949         &dra7xx_l4_per2__atl,
3950         &dra7xx_l3_main_1__bb2d,
3951         &dra7xx_l4_wkup__counter_32k,
3952         &dra7xx_l4_wkup__ctrl_module_wkup,
3953         &dra7xx_l4_wkup__dcan1,
3954         &dra7xx_l4_per2__dcan2,
3955         &dra7xx_l4_per2__cpgmac0,
3956         &dra7xx_l4_per2__mcasp1,
3957         &dra7xx_l3_main_1__mcasp1,
3958         &dra7xx_l4_per2__mcasp2,
3959         &dra7xx_l3_main_1__mcasp2,
3960         &dra7xx_l4_per2__mcasp3,
3961         &dra7xx_l3_main_1__mcasp3,
3962         &dra7xx_l4_per2__mcasp4,
3963         &dra7xx_l4_per2__mcasp5,
3964         &dra7xx_l4_per2__mcasp6,
3965         &dra7xx_l4_per2__mcasp7,
3966         &dra7xx_l4_per2__mcasp8,
3967         &dra7xx_gmac__mdio,
3968         &dra7xx_l4_cfg__dma_system,
3969         &dra7xx_l3_main_1__tpcc,
3970         &dra7xx_l3_main_1__tptc0,
3971         &dra7xx_l3_main_1__tptc1,
3972         &dra7xx_l3_main_1__dss,
3973         &dra7xx_l3_main_1__dispc,
3974         &dra7xx_l3_main_1__hdmi,
3975         &dra7xx_l3_main_1__aes1,
3976         &dra7xx_l3_main_1__aes2,
3977         &dra7xx_l3_main_1__sha0,
3978         &dra7xx_l4_per1__elm,
3979         &dra7xx_l4_wkup__gpio1,
3980         &dra7xx_l4_per1__gpio2,
3981         &dra7xx_l4_per1__gpio3,
3982         &dra7xx_l4_per1__gpio4,
3983         &dra7xx_l4_per1__gpio5,
3984         &dra7xx_l4_per1__gpio6,
3985         &dra7xx_l4_per1__gpio7,
3986         &dra7xx_l4_per1__gpio8,
3987         &dra7xx_l3_main_1__gpmc,
3988         &dra7xx_l4_per1__hdq1w,
3989         &dra7xx_l4_per1__i2c1,
3990         &dra7xx_l4_per1__i2c2,
3991         &dra7xx_l4_per1__i2c3,
3992         &dra7xx_l4_per1__i2c4,
3993         &dra7xx_l4_per1__i2c5,
3994         &dra7xx_l4_cfg__mailbox1,
3995         &dra7xx_l4_per3__mailbox2,
3996         &dra7xx_l4_per3__mailbox3,
3997         &dra7xx_l4_per3__mailbox4,
3998         &dra7xx_l4_per3__mailbox5,
3999         &dra7xx_l4_per3__mailbox6,
4000         &dra7xx_l4_per3__mailbox7,
4001         &dra7xx_l4_per3__mailbox8,
4002         &dra7xx_l4_per3__mailbox9,
4003         &dra7xx_l4_per3__mailbox10,
4004         &dra7xx_l4_per3__mailbox11,
4005         &dra7xx_l4_per3__mailbox12,
4006         &dra7xx_l4_per3__mailbox13,
4007         &dra7xx_l4_per1__mcspi1,
4008         &dra7xx_l4_per1__mcspi2,
4009         &dra7xx_l4_per1__mcspi3,
4010         &dra7xx_l4_per1__mcspi4,
4011         &dra7xx_l4_per1__mmc1,
4012         &dra7xx_l4_per1__mmc2,
4013         &dra7xx_l4_per1__mmc3,
4014         &dra7xx_l4_per1__mmc4,
4015         &dra7xx_l4_cfg__mpu,
4016         &dra7xx_l4_cfg__ocp2scp1,
4017         &dra7xx_l4_cfg__ocp2scp3,
4018         &dra7xx_l3_main_1__pciess1,
4019         &dra7xx_l4_cfg__pciess1,
4020         &dra7xx_l3_main_1__pciess2,
4021         &dra7xx_l4_cfg__pciess2,
4022         &dra7xx_l3_main_1__qspi,
4023         &dra7xx_l4_cfg__sata,
4024         &dra7xx_l4_cfg__smartreflex_core,
4025         &dra7xx_l4_cfg__smartreflex_mpu,
4026         &dra7xx_l4_cfg__spinlock,
4027         &dra7xx_l4_wkup__timer1,
4028         &dra7xx_l4_per1__timer2,
4029         &dra7xx_l4_per1__timer3,
4030         &dra7xx_l4_per1__timer4,
4031         &dra7xx_l4_per3__timer5,
4032         &dra7xx_l4_per3__timer6,
4033         &dra7xx_l4_per3__timer7,
4034         &dra7xx_l4_per3__timer8,
4035         &dra7xx_l4_per1__timer9,
4036         &dra7xx_l4_per1__timer10,
4037         &dra7xx_l4_per1__timer11,
4038         &dra7xx_l4_per3__timer13,
4039         &dra7xx_l4_per3__timer14,
4040         &dra7xx_l4_per3__timer15,
4041         &dra7xx_l4_per3__timer16,
4042         &dra7xx_l4_per1__uart1,
4043         &dra7xx_l4_per1__uart2,
4044         &dra7xx_l4_per1__uart3,
4045         &dra7xx_l4_per1__uart4,
4046         &dra7xx_l4_per1__uart5,
4047         &dra7xx_l4_per1__uart6,
4048         &dra7xx_l4_per2__uart7,
4049         &dra7xx_l4_per2__uart8,
4050         &dra7xx_l4_per2__uart9,
4051         &dra7xx_l4_wkup__uart10,
4052         &dra7xx_l4_per1__des,
4053         &dra7xx_l4_per3__usb_otg_ss1,
4054         &dra7xx_l4_per3__usb_otg_ss2,
4055         &dra7xx_l4_per3__usb_otg_ss3,
4056         &dra7xx_l3_main_1__vcp1,
4057         &dra7xx_l4_per2__vcp1,
4058         &dra7xx_l3_main_1__vcp2,
4059         &dra7xx_l4_per2__vcp2,
4060         &dra7xx_l4_wkup__wd_timer2,
4061         &dra7xx_l4_per2__epwmss0,
4062         &dra7xx_l4_per2__epwmss1,
4063         &dra7xx_l4_per2__epwmss2,
4064         NULL,
4065 };
4066
4067 /* GP-only hwmod links */
4068 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
4069         &dra7xx_l4_wkup__timer12,
4070         &dra7xx_l4_per1__rng,
4071         NULL,
4072 };
4073
4074 /* SoC variant specific hwmod links */
4075 static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
4076         &dra7xx_l4_per3__usb_otg_ss4,
4077         NULL,
4078 };
4079
4080 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
4081         &dra7xx_l4_per3__usb_otg_ss4,
4082         NULL,
4083 };
4084
4085 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
4086         NULL,
4087 };
4088
4089 static struct omap_hwmod_ocp_if *dra74x_dra72x_hwmod_ocp_ifs[] __initdata = {
4090         &dra7xx_l4_per3__rtcss,
4091         NULL,
4092 };
4093
4094 int __init dra7xx_hwmod_init(void)
4095 {
4096         int ret;
4097
4098         omap_hwmod_init();
4099         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
4100
4101         if (!ret && soc_is_dra74x())
4102                 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
4103         else if (!ret && soc_is_dra72x())
4104                 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4105         else if (!ret && soc_is_dra76x())
4106                 ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
4107
4108         if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
4109                 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
4110
4111         /* now for the IPs available only in dra74 and dra72 */
4112         if (!ret && !of_machine_is_compatible("ti,dra718") && !soc_is_dra76x())
4113                 ret = omap_hwmod_register_links(dra74x_dra72x_hwmod_ocp_ifs);
4114
4115         return ret;
4116 }