arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 /*
   2  * Hardware modules present on the DRA7xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/platform_data/hsmmc-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_7xx.h"
  34 #include "cm2_7xx.h"
  35 #include "prm7xx.h"
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "soc.h"
  39
  40 /* Base offset for all DRA7XX interrupts external to MPUSS */
  41 #define DRA7XX_IRQ_GIC_START    32
  42
  43 /* Base offset for all DRA7XX dma requests */
  44 #define DRA7XX_DMA_REQ_START    1
  45
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'dmm' class
  53  * instance(s): dmm
  54  */
  55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
  56         .name   = "dmm",
  57 };
  58
  59 /* dmm */
  60 static struct omap_hwmod dra7xx_dmm_hwmod = {
  61         .name           = "dmm",
  62         .class          = &dra7xx_dmm_hwmod_class,
  63         .clkdm_name     = "emif_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  67                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'l3' class
  74  * instance(s): l3_instr, l3_main_1, l3_main_2
  75  */
  76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  77         .name   = "l3",
  78 };
  79
  80 /* l3_instr */
  81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  82         .name           = "l3_instr",
  83         .class          = &dra7xx_l3_hwmod_class,
  84         .clkdm_name     = "l3instr_clkdm",
  85         .prcm = {
  86                 .omap4 = {
  87                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  88                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  89                         .modulemode   = MODULEMODE_HWCTRL,
  90                 },
  91         },
  92 };
  93
  94 /* l3_main_1 */
  95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  96         .name           = "l3_main_1",
  97         .class          = &dra7xx_l3_hwmod_class,
  98         .clkdm_name     = "l3main1_clkdm",
  99         .prcm = {
 100                 .omap4 = {
 101                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 102                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 103                 },
 104         },
 105 };
 106
 107 /* l3_main_2 */
 108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
 109         .name           = "l3_main_2",
 110         .class          = &dra7xx_l3_hwmod_class,
 111         .clkdm_name     = "l3instr_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
 115                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
 116                         .modulemode   = MODULEMODE_HWCTRL,
 117                 },
 118         },
 119 };
 120
 121 /*
 122  * 'l4' class
 123  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 124  */
 125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 126         .name   = "l4",
 127 };
 128
 129 /* l4_cfg */
 130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 131         .name           = "l4_cfg",
 132         .class          = &dra7xx_l4_hwmod_class,
 133         .clkdm_name     = "l4cfg_clkdm",
 134         .prcm = {
 135                 .omap4 = {
 136                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 137                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 138                 },
 139         },
 140 };
 141
 142 /* l4_per1 */
 143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 144         .name           = "l4_per1",
 145         .class          = &dra7xx_l4_hwmod_class,
 146         .clkdm_name     = "l4per_clkdm",
 147         .prcm = {
 148                 .omap4 = {
 149                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 150                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 151                 },
 152         },
 153 };
 154
 155 /* l4_per2 */
 156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 157         .name           = "l4_per2",
 158         .class          = &dra7xx_l4_hwmod_class,
 159         .clkdm_name     = "l4per2_clkdm",
 160         .prcm = {
 161                 .omap4 = {
 162                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 163                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 164                 },
 165         },
 166 };
 167
 168 /* l4_per3 */
 169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 170         .name           = "l4_per3",
 171         .class          = &dra7xx_l4_hwmod_class,
 172         .clkdm_name     = "l4per3_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 176                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 177                 },
 178         },
 179 };
 180
 181 /* l4_wkup */
 182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 183         .name           = "l4_wkup",
 184         .class          = &dra7xx_l4_hwmod_class,
 185         .clkdm_name     = "wkupaon_clkdm",
 186         .prcm = {
 187                 .omap4 = {
 188                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 189                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 190                 },
 191         },
 192 };
 193
 194 /*
 195  * 'atl' class
 196  *
 197  */
 198
 199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 200         .name   = "atl",
 201 };
 202
 203 /* atl */
 204 static struct omap_hwmod dra7xx_atl_hwmod = {
 205         .name           = "atl",
 206         .class          = &dra7xx_atl_hwmod_class,
 207         .clkdm_name     = "atl_clkdm",
 208         .main_clk       = "atl_gfclk_mux",
 209         .prcm = {
 210                 .omap4 = {
 211                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 212                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 213                         .modulemode   = MODULEMODE_SWCTRL,
 214                 },
 215         },
 216 };
 217
 218 /*
 219  * 'bb2d' class
 220  *
 221  */
 222
 223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 224         .name   = "bb2d",
 225 };
 226
 227 /* bb2d */
 228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 229         .name           = "bb2d",
 230         .class          = &dra7xx_bb2d_hwmod_class,
 231         .clkdm_name     = "dss_clkdm",
 232         .main_clk       = "dpll_core_h24x2_ck",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 236                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 237                         .modulemode   = MODULEMODE_SWCTRL,
 238                 },
 239         },
 240 };
 241
 242 /*
 243  * 'counter' class
 244  *
 245  */
 246
 247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 248         .rev_offs       = 0x0000,
 249         .sysc_offs      = 0x0010,
 250         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 251         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 252                            SIDLE_SMART_WKUP),
 253         .sysc_fields    = &omap_hwmod_sysc_type1,
 254 };
 255
 256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 257         .name   = "counter",
 258         .sysc   = &dra7xx_counter_sysc,
 259 };
 260
 261 /* counter_32k */
 262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 263         .name           = "counter_32k",
 264         .class          = &dra7xx_counter_hwmod_class,
 265         .clkdm_name     = "wkupaon_clkdm",
 266         .flags          = HWMOD_SWSUP_SIDLE,
 267         .main_clk       = "wkupaon_iclk_mux",
 268         .prcm = {
 269                 .omap4 = {
 270                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 271                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 272                 },
 273         },
 274 };
 275
 276 /*
 277  * 'ctrl_module' class
 278  *
 279  */
 280
 281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 282         .name   = "ctrl_module",
 283 };
 284
 285 /* ctrl_module_wkup */
 286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 287         .name           = "ctrl_module_wkup",
 288         .class          = &dra7xx_ctrl_module_hwmod_class,
 289         .clkdm_name     = "wkupaon_clkdm",
 290         .prcm = {
 291                 .omap4 = {
 292                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 293                 },
 294         },
 295 };
 296
 297 /*
 298  * 'gmac' class
 299  * cpsw/gmac sub system
 300  */
 301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
 302         .rev_offs       = 0x0,
 303         .sysc_offs      = 0x8,
 304         .syss_offs      = 0x4,
 305         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 306                            SYSS_HAS_RESET_STATUS),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 308                            MSTANDBY_NO),
 309         .sysc_fields    = &omap_hwmod_sysc_type3,
 310 };
 311
 312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
 313         .name           = "gmac",
 314         .sysc           = &dra7xx_gmac_sysc,
 315 };
 316
 317 static struct omap_hwmod dra7xx_gmac_hwmod = {
 318         .name           = "gmac",
 319         .class          = &dra7xx_gmac_hwmod_class,
 320         .clkdm_name     = "gmac_clkdm",
 321         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 322         .main_clk       = "dpll_gmac_ck",
 323         .mpu_rt_idx     = 1,
 324         .prcm           = {
 325                 .omap4  = {
 326                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
 327                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
 328                         .modulemode     = MODULEMODE_SWCTRL,
 329                 },
 330         },
 331 };
 332
 333 /*
 334  * 'mdio' class
 335  */
 336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
 337         .name           = "davinci_mdio",
 338 };
 339
 340 static struct omap_hwmod dra7xx_mdio_hwmod = {
 341         .name           = "davinci_mdio",
 342         .class          = &dra7xx_mdio_hwmod_class,
 343         .clkdm_name     = "gmac_clkdm",
 344         .main_clk       = "dpll_gmac_ck",
 345 };
 346
 347 /*
 348  * 'dcan' class
 349  *
 350  */
 351
 352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 353         .name   = "dcan",
 354 };
 355
 356 /* dcan1 */
 357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 358         .name           = "dcan1",
 359         .class          = &dra7xx_dcan_hwmod_class,
 360         .clkdm_name     = "wkupaon_clkdm",
 361         .main_clk       = "dcan1_sys_clk_mux",
 362         .prcm = {
 363                 .omap4 = {
 364                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 365                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 366                         .modulemode   = MODULEMODE_SWCTRL,
 367                 },
 368         },
 369 };
 370
 371 /* dcan2 */
 372 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 373         .name           = "dcan2",
 374         .class          = &dra7xx_dcan_hwmod_class,
 375         .clkdm_name     = "l4per2_clkdm",
 376         .main_clk       = "sys_clkin1",
 377         .prcm = {
 378                 .omap4 = {
 379                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 380                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 381                         .modulemode   = MODULEMODE_SWCTRL,
 382                 },
 383         },
 384 };
 385
 386 /* pwmss  */
 387 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
 388         .rev_offs       = 0x0,
 389         .sysc_offs      = 0x4,
 390         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 391                           SYSC_HAS_RESET_STATUS,
 392         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 393         .sysc_fields    = &omap_hwmod_sysc_type2,
 394 };
 395
 396 /*
 397  * epwmss class
 398  */
 399 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
 400         .name           = "epwmss",
 401         .sysc           = &dra7xx_epwmss_sysc,
 402 };
 403
 404 /* epwmss0 */
 405 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
 406         .name           = "epwmss0",
 407         .class          = &dra7xx_epwmss_hwmod_class,
 408         .clkdm_name     = "l4per2_clkdm",
 409         .main_clk       = "l4_root_clk_div",
 410         .prcm           = {
 411                 .omap4  = {
 412                         .modulemode     = MODULEMODE_SWCTRL,
 413                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
 414                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
 415                 },
 416         },
 417 };
 418
 419 /* epwmss1 */
 420 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
 421         .name           = "epwmss1",
 422         .class          = &dra7xx_epwmss_hwmod_class,
 423         .clkdm_name     = "l4per2_clkdm",
 424         .main_clk       = "l4_root_clk_div",
 425         .prcm           = {
 426                 .omap4  = {
 427                         .modulemode     = MODULEMODE_SWCTRL,
 428                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
 429                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
 430                 },
 431         },
 432 };
 433
 434 /* epwmss2 */
 435 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
 436         .name           = "epwmss2",
 437         .class          = &dra7xx_epwmss_hwmod_class,
 438         .clkdm_name     = "l4per2_clkdm",
 439         .main_clk       = "l4_root_clk_div",
 440         .prcm           = {
 441                 .omap4  = {
 442                         .modulemode     = MODULEMODE_SWCTRL,
 443                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
 444                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
 445                 },
 446         },
 447 };
 448
 449 /*
 450  * 'dma' class
 451  *
 452  */
 453
 454 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 455         .rev_offs       = 0x0000,
 456         .sysc_offs      = 0x002c,
 457         .syss_offs      = 0x0028,
 458         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 459                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 460                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 461                            SYSS_HAS_RESET_STATUS),
 462         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 463                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 464                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 465         .sysc_fields    = &omap_hwmod_sysc_type1,
 466 };
 467
 468 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 469         .name   = "dma",
 470         .sysc   = &dra7xx_dma_sysc,
 471 };
 472
 473 /* dma dev_attr */
 474 static struct omap_dma_dev_attr dma_dev_attr = {
 475         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 476                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 477         .lch_count      = 32,
 478 };
 479
 480 /* dma_system */
 481 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 482         .name           = "dma_system",
 483         .class          = &dra7xx_dma_hwmod_class,
 484         .clkdm_name     = "dma_clkdm",
 485         .main_clk       = "l3_iclk_div",
 486         .prcm = {
 487                 .omap4 = {
 488                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 489                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 490                 },
 491         },
 492         .dev_attr       = &dma_dev_attr,
 493 };
 494
 495 /*
 496  * 'tpcc' class
 497  *
 498  */
 499 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
 500         .name           = "tpcc",
 501 };
 502
 503 static struct omap_hwmod dra7xx_tpcc_hwmod = {
 504         .name           = "tpcc",
 505         .class          = &dra7xx_tpcc_hwmod_class,
 506         .clkdm_name     = "l3main1_clkdm",
 507         .main_clk       = "l3_iclk_div",
 508         .prcm           = {
 509                 .omap4  = {
 510                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
 511                         .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
 512                 },
 513         },
 514 };
 515
 516 /*
 517  * 'tptc' class
 518  *
 519  */
 520 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
 521         .name           = "tptc",
 522 };
 523
 524 /* tptc0 */
 525 static struct omap_hwmod dra7xx_tptc0_hwmod = {
 526         .name           = "tptc0",
 527         .class          = &dra7xx_tptc_hwmod_class,
 528         .clkdm_name     = "l3main1_clkdm",
 529         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 530         .main_clk       = "l3_iclk_div",
 531         .prcm           = {
 532                 .omap4  = {
 533                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
 534                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
 535                         .modulemode   = MODULEMODE_HWCTRL,
 536                 },
 537         },
 538 };
 539
 540 /* tptc1 */
 541 static struct omap_hwmod dra7xx_tptc1_hwmod = {
 542         .name           = "tptc1",
 543         .class          = &dra7xx_tptc_hwmod_class,
 544         .clkdm_name     = "l3main1_clkdm",
 545         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 546         .main_clk       = "l3_iclk_div",
 547         .prcm           = {
 548                 .omap4  = {
 549                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
 550                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
 551                         .modulemode   = MODULEMODE_HWCTRL,
 552                 },
 553         },
 554 };
 555
 556 /*
 557  * 'dss' class
 558  *
 559  */
 560
 561 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 562         .rev_offs       = 0x0000,
 563         .syss_offs      = 0x0014,
 564         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 565 };
 566
 567 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 568         .name   = "dss",
 569         .sysc   = &dra7xx_dss_sysc,
 570         .reset  = omap_dss_reset,
 571 };
 572
 573 /* dss */
 574 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
 575         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
 576         { .dma_req = -1 }
 577 };
 578
 579 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 580         { .role = "dss_clk", .clk = "dss_dss_clk" },
 581         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 582         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 583         { .role = "video2_clk", .clk = "dss_video2_clk" },
 584         { .role = "video1_clk", .clk = "dss_video1_clk" },
 585         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 586         { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
 587 };
 588
 589 static struct omap_hwmod dra7xx_dss_hwmod = {
 590         .name           = "dss_core",
 591         .class          = &dra7xx_dss_hwmod_class,
 592         .clkdm_name     = "dss_clkdm",
 593         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 594         .sdma_reqs      = dra7xx_dss_sdma_reqs,
 595         .main_clk       = "dss_dss_clk",
 596         .prcm = {
 597                 .omap4 = {
 598                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 599                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 600                         .modulemode   = MODULEMODE_SWCTRL,
 601                 },
 602         },
 603         .opt_clks       = dss_opt_clks,
 604         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 605 };
 606
 607 /*
 608  * 'dispc' class
 609  * display controller
 610  */
 611
 612 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 613         .rev_offs       = 0x0000,
 614         .sysc_offs      = 0x0010,
 615         .syss_offs      = 0x0014,
 616         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 617                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 618                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 619                            SYSS_HAS_RESET_STATUS),
 620         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 621                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 622         .sysc_fields    = &omap_hwmod_sysc_type1,
 623 };
 624
 625 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 626         .name   = "dispc",
 627         .sysc   = &dra7xx_dispc_sysc,
 628 };
 629
 630 /* dss_dispc */
 631 /* dss_dispc dev_attr */
 632 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 633         .has_framedonetv_irq    = 1,
 634         .manager_count          = 4,
 635 };
 636
 637 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 638         .name           = "dss_dispc",
 639         .class          = &dra7xx_dispc_hwmod_class,
 640         .clkdm_name     = "dss_clkdm",
 641         .main_clk       = "dss_dss_clk",
 642         .prcm = {
 643                 .omap4 = {
 644                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 645                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 646                 },
 647         },
 648         .dev_attr       = &dss_dispc_dev_attr,
 649         .parent_hwmod   = &dra7xx_dss_hwmod,
 650 };
 651
 652 /*
 653  * 'hdmi' class
 654  * hdmi controller
 655  */
 656
 657 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 658         .rev_offs       = 0x0000,
 659         .sysc_offs      = 0x0010,
 660         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 661                            SYSC_HAS_SOFTRESET),
 662         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 663                            SIDLE_SMART_WKUP),
 664         .sysc_fields    = &omap_hwmod_sysc_type2,
 665 };
 666
 667 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 668         .name   = "hdmi",
 669         .sysc   = &dra7xx_hdmi_sysc,
 670 };
 671
 672 /* dss_hdmi */
 673
 674 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 675         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 676 };
 677
 678 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 679         .name           = "dss_hdmi",
 680         .class          = &dra7xx_hdmi_hwmod_class,
 681         .clkdm_name     = "dss_clkdm",
 682         .main_clk       = "dss_48mhz_clk",
 683         .prcm = {
 684                 .omap4 = {
 685                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 686                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 687                 },
 688         },
 689         .opt_clks       = dss_hdmi_opt_clks,
 690         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 691         .parent_hwmod   = &dra7xx_dss_hwmod,
 692 };
 693
 694 /*
 695  * 'elm' class
 696  *
 697  */
 698
 699 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 700         .rev_offs       = 0x0000,
 701         .sysc_offs      = 0x0010,
 702         .syss_offs      = 0x0014,
 703         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 704                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 705                            SYSS_HAS_RESET_STATUS),
 706         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 707                            SIDLE_SMART_WKUP),
 708         .sysc_fields    = &omap_hwmod_sysc_type1,
 709 };
 710
 711 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 712         .name   = "elm",
 713         .sysc   = &dra7xx_elm_sysc,
 714 };
 715
 716 /* elm */
 717
 718 static struct omap_hwmod dra7xx_elm_hwmod = {
 719         .name           = "elm",
 720         .class          = &dra7xx_elm_hwmod_class,
 721         .clkdm_name     = "l4per_clkdm",
 722         .main_clk       = "l3_iclk_div",
 723         .prcm = {
 724                 .omap4 = {
 725                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 726                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 727                 },
 728         },
 729 };
 730
 731 /*
 732  * 'gpio' class
 733  *
 734  */
 735
 736 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
 737         .rev_offs       = 0x0000,
 738         .sysc_offs      = 0x0010,
 739         .syss_offs      = 0x0114,
 740         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 741                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 742                            SYSS_HAS_RESET_STATUS),
 743         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 744                            SIDLE_SMART_WKUP),
 745         .sysc_fields    = &omap_hwmod_sysc_type1,
 746 };
 747
 748 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 749         .name   = "gpio",
 750         .sysc   = &dra7xx_gpio_sysc,
 751         .rev    = 2,
 752 };
 753
 754 /* gpio dev_attr */
 755 static struct omap_gpio_dev_attr gpio_dev_attr = {
 756         .bank_width     = 32,
 757         .dbck_flag      = true,
 758 };
 759
 760 /* gpio1 */
 761 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 762         { .role = "dbclk", .clk = "gpio1_dbclk" },
 763 };
 764
 765 static struct omap_hwmod dra7xx_gpio1_hwmod = {
 766         .name           = "gpio1",
 767         .class          = &dra7xx_gpio_hwmod_class,
 768         .clkdm_name     = "wkupaon_clkdm",
 769         .main_clk       = "wkupaon_iclk_mux",
 770         .prcm = {
 771                 .omap4 = {
 772                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 773                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 774                         .modulemode   = MODULEMODE_HWCTRL,
 775                 },
 776         },
 777         .opt_clks       = gpio1_opt_clks,
 778         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 779         .dev_attr       = &gpio_dev_attr,
 780 };
 781
 782 /* gpio2 */
 783 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 784         { .role = "dbclk", .clk = "gpio2_dbclk" },
 785 };
 786
 787 static struct omap_hwmod dra7xx_gpio2_hwmod = {
 788         .name           = "gpio2",
 789         .class          = &dra7xx_gpio_hwmod_class,
 790         .clkdm_name     = "l4per_clkdm",
 791         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 792         .main_clk       = "l3_iclk_div",
 793         .prcm = {
 794                 .omap4 = {
 795                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 796                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 797                         .modulemode   = MODULEMODE_HWCTRL,
 798                 },
 799         },
 800         .opt_clks       = gpio2_opt_clks,
 801         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 802         .dev_attr       = &gpio_dev_attr,
 803 };
 804
 805 /* gpio3 */
 806 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 807         { .role = "dbclk", .clk = "gpio3_dbclk" },
 808 };
 809
 810 static struct omap_hwmod dra7xx_gpio3_hwmod = {
 811         .name           = "gpio3",
 812         .class          = &dra7xx_gpio_hwmod_class,
 813         .clkdm_name     = "l4per_clkdm",
 814         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 815         .main_clk       = "l3_iclk_div",
 816         .prcm = {
 817                 .omap4 = {
 818                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 819                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 820                         .modulemode   = MODULEMODE_HWCTRL,
 821                 },
 822         },
 823         .opt_clks       = gpio3_opt_clks,
 824         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 825         .dev_attr       = &gpio_dev_attr,
 826 };
 827
 828 /* gpio4 */
 829 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 830         { .role = "dbclk", .clk = "gpio4_dbclk" },
 831 };
 832
 833 static struct omap_hwmod dra7xx_gpio4_hwmod = {
 834         .name           = "gpio4",
 835         .class          = &dra7xx_gpio_hwmod_class,
 836         .clkdm_name     = "l4per_clkdm",
 837         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 838         .main_clk       = "l3_iclk_div",
 839         .prcm = {
 840                 .omap4 = {
 841                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 842                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 843                         .modulemode   = MODULEMODE_HWCTRL,
 844                 },
 845         },
 846         .opt_clks       = gpio4_opt_clks,
 847         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 848         .dev_attr       = &gpio_dev_attr,
 849 };
 850
 851 /* gpio5 */
 852 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 853         { .role = "dbclk", .clk = "gpio5_dbclk" },
 854 };
 855
 856 static struct omap_hwmod dra7xx_gpio5_hwmod = {
 857         .name           = "gpio5",
 858         .class          = &dra7xx_gpio_hwmod_class,
 859         .clkdm_name     = "l4per_clkdm",
 860         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 861         .main_clk       = "l3_iclk_div",
 862         .prcm = {
 863                 .omap4 = {
 864                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 865                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 866                         .modulemode   = MODULEMODE_HWCTRL,
 867                 },
 868         },
 869         .opt_clks       = gpio5_opt_clks,
 870         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 871         .dev_attr       = &gpio_dev_attr,
 872 };
 873
 874 /* gpio6 */
 875 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 876         { .role = "dbclk", .clk = "gpio6_dbclk" },
 877 };
 878
 879 static struct omap_hwmod dra7xx_gpio6_hwmod = {
 880         .name           = "gpio6",
 881         .class          = &dra7xx_gpio_hwmod_class,
 882         .clkdm_name     = "l4per_clkdm",
 883         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 884         .main_clk       = "l3_iclk_div",
 885         .prcm = {
 886                 .omap4 = {
 887                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 888                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 889                         .modulemode   = MODULEMODE_HWCTRL,
 890                 },
 891         },
 892         .opt_clks       = gpio6_opt_clks,
 893         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 894         .dev_attr       = &gpio_dev_attr,
 895 };
 896
 897 /* gpio7 */
 898 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 899         { .role = "dbclk", .clk = "gpio7_dbclk" },
 900 };
 901
 902 static struct omap_hwmod dra7xx_gpio7_hwmod = {
 903         .name           = "gpio7",
 904         .class          = &dra7xx_gpio_hwmod_class,
 905         .clkdm_name     = "l4per_clkdm",
 906         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 907         .main_clk       = "l3_iclk_div",
 908         .prcm = {
 909                 .omap4 = {
 910                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 911                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 912                         .modulemode   = MODULEMODE_HWCTRL,
 913                 },
 914         },
 915         .opt_clks       = gpio7_opt_clks,
 916         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 917         .dev_attr       = &gpio_dev_attr,
 918 };
 919
 920 /* gpio8 */
 921 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 922         { .role = "dbclk", .clk = "gpio8_dbclk" },
 923 };
 924
 925 static struct omap_hwmod dra7xx_gpio8_hwmod = {
 926         .name           = "gpio8",
 927         .class          = &dra7xx_gpio_hwmod_class,
 928         .clkdm_name     = "l4per_clkdm",
 929         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 930         .main_clk       = "l3_iclk_div",
 931         .prcm = {
 932                 .omap4 = {
 933                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 934                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 935                         .modulemode   = MODULEMODE_HWCTRL,
 936                 },
 937         },
 938         .opt_clks       = gpio8_opt_clks,
 939         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 940         .dev_attr       = &gpio_dev_attr,
 941 };
 942
 943 /*
 944  * 'gpmc' class
 945  *
 946  */
 947
 948 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
 949         .rev_offs       = 0x0000,
 950         .sysc_offs      = 0x0010,
 951         .syss_offs      = 0x0014,
 952         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 953                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 954         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 955         .sysc_fields    = &omap_hwmod_sysc_type1,
 956 };
 957
 958 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
 959         .name   = "gpmc",
 960         .sysc   = &dra7xx_gpmc_sysc,
 961 };
 962
 963 /* gpmc */
 964
 965 static struct omap_hwmod dra7xx_gpmc_hwmod = {
 966         .name           = "gpmc",
 967         .class          = &dra7xx_gpmc_hwmod_class,
 968         .clkdm_name     = "l3main1_clkdm",
 969         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 970         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 971         .main_clk       = "l3_iclk_div",
 972         .prcm = {
 973                 .omap4 = {
 974                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
 975                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
 976                         .modulemode   = MODULEMODE_HWCTRL,
 977                 },
 978         },
 979 };
 980
 981 /*
 982  * 'hdq1w' class
 983  *
 984  */
 985
 986 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
 987         .rev_offs       = 0x0000,
 988         .sysc_offs      = 0x0014,
 989         .syss_offs      = 0x0018,
 990         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
 991                            SYSS_HAS_RESET_STATUS),
 992         .sysc_fields    = &omap_hwmod_sysc_type1,
 993 };
 994
 995 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
 996         .name   = "hdq1w",
 997         .sysc   = &dra7xx_hdq1w_sysc,
 998 };
 999
1000 /* hdq1w */
1001
1002 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1003         .name           = "hdq1w",
1004         .class          = &dra7xx_hdq1w_hwmod_class,
1005         .clkdm_name     = "l4per_clkdm",
1006         .flags          = HWMOD_INIT_NO_RESET,
1007         .main_clk       = "func_12m_fclk",
1008         .prcm = {
1009                 .omap4 = {
1010                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1011                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1012                         .modulemode   = MODULEMODE_SWCTRL,
1013                 },
1014         },
1015 };
1016
1017 /*
1018  * 'i2c' class
1019  *
1020  */
1021
1022 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1023         .sysc_offs      = 0x0010,
1024         .syss_offs      = 0x0090,
1025         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1026                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1027                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1028         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1029                            SIDLE_SMART_WKUP),
1030         .clockact       = CLOCKACT_TEST_ICLK,
1031         .sysc_fields    = &omap_hwmod_sysc_type1,
1032 };
1033
1034 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1035         .name   = "i2c",
1036         .sysc   = &dra7xx_i2c_sysc,
1037         .reset  = &omap_i2c_reset,
1038         .rev    = OMAP_I2C_IP_VERSION_2,
1039 };
1040
1041 /* i2c dev_attr */
1042 static struct omap_i2c_dev_attr i2c_dev_attr = {
1043         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1044 };
1045
1046 /* i2c1 */
1047 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1048         .name           = "i2c1",
1049         .class          = &dra7xx_i2c_hwmod_class,
1050         .clkdm_name     = "l4per_clkdm",
1051         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1052         .main_clk       = "func_96m_fclk",
1053         .prcm = {
1054                 .omap4 = {
1055                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1056                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1057                         .modulemode   = MODULEMODE_SWCTRL,
1058                 },
1059         },
1060         .dev_attr       = &i2c_dev_attr,
1061 };
1062
1063 /* i2c2 */
1064 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1065         .name           = "i2c2",
1066         .class          = &dra7xx_i2c_hwmod_class,
1067         .clkdm_name     = "l4per_clkdm",
1068         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1069         .main_clk       = "func_96m_fclk",
1070         .prcm = {
1071                 .omap4 = {
1072                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1073                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1074                         .modulemode   = MODULEMODE_SWCTRL,
1075                 },
1076         },
1077         .dev_attr       = &i2c_dev_attr,
1078 };
1079
1080 /* i2c3 */
1081 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1082         .name           = "i2c3",
1083         .class          = &dra7xx_i2c_hwmod_class,
1084         .clkdm_name     = "l4per_clkdm",
1085         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1086         .main_clk       = "func_96m_fclk",
1087         .prcm = {
1088                 .omap4 = {
1089                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1090                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1091                         .modulemode   = MODULEMODE_SWCTRL,
1092                 },
1093         },
1094         .dev_attr       = &i2c_dev_attr,
1095 };
1096
1097 /* i2c4 */
1098 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1099         .name           = "i2c4",
1100         .class          = &dra7xx_i2c_hwmod_class,
1101         .clkdm_name     = "l4per_clkdm",
1102         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1103         .main_clk       = "func_96m_fclk",
1104         .prcm = {
1105                 .omap4 = {
1106                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1107                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1108                         .modulemode   = MODULEMODE_SWCTRL,
1109                 },
1110         },
1111         .dev_attr       = &i2c_dev_attr,
1112 };
1113
1114 /* i2c5 */
1115 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1116         .name           = "i2c5",
1117         .class          = &dra7xx_i2c_hwmod_class,
1118         .clkdm_name     = "ipu_clkdm",
1119         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1120         .main_clk       = "func_96m_fclk",
1121         .prcm = {
1122                 .omap4 = {
1123                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1124                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1125                         .modulemode   = MODULEMODE_SWCTRL,
1126                 },
1127         },
1128         .dev_attr       = &i2c_dev_attr,
1129 };
1130
1131 /*
1132  * 'mailbox' class
1133  *
1134  */
1135
1136 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1137         .rev_offs       = 0x0000,
1138         .sysc_offs      = 0x0010,
1139         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1140                            SYSC_HAS_SOFTRESET),
1141         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1142         .sysc_fields    = &omap_hwmod_sysc_type2,
1143 };
1144
1145 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1146         .name   = "mailbox",
1147         .sysc   = &dra7xx_mailbox_sysc,
1148 };
1149
1150 /* mailbox1 */
1151 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1152         .name           = "mailbox1",
1153         .class          = &dra7xx_mailbox_hwmod_class,
1154         .clkdm_name     = "l4cfg_clkdm",
1155         .prcm = {
1156                 .omap4 = {
1157                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1158                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1159                 },
1160         },
1161 };
1162
1163 /* mailbox2 */
1164 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1165         .name           = "mailbox2",
1166         .class          = &dra7xx_mailbox_hwmod_class,
1167         .clkdm_name     = "l4cfg_clkdm",
1168         .prcm = {
1169                 .omap4 = {
1170                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1171                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1172                 },
1173         },
1174 };
1175
1176 /* mailbox3 */
1177 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1178         .name           = "mailbox3",
1179         .class          = &dra7xx_mailbox_hwmod_class,
1180         .clkdm_name     = "l4cfg_clkdm",
1181         .prcm = {
1182                 .omap4 = {
1183                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1184                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1185                 },
1186         },
1187 };
1188
1189 /* mailbox4 */
1190 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1191         .name           = "mailbox4",
1192         .class          = &dra7xx_mailbox_hwmod_class,
1193         .clkdm_name     = "l4cfg_clkdm",
1194         .prcm = {
1195                 .omap4 = {
1196                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1197                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1198                 },
1199         },
1200 };
1201
1202 /* mailbox5 */
1203 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1204         .name           = "mailbox5",
1205         .class          = &dra7xx_mailbox_hwmod_class,
1206         .clkdm_name     = "l4cfg_clkdm",
1207         .prcm = {
1208                 .omap4 = {
1209                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1210                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1211                 },
1212         },
1213 };
1214
1215 /* mailbox6 */
1216 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1217         .name           = "mailbox6",
1218         .class          = &dra7xx_mailbox_hwmod_class,
1219         .clkdm_name     = "l4cfg_clkdm",
1220         .prcm = {
1221                 .omap4 = {
1222                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1223                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1224                 },
1225         },
1226 };
1227
1228 /* mailbox7 */
1229 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1230         .name           = "mailbox7",
1231         .class          = &dra7xx_mailbox_hwmod_class,
1232         .clkdm_name     = "l4cfg_clkdm",
1233         .prcm = {
1234                 .omap4 = {
1235                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1236                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1237                 },
1238         },
1239 };
1240
1241 /* mailbox8 */
1242 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1243         .name           = "mailbox8",
1244         .class          = &dra7xx_mailbox_hwmod_class,
1245         .clkdm_name     = "l4cfg_clkdm",
1246         .prcm = {
1247                 .omap4 = {
1248                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1249                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1250                 },
1251         },
1252 };
1253
1254 /* mailbox9 */
1255 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1256         .name           = "mailbox9",
1257         .class          = &dra7xx_mailbox_hwmod_class,
1258         .clkdm_name     = "l4cfg_clkdm",
1259         .prcm = {
1260                 .omap4 = {
1261                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1262                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1263                 },
1264         },
1265 };
1266
1267 /* mailbox10 */
1268 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1269         .name           = "mailbox10",
1270         .class          = &dra7xx_mailbox_hwmod_class,
1271         .clkdm_name     = "l4cfg_clkdm",
1272         .prcm = {
1273                 .omap4 = {
1274                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1275                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1276                 },
1277         },
1278 };
1279
1280 /* mailbox11 */
1281 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1282         .name           = "mailbox11",
1283         .class          = &dra7xx_mailbox_hwmod_class,
1284         .clkdm_name     = "l4cfg_clkdm",
1285         .prcm = {
1286                 .omap4 = {
1287                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1288                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1289                 },
1290         },
1291 };
1292
1293 /* mailbox12 */
1294 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1295         .name           = "mailbox12",
1296         .class          = &dra7xx_mailbox_hwmod_class,
1297         .clkdm_name     = "l4cfg_clkdm",
1298         .prcm = {
1299                 .omap4 = {
1300                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1301                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1302                 },
1303         },
1304 };
1305
1306 /* mailbox13 */
1307 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1308         .name           = "mailbox13",
1309         .class          = &dra7xx_mailbox_hwmod_class,
1310         .clkdm_name     = "l4cfg_clkdm",
1311         .prcm = {
1312                 .omap4 = {
1313                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1314                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1315                 },
1316         },
1317 };
1318
1319 /*
1320  * 'mcspi' class
1321  *
1322  */
1323
1324 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1325         .rev_offs       = 0x0000,
1326         .sysc_offs      = 0x0010,
1327         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1328                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1329         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1330                            SIDLE_SMART_WKUP),
1331         .sysc_fields    = &omap_hwmod_sysc_type2,
1332 };
1333
1334 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1335         .name   = "mcspi",
1336         .sysc   = &dra7xx_mcspi_sysc,
1337         .rev    = OMAP4_MCSPI_REV,
1338 };
1339
1340 /* mcspi1 */
1341 /* mcspi1 dev_attr */
1342 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1343         .num_chipselect = 4,
1344 };
1345
1346 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1347         .name           = "mcspi1",
1348         .class          = &dra7xx_mcspi_hwmod_class,
1349         .clkdm_name     = "l4per_clkdm",
1350         .main_clk       = "func_48m_fclk",
1351         .prcm = {
1352                 .omap4 = {
1353                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1354                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1355                         .modulemode   = MODULEMODE_SWCTRL,
1356                 },
1357         },
1358         .dev_attr       = &mcspi1_dev_attr,
1359 };
1360
1361 /* mcspi2 */
1362 /* mcspi2 dev_attr */
1363 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1364         .num_chipselect = 2,
1365 };
1366
1367 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1368         .name           = "mcspi2",
1369         .class          = &dra7xx_mcspi_hwmod_class,
1370         .clkdm_name     = "l4per_clkdm",
1371         .main_clk       = "func_48m_fclk",
1372         .prcm = {
1373                 .omap4 = {
1374                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1375                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1376                         .modulemode   = MODULEMODE_SWCTRL,
1377                 },
1378         },
1379         .dev_attr       = &mcspi2_dev_attr,
1380 };
1381
1382 /* mcspi3 */
1383 /* mcspi3 dev_attr */
1384 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1385         .num_chipselect = 2,
1386 };
1387
1388 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1389         .name           = "mcspi3",
1390         .class          = &dra7xx_mcspi_hwmod_class,
1391         .clkdm_name     = "l4per_clkdm",
1392         .main_clk       = "func_48m_fclk",
1393         .prcm = {
1394                 .omap4 = {
1395                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1396                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1397                         .modulemode   = MODULEMODE_SWCTRL,
1398                 },
1399         },
1400         .dev_attr       = &mcspi3_dev_attr,
1401 };
1402
1403 /* mcspi4 */
1404 /* mcspi4 dev_attr */
1405 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1406         .num_chipselect = 1,
1407 };
1408
1409 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1410         .name           = "mcspi4",
1411         .class          = &dra7xx_mcspi_hwmod_class,
1412         .clkdm_name     = "l4per_clkdm",
1413         .main_clk       = "func_48m_fclk",
1414         .prcm = {
1415                 .omap4 = {
1416                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1417                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1418                         .modulemode   = MODULEMODE_SWCTRL,
1419                 },
1420         },
1421         .dev_attr       = &mcspi4_dev_attr,
1422 };
1423
1424 /*
1425  * 'mcasp' class
1426  *
1427  */
1428 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1429         .sysc_offs      = 0x0004,
1430         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1431         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1432         .sysc_fields    = &omap_hwmod_sysc_type3,
1433 };
1434
1435 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1436         .name   = "mcasp",
1437         .sysc   = &dra7xx_mcasp_sysc,
1438 };
1439
1440 /* mcasp1 */
1441 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1442         { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1443         { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1444 };
1445
1446 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1447         .name           = "mcasp1",
1448         .class          = &dra7xx_mcasp_hwmod_class,
1449         .clkdm_name     = "ipu_clkdm",
1450         .main_clk       = "mcasp1_aux_gfclk_mux",
1451         .flags          = HWMOD_OPT_CLKS_NEEDED,
1452         .prcm = {
1453                 .omap4 = {
1454                         .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1455                         .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1456                         .modulemode   = MODULEMODE_SWCTRL,
1457                 },
1458         },
1459         .opt_clks       = mcasp1_opt_clks,
1460         .opt_clks_cnt   = ARRAY_SIZE(mcasp1_opt_clks),
1461 };
1462
1463 /* mcasp2 */
1464 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1465         { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1466         { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1467 };
1468
1469 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1470         .name           = "mcasp2",
1471         .class          = &dra7xx_mcasp_hwmod_class,
1472         .clkdm_name     = "l4per2_clkdm",
1473         .main_clk       = "mcasp2_aux_gfclk_mux",
1474         .flags          = HWMOD_OPT_CLKS_NEEDED,
1475         .prcm = {
1476                 .omap4 = {
1477                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1478                         .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1479                         .modulemode   = MODULEMODE_SWCTRL,
1480                 },
1481         },
1482         .opt_clks       = mcasp2_opt_clks,
1483         .opt_clks_cnt   = ARRAY_SIZE(mcasp2_opt_clks),
1484 };
1485
1486 /* mcasp3 */
1487 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1488         { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1489 };
1490
1491 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1492         .name           = "mcasp3",
1493         .class          = &dra7xx_mcasp_hwmod_class,
1494         .clkdm_name     = "l4per2_clkdm",
1495         .main_clk       = "mcasp3_aux_gfclk_mux",
1496         .flags          = HWMOD_OPT_CLKS_NEEDED,
1497         .prcm = {
1498                 .omap4 = {
1499                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1500                         .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1501                         .modulemode   = MODULEMODE_SWCTRL,
1502                 },
1503         },
1504         .opt_clks       = mcasp3_opt_clks,
1505         .opt_clks_cnt   = ARRAY_SIZE(mcasp3_opt_clks),
1506 };
1507
1508 /* mcasp4 */
1509 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1510         { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1511 };
1512
1513 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1514         .name           = "mcasp4",
1515         .class          = &dra7xx_mcasp_hwmod_class,
1516         .clkdm_name     = "l4per2_clkdm",
1517         .main_clk       = "mcasp4_aux_gfclk_mux",
1518         .flags          = HWMOD_OPT_CLKS_NEEDED,
1519         .prcm = {
1520                 .omap4 = {
1521                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1522                         .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1523                         .modulemode   = MODULEMODE_SWCTRL,
1524                 },
1525         },
1526         .opt_clks       = mcasp4_opt_clks,
1527         .opt_clks_cnt   = ARRAY_SIZE(mcasp4_opt_clks),
1528 };
1529
1530 /* mcasp5 */
1531 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1532         { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1533 };
1534
1535 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1536         .name           = "mcasp5",
1537         .class          = &dra7xx_mcasp_hwmod_class,
1538         .clkdm_name     = "l4per2_clkdm",
1539         .main_clk       = "mcasp5_aux_gfclk_mux",
1540         .flags          = HWMOD_OPT_CLKS_NEEDED,
1541         .prcm = {
1542                 .omap4 = {
1543                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1544                         .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1545                         .modulemode   = MODULEMODE_SWCTRL,
1546                 },
1547         },
1548         .opt_clks       = mcasp5_opt_clks,
1549         .opt_clks_cnt   = ARRAY_SIZE(mcasp5_opt_clks),
1550 };
1551
1552 /* mcasp6 */
1553 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1554         { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1555 };
1556
1557 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1558         .name           = "mcasp6",
1559         .class          = &dra7xx_mcasp_hwmod_class,
1560         .clkdm_name     = "l4per2_clkdm",
1561         .main_clk       = "mcasp6_aux_gfclk_mux",
1562         .flags          = HWMOD_OPT_CLKS_NEEDED,
1563         .prcm = {
1564                 .omap4 = {
1565                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1566                         .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1567                         .modulemode   = MODULEMODE_SWCTRL,
1568                 },
1569         },
1570         .opt_clks       = mcasp6_opt_clks,
1571         .opt_clks_cnt   = ARRAY_SIZE(mcasp6_opt_clks),
1572 };
1573
1574 /* mcasp7 */
1575 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1576         { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1577 };
1578
1579 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1580         .name           = "mcasp7",
1581         .class          = &dra7xx_mcasp_hwmod_class,
1582         .clkdm_name     = "l4per2_clkdm",
1583         .main_clk       = "mcasp7_aux_gfclk_mux",
1584         .flags          = HWMOD_OPT_CLKS_NEEDED,
1585         .prcm = {
1586                 .omap4 = {
1587                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1588                         .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1589                         .modulemode   = MODULEMODE_SWCTRL,
1590                 },
1591         },
1592         .opt_clks       = mcasp7_opt_clks,
1593         .opt_clks_cnt   = ARRAY_SIZE(mcasp7_opt_clks),
1594 };
1595
1596 /* mcasp8 */
1597 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1598         { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1599 };
1600
1601 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1602         .name           = "mcasp8",
1603         .class          = &dra7xx_mcasp_hwmod_class,
1604         .clkdm_name     = "l4per2_clkdm",
1605         .main_clk       = "mcasp8_aux_gfclk_mux",
1606         .flags          = HWMOD_OPT_CLKS_NEEDED,
1607         .prcm = {
1608                 .omap4 = {
1609                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1610                         .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1611                         .modulemode   = MODULEMODE_SWCTRL,
1612                 },
1613         },
1614         .opt_clks       = mcasp8_opt_clks,
1615         .opt_clks_cnt   = ARRAY_SIZE(mcasp8_opt_clks),
1616 };
1617
1618 /*
1619  * 'mmc' class
1620  *
1621  */
1622
1623 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1624         .rev_offs       = 0x0000,
1625         .sysc_offs      = 0x0010,
1626         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1627                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1628                            SYSC_HAS_SOFTRESET),
1629         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1630                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1631                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1632         .sysc_fields    = &omap_hwmod_sysc_type2,
1633 };
1634
1635 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1636         .name   = "mmc",
1637         .sysc   = &dra7xx_mmc_sysc,
1638 };
1639
1640 /* mmc1 */
1641 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1642         { .role = "clk32k", .clk = "mmc1_clk32k" },
1643 };
1644
1645 /* mmc1 dev_attr */
1646 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1647         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1648 };
1649
1650 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1651         .name           = "mmc1",
1652         .class          = &dra7xx_mmc_hwmod_class,
1653         .clkdm_name     = "l3init_clkdm",
1654         .main_clk       = "mmc1_fclk_div",
1655         .prcm = {
1656                 .omap4 = {
1657                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1658                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1659                         .modulemode   = MODULEMODE_SWCTRL,
1660                 },
1661         },
1662         .opt_clks       = mmc1_opt_clks,
1663         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1664         .dev_attr       = &mmc1_dev_attr,
1665 };
1666
1667 /* mmc2 */
1668 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1669         { .role = "clk32k", .clk = "mmc2_clk32k" },
1670 };
1671
1672 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1673         .name           = "mmc2",
1674         .class          = &dra7xx_mmc_hwmod_class,
1675         .clkdm_name     = "l3init_clkdm",
1676         .main_clk       = "mmc2_fclk_div",
1677         .prcm = {
1678                 .omap4 = {
1679                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1680                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1681                         .modulemode   = MODULEMODE_SWCTRL,
1682                 },
1683         },
1684         .opt_clks       = mmc2_opt_clks,
1685         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1686 };
1687
1688 /* mmc3 */
1689 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1690         { .role = "clk32k", .clk = "mmc3_clk32k" },
1691 };
1692
1693 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1694         .name           = "mmc3",
1695         .class          = &dra7xx_mmc_hwmod_class,
1696         .clkdm_name     = "l4per_clkdm",
1697         .main_clk       = "mmc3_gfclk_div",
1698         .prcm = {
1699                 .omap4 = {
1700                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1701                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1702                         .modulemode   = MODULEMODE_SWCTRL,
1703                 },
1704         },
1705         .opt_clks       = mmc3_opt_clks,
1706         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1707 };
1708
1709 /* mmc4 */
1710 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1711         { .role = "clk32k", .clk = "mmc4_clk32k" },
1712 };
1713
1714 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1715         .name           = "mmc4",
1716         .class          = &dra7xx_mmc_hwmod_class,
1717         .clkdm_name     = "l4per_clkdm",
1718         .main_clk       = "mmc4_gfclk_div",
1719         .prcm = {
1720                 .omap4 = {
1721                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1722                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1723                         .modulemode   = MODULEMODE_SWCTRL,
1724                 },
1725         },
1726         .opt_clks       = mmc4_opt_clks,
1727         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1728 };
1729
1730 /*
1731  * 'mpu' class
1732  *
1733  */
1734
1735 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1736         .name   = "mpu",
1737 };
1738
1739 /* mpu */
1740 static struct omap_hwmod dra7xx_mpu_hwmod = {
1741         .name           = "mpu",
1742         .class          = &dra7xx_mpu_hwmod_class,
1743         .clkdm_name     = "mpu_clkdm",
1744         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1745         .main_clk       = "dpll_mpu_m2_ck",
1746         .prcm = {
1747                 .omap4 = {
1748                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1749                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1750                 },
1751         },
1752 };
1753
1754 /*
1755  * 'ocp2scp' class
1756  *
1757  */
1758
1759 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1760         .rev_offs       = 0x0000,
1761         .sysc_offs      = 0x0010,
1762         .syss_offs      = 0x0014,
1763         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1764                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1765         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1766         .sysc_fields    = &omap_hwmod_sysc_type1,
1767 };
1768
1769 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1770         .name   = "ocp2scp",
1771         .sysc   = &dra7xx_ocp2scp_sysc,
1772 };
1773
1774 /* ocp2scp1 */
1775 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1776         .name           = "ocp2scp1",
1777         .class          = &dra7xx_ocp2scp_hwmod_class,
1778         .clkdm_name     = "l3init_clkdm",
1779         .main_clk       = "l4_root_clk_div",
1780         .prcm = {
1781                 .omap4 = {
1782                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1783                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1784                         .modulemode   = MODULEMODE_HWCTRL,
1785                 },
1786         },
1787 };
1788
1789 /* ocp2scp3 */
1790 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1791         .name           = "ocp2scp3",
1792         .class          = &dra7xx_ocp2scp_hwmod_class,
1793         .clkdm_name     = "l3init_clkdm",
1794         .main_clk       = "l4_root_clk_div",
1795         .prcm = {
1796                 .omap4 = {
1797                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1798                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1799                         .modulemode   = MODULEMODE_HWCTRL,
1800                 },
1801         },
1802 };
1803
1804 /*
1805  * 'PCIE' class
1806  *
1807  */
1808
1809 /*
1810  * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1811  * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1812  * associated with an IP automatically leaving the driver to handle that
1813  * by itself. This does not work for PCIeSS which needs the reset lines
1814  * deasserted for the driver to start accessing registers.
1815  *
1816  * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1817  * lines after asserting them.
1818  */
1819 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1820 {
1821         int i;
1822
1823         for (i = 0; i < oh->rst_lines_cnt; i++) {
1824                 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1825                 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1826         }
1827
1828         return 0;
1829 }
1830
1831 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1832         .name   = "pcie",
1833         .reset  = dra7xx_pciess_reset,
1834 };
1835
1836 /* pcie1 */
1837 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1838         { .name = "pcie", .rst_shift = 0 },
1839 };
1840
1841 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1842         .name           = "pcie1",
1843         .class          = &dra7xx_pciess_hwmod_class,
1844         .clkdm_name     = "pcie_clkdm",
1845         .rst_lines      = dra7xx_pciess1_resets,
1846         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess1_resets),
1847         .main_clk       = "l4_root_clk_div",
1848         .prcm = {
1849                 .omap4 = {
1850                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1851                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1852                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1853                         .modulemode   = MODULEMODE_SWCTRL,
1854                 },
1855         },
1856 };
1857
1858 /* pcie2 */
1859 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1860         { .name = "pcie", .rst_shift = 1 },
1861 };
1862
1863 /* pcie2 */
1864 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1865         .name           = "pcie2",
1866         .class          = &dra7xx_pciess_hwmod_class,
1867         .clkdm_name     = "pcie_clkdm",
1868         .rst_lines      = dra7xx_pciess2_resets,
1869         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess2_resets),
1870         .main_clk       = "l4_root_clk_div",
1871         .prcm = {
1872                 .omap4 = {
1873                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1874                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1875                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1876                         .modulemode   = MODULEMODE_SWCTRL,
1877                 },
1878         },
1879 };
1880
1881 /*
1882  * 'qspi' class
1883  *
1884  */
1885
1886 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1887         .sysc_offs      = 0x0010,
1888         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1889         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1890                            SIDLE_SMART_WKUP),
1891         .sysc_fields    = &omap_hwmod_sysc_type2,
1892 };
1893
1894 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1895         .name   = "qspi",
1896         .sysc   = &dra7xx_qspi_sysc,
1897 };
1898
1899 /* qspi */
1900 static struct omap_hwmod dra7xx_qspi_hwmod = {
1901         .name           = "qspi",
1902         .class          = &dra7xx_qspi_hwmod_class,
1903         .clkdm_name     = "l4per2_clkdm",
1904         .main_clk       = "qspi_gfclk_div",
1905         .prcm = {
1906                 .omap4 = {
1907                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1908                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1909                         .modulemode   = MODULEMODE_SWCTRL,
1910                 },
1911         },
1912 };
1913
1914 /*
1915  * 'rtcss' class
1916  *
1917  */
1918 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1919         .sysc_offs      = 0x0078,
1920         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1921         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1922                            SIDLE_SMART_WKUP),
1923         .sysc_fields    = &omap_hwmod_sysc_type3,
1924 };
1925
1926 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1927         .name   = "rtcss",
1928         .sysc   = &dra7xx_rtcss_sysc,
1929         .unlock = &omap_hwmod_rtc_unlock,
1930         .lock   = &omap_hwmod_rtc_lock,
1931 };
1932
1933 /* rtcss */
1934 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1935         .name           = "rtcss",
1936         .class          = &dra7xx_rtcss_hwmod_class,
1937         .clkdm_name     = "rtc_clkdm",
1938         .main_clk       = "sys_32k_ck",
1939         .prcm = {
1940                 .omap4 = {
1941                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1942                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1943                         .modulemode   = MODULEMODE_SWCTRL,
1944                 },
1945         },
1946 };
1947
1948 /*
1949  * 'sata' class
1950  *
1951  */
1952
1953 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1954         .sysc_offs      = 0x0000,
1955         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1956         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1957                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1958                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1959         .sysc_fields    = &omap_hwmod_sysc_type2,
1960 };
1961
1962 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1963         .name   = "sata",
1964         .sysc   = &dra7xx_sata_sysc,
1965 };
1966
1967 /* sata */
1968
1969 static struct omap_hwmod dra7xx_sata_hwmod = {
1970         .name           = "sata",
1971         .class          = &dra7xx_sata_hwmod_class,
1972         .clkdm_name     = "l3init_clkdm",
1973         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1974         .main_clk       = "func_48m_fclk",
1975         .mpu_rt_idx     = 1,
1976         .prcm = {
1977                 .omap4 = {
1978                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1979                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1980                         .modulemode   = MODULEMODE_SWCTRL,
1981                 },
1982         },
1983 };
1984
1985 /*
1986  * 'smartreflex' class
1987  *
1988  */
1989
1990 /* The IP is not compliant to type1 / type2 scheme */
1991 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1992         .sidle_shift    = 24,
1993         .enwkup_shift   = 26,
1994 };
1995
1996 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1997         .sysc_offs      = 0x0038,
1998         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1999         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2000                            SIDLE_SMART_WKUP),
2001         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2002 };
2003
2004 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2005         .name   = "smartreflex",
2006         .sysc   = &dra7xx_smartreflex_sysc,
2007         .rev    = 2,
2008 };
2009
2010 /* smartreflex_core */
2011 /* smartreflex_core dev_attr */
2012 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2013         .sensor_voltdm_name     = "core",
2014 };
2015
2016 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2017         .name           = "smartreflex_core",
2018         .class          = &dra7xx_smartreflex_hwmod_class,
2019         .clkdm_name     = "coreaon_clkdm",
2020         .main_clk       = "wkupaon_iclk_mux",
2021         .prcm = {
2022                 .omap4 = {
2023                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2024                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2025                         .modulemode   = MODULEMODE_SWCTRL,
2026                 },
2027         },
2028         .dev_attr       = &smartreflex_core_dev_attr,
2029 };
2030
2031 /* smartreflex_mpu */
2032 /* smartreflex_mpu dev_attr */
2033 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2034         .sensor_voltdm_name     = "mpu",
2035 };
2036
2037 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2038         .name           = "smartreflex_mpu",
2039         .class          = &dra7xx_smartreflex_hwmod_class,
2040         .clkdm_name     = "coreaon_clkdm",
2041         .main_clk       = "wkupaon_iclk_mux",
2042         .prcm = {
2043                 .omap4 = {
2044                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2045                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2046                         .modulemode   = MODULEMODE_SWCTRL,
2047                 },
2048         },
2049         .dev_attr       = &smartreflex_mpu_dev_attr,
2050 };
2051
2052 /*
2053  * 'spinlock' class
2054  *
2055  */
2056
2057 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2058         .rev_offs       = 0x0000,
2059         .sysc_offs      = 0x0010,
2060         .syss_offs      = 0x0014,
2061         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2062                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2063                            SYSS_HAS_RESET_STATUS),
2064         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2065         .sysc_fields    = &omap_hwmod_sysc_type1,
2066 };
2067
2068 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2069         .name   = "spinlock",
2070         .sysc   = &dra7xx_spinlock_sysc,
2071 };
2072
2073 /* spinlock */
2074 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2075         .name           = "spinlock",
2076         .class          = &dra7xx_spinlock_hwmod_class,
2077         .clkdm_name     = "l4cfg_clkdm",
2078         .main_clk       = "l3_iclk_div",
2079         .prcm = {
2080                 .omap4 = {
2081                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2082                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2083                 },
2084         },
2085 };
2086
2087 /*
2088  * 'timer' class
2089  *
2090  * This class contains several variants: ['timer_1ms', 'timer_secure',
2091  * 'timer']
2092  */
2093
2094 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2095         .rev_offs       = 0x0000,
2096         .sysc_offs      = 0x0010,
2097         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2098                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2099         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2100                            SIDLE_SMART_WKUP),
2101         .sysc_fields    = &omap_hwmod_sysc_type2,
2102 };
2103
2104 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2105         .name   = "timer",
2106         .sysc   = &dra7xx_timer_1ms_sysc,
2107 };
2108
2109 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2110         .rev_offs       = 0x0000,
2111         .sysc_offs      = 0x0010,
2112         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2113                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2114         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2115                            SIDLE_SMART_WKUP),
2116         .sysc_fields    = &omap_hwmod_sysc_type2,
2117 };
2118
2119 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2120         .name   = "timer",
2121         .sysc   = &dra7xx_timer_sysc,
2122 };
2123
2124 /* timer1 */
2125 static struct omap_hwmod dra7xx_timer1_hwmod = {
2126         .name           = "timer1",
2127         .class          = &dra7xx_timer_1ms_hwmod_class,
2128         .clkdm_name     = "wkupaon_clkdm",
2129         .main_clk       = "timer1_gfclk_mux",
2130         .prcm = {
2131                 .omap4 = {
2132                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2133                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2134                         .modulemode   = MODULEMODE_SWCTRL,
2135                 },
2136         },
2137 };
2138
2139 /* timer2 */
2140 static struct omap_hwmod dra7xx_timer2_hwmod = {
2141         .name           = "timer2",
2142         .class          = &dra7xx_timer_1ms_hwmod_class,
2143         .clkdm_name     = "l4per_clkdm",
2144         .main_clk       = "timer2_gfclk_mux",
2145         .prcm = {
2146                 .omap4 = {
2147                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2148                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2149                         .modulemode   = MODULEMODE_SWCTRL,
2150                 },
2151         },
2152 };
2153
2154 /* timer3 */
2155 static struct omap_hwmod dra7xx_timer3_hwmod = {
2156         .name           = "timer3",
2157         .class          = &dra7xx_timer_hwmod_class,
2158         .clkdm_name     = "l4per_clkdm",
2159         .main_clk       = "timer3_gfclk_mux",
2160         .prcm = {
2161                 .omap4 = {
2162                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2163                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2164                         .modulemode   = MODULEMODE_SWCTRL,
2165                 },
2166         },
2167 };
2168
2169 /* timer4 */
2170 static struct omap_hwmod dra7xx_timer4_hwmod = {
2171         .name           = "timer4",
2172         .class          = &dra7xx_timer_hwmod_class,
2173         .clkdm_name     = "l4per_clkdm",
2174         .main_clk       = "timer4_gfclk_mux",
2175         .prcm = {
2176                 .omap4 = {
2177                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2178                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2179                         .modulemode   = MODULEMODE_SWCTRL,
2180                 },
2181         },
2182 };
2183
2184 /* timer5 */
2185 static struct omap_hwmod dra7xx_timer5_hwmod = {
2186         .name           = "timer5",
2187         .class          = &dra7xx_timer_hwmod_class,
2188         .clkdm_name     = "ipu_clkdm",
2189         .main_clk       = "timer5_gfclk_mux",
2190         .prcm = {
2191                 .omap4 = {
2192                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2193                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2194                         .modulemode   = MODULEMODE_SWCTRL,
2195                 },
2196         },
2197 };
2198
2199 /* timer6 */
2200 static struct omap_hwmod dra7xx_timer6_hwmod = {
2201         .name           = "timer6",
2202         .class          = &dra7xx_timer_hwmod_class,
2203         .clkdm_name     = "ipu_clkdm",
2204         .main_clk       = "timer6_gfclk_mux",
2205         .prcm = {
2206                 .omap4 = {
2207                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2208                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2209                         .modulemode   = MODULEMODE_SWCTRL,
2210                 },
2211         },
2212 };
2213
2214 /* timer7 */
2215 static struct omap_hwmod dra7xx_timer7_hwmod = {
2216         .name           = "timer7",
2217         .class          = &dra7xx_timer_hwmod_class,
2218         .clkdm_name     = "ipu_clkdm",
2219         .main_clk       = "timer7_gfclk_mux",
2220         .prcm = {
2221                 .omap4 = {
2222                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2223                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2224                         .modulemode   = MODULEMODE_SWCTRL,
2225                 },
2226         },
2227 };
2228
2229 /* timer8 */
2230 static struct omap_hwmod dra7xx_timer8_hwmod = {
2231         .name           = "timer8",
2232         .class          = &dra7xx_timer_hwmod_class,
2233         .clkdm_name     = "ipu_clkdm",
2234         .main_clk       = "timer8_gfclk_mux",
2235         .prcm = {
2236                 .omap4 = {
2237                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2238                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2239                         .modulemode   = MODULEMODE_SWCTRL,
2240                 },
2241         },
2242 };
2243
2244 /* timer9 */
2245 static struct omap_hwmod dra7xx_timer9_hwmod = {
2246         .name           = "timer9",
2247         .class          = &dra7xx_timer_hwmod_class,
2248         .clkdm_name     = "l4per_clkdm",
2249         .main_clk       = "timer9_gfclk_mux",
2250         .prcm = {
2251                 .omap4 = {
2252                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2253                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2254                         .modulemode   = MODULEMODE_SWCTRL,
2255                 },
2256         },
2257 };
2258
2259 /* timer10 */
2260 static struct omap_hwmod dra7xx_timer10_hwmod = {
2261         .name           = "timer10",
2262         .class          = &dra7xx_timer_1ms_hwmod_class,
2263         .clkdm_name     = "l4per_clkdm",
2264         .main_clk       = "timer10_gfclk_mux",
2265         .prcm = {
2266                 .omap4 = {
2267                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2268                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2269                         .modulemode   = MODULEMODE_SWCTRL,
2270                 },
2271         },
2272 };
2273
2274 /* timer11 */
2275 static struct omap_hwmod dra7xx_timer11_hwmod = {
2276         .name           = "timer11",
2277         .class          = &dra7xx_timer_hwmod_class,
2278         .clkdm_name     = "l4per_clkdm",
2279         .main_clk       = "timer11_gfclk_mux",
2280         .prcm = {
2281                 .omap4 = {
2282                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2283                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2284                         .modulemode   = MODULEMODE_SWCTRL,
2285                 },
2286         },
2287 };
2288
2289 /* timer12 */
2290 static struct omap_hwmod dra7xx_timer12_hwmod = {
2291         .name           = "timer12",
2292         .class          = &dra7xx_timer_hwmod_class,
2293         .clkdm_name     = "wkupaon_clkdm",
2294         .main_clk       = "secure_32k_clk_src_ck",
2295         .prcm = {
2296                 .omap4 = {
2297                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2298                         .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2299                 },
2300         },
2301 };
2302
2303 /* timer13 */
2304 static struct omap_hwmod dra7xx_timer13_hwmod = {
2305         .name           = "timer13",
2306         .class          = &dra7xx_timer_hwmod_class,
2307         .clkdm_name     = "l4per3_clkdm",
2308         .main_clk       = "timer13_gfclk_mux",
2309         .prcm = {
2310                 .omap4 = {
2311                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2312                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2313                         .modulemode   = MODULEMODE_SWCTRL,
2314                 },
2315         },
2316 };
2317
2318 /* timer14 */
2319 static struct omap_hwmod dra7xx_timer14_hwmod = {
2320         .name           = "timer14",
2321         .class          = &dra7xx_timer_hwmod_class,
2322         .clkdm_name     = "l4per3_clkdm",
2323         .main_clk       = "timer14_gfclk_mux",
2324         .prcm = {
2325                 .omap4 = {
2326                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2327                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2328                         .modulemode   = MODULEMODE_SWCTRL,
2329                 },
2330         },
2331 };
2332
2333 /* timer15 */
2334 static struct omap_hwmod dra7xx_timer15_hwmod = {
2335         .name           = "timer15",
2336         .class          = &dra7xx_timer_hwmod_class,
2337         .clkdm_name     = "l4per3_clkdm",
2338         .main_clk       = "timer15_gfclk_mux",
2339         .prcm = {
2340                 .omap4 = {
2341                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2342                         .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2343                         .modulemode   = MODULEMODE_SWCTRL,
2344                 },
2345         },
2346 };
2347
2348 /* timer16 */
2349 static struct omap_hwmod dra7xx_timer16_hwmod = {
2350         .name           = "timer16",
2351         .class          = &dra7xx_timer_hwmod_class,
2352         .clkdm_name     = "l4per3_clkdm",
2353         .main_clk       = "timer16_gfclk_mux",
2354         .prcm = {
2355                 .omap4 = {
2356                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2357                         .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2358                         .modulemode   = MODULEMODE_SWCTRL,
2359                 },
2360         },
2361 };
2362
2363 /*
2364  * 'uart' class
2365  *
2366  */
2367
2368 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2369         .rev_offs       = 0x0050,
2370         .sysc_offs      = 0x0054,
2371         .syss_offs      = 0x0058,
2372         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2373                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2374                            SYSS_HAS_RESET_STATUS),
2375         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2376                            SIDLE_SMART_WKUP),
2377         .sysc_fields    = &omap_hwmod_sysc_type1,
2378 };
2379
2380 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2381         .name   = "uart",
2382         .sysc   = &dra7xx_uart_sysc,
2383 };
2384
2385 /* uart1 */
2386 static struct omap_hwmod dra7xx_uart1_hwmod = {
2387         .name           = "uart1",
2388         .class          = &dra7xx_uart_hwmod_class,
2389         .clkdm_name     = "l4per_clkdm",
2390         .main_clk       = "uart1_gfclk_mux",
2391         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2392         .prcm = {
2393                 .omap4 = {
2394                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2395                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2396                         .modulemode   = MODULEMODE_SWCTRL,
2397                 },
2398         },
2399 };
2400
2401 /* uart2 */
2402 static struct omap_hwmod dra7xx_uart2_hwmod = {
2403         .name           = "uart2",
2404         .class          = &dra7xx_uart_hwmod_class,
2405         .clkdm_name     = "l4per_clkdm",
2406         .main_clk       = "uart2_gfclk_mux",
2407         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2408         .prcm = {
2409                 .omap4 = {
2410                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2411                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2412                         .modulemode   = MODULEMODE_SWCTRL,
2413                 },
2414         },
2415 };
2416
2417 /* uart3 */
2418 static struct omap_hwmod dra7xx_uart3_hwmod = {
2419         .name           = "uart3",
2420         .class          = &dra7xx_uart_hwmod_class,
2421         .clkdm_name     = "l4per_clkdm",
2422         .main_clk       = "uart3_gfclk_mux",
2423         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2424         .prcm = {
2425                 .omap4 = {
2426                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2427                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2428                         .modulemode   = MODULEMODE_SWCTRL,
2429                 },
2430         },
2431 };
2432
2433 /* uart4 */
2434 static struct omap_hwmod dra7xx_uart4_hwmod = {
2435         .name           = "uart4",
2436         .class          = &dra7xx_uart_hwmod_class,
2437         .clkdm_name     = "l4per_clkdm",
2438         .main_clk       = "uart4_gfclk_mux",
2439         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2440         .prcm = {
2441                 .omap4 = {
2442                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2443                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2444                         .modulemode   = MODULEMODE_SWCTRL,
2445                 },
2446         },
2447 };
2448
2449 /* uart5 */
2450 static struct omap_hwmod dra7xx_uart5_hwmod = {
2451         .name           = "uart5",
2452         .class          = &dra7xx_uart_hwmod_class,
2453         .clkdm_name     = "l4per_clkdm",
2454         .main_clk       = "uart5_gfclk_mux",
2455         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2456         .prcm = {
2457                 .omap4 = {
2458                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2459                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2460                         .modulemode   = MODULEMODE_SWCTRL,
2461                 },
2462         },
2463 };
2464
2465 /* uart6 */
2466 static struct omap_hwmod dra7xx_uart6_hwmod = {
2467         .name           = "uart6",
2468         .class          = &dra7xx_uart_hwmod_class,
2469         .clkdm_name     = "ipu_clkdm",
2470         .main_clk       = "uart6_gfclk_mux",
2471         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2472         .prcm = {
2473                 .omap4 = {
2474                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2475                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2476                         .modulemode   = MODULEMODE_SWCTRL,
2477                 },
2478         },
2479 };
2480
2481 /* uart7 */
2482 static struct omap_hwmod dra7xx_uart7_hwmod = {
2483         .name           = "uart7",
2484         .class          = &dra7xx_uart_hwmod_class,
2485         .clkdm_name     = "l4per2_clkdm",
2486         .main_clk       = "uart7_gfclk_mux",
2487         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2488         .prcm = {
2489                 .omap4 = {
2490                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2491                         .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2492                         .modulemode   = MODULEMODE_SWCTRL,
2493                 },
2494         },
2495 };
2496
2497 /* uart8 */
2498 static struct omap_hwmod dra7xx_uart8_hwmod = {
2499         .name           = "uart8",
2500         .class          = &dra7xx_uart_hwmod_class,
2501         .clkdm_name     = "l4per2_clkdm",
2502         .main_clk       = "uart8_gfclk_mux",
2503         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2504         .prcm = {
2505                 .omap4 = {
2506                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2507                         .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2508                         .modulemode   = MODULEMODE_SWCTRL,
2509                 },
2510         },
2511 };
2512
2513 /* uart9 */
2514 static struct omap_hwmod dra7xx_uart9_hwmod = {
2515         .name           = "uart9",
2516         .class          = &dra7xx_uart_hwmod_class,
2517         .clkdm_name     = "l4per2_clkdm",
2518         .main_clk       = "uart9_gfclk_mux",
2519         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2520         .prcm = {
2521                 .omap4 = {
2522                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2523                         .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2524                         .modulemode   = MODULEMODE_SWCTRL,
2525                 },
2526         },
2527 };
2528
2529 /* uart10 */
2530 static struct omap_hwmod dra7xx_uart10_hwmod = {
2531         .name           = "uart10",
2532         .class          = &dra7xx_uart_hwmod_class,
2533         .clkdm_name     = "wkupaon_clkdm",
2534         .main_clk       = "uart10_gfclk_mux",
2535         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2536         .prcm = {
2537                 .omap4 = {
2538                         .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2539                         .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2540                         .modulemode   = MODULEMODE_SWCTRL,
2541                 },
2542         },
2543 };
2544
2545 /*
2546  * 'usb_otg_ss' class
2547  *
2548  */
2549
2550 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2551         .rev_offs       = 0x0000,
2552         .sysc_offs      = 0x0010,
2553         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2554                            SYSC_HAS_SIDLEMODE),
2555         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2556                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2557                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2558         .sysc_fields    = &omap_hwmod_sysc_type2,
2559 };
2560
2561 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2562         .name   = "usb_otg_ss",
2563         .sysc   = &dra7xx_usb_otg_ss_sysc,
2564 };
2565
2566 /* usb_otg_ss1 */
2567 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2568         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2569 };
2570
2571 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2572         .name           = "usb_otg_ss1",
2573         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2574         .clkdm_name     = "l3init_clkdm",
2575         .main_clk       = "dpll_core_h13x2_ck",
2576         .prcm = {
2577                 .omap4 = {
2578                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2579                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2580                         .modulemode   = MODULEMODE_HWCTRL,
2581                 },
2582         },
2583         .opt_clks       = usb_otg_ss1_opt_clks,
2584         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2585 };
2586
2587 /* usb_otg_ss2 */
2588 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2589         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2590 };
2591
2592 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2593         .name           = "usb_otg_ss2",
2594         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2595         .clkdm_name     = "l3init_clkdm",
2596         .main_clk       = "dpll_core_h13x2_ck",
2597         .prcm = {
2598                 .omap4 = {
2599                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2600                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2601                         .modulemode   = MODULEMODE_HWCTRL,
2602                 },
2603         },
2604         .opt_clks       = usb_otg_ss2_opt_clks,
2605         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2606 };
2607
2608 /* usb_otg_ss3 */
2609 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2610         .name           = "usb_otg_ss3",
2611         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2612         .clkdm_name     = "l3init_clkdm",
2613         .main_clk       = "dpll_core_h13x2_ck",
2614         .prcm = {
2615                 .omap4 = {
2616                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2617                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2618                         .modulemode   = MODULEMODE_HWCTRL,
2619                 },
2620         },
2621 };
2622
2623 /* usb_otg_ss4 */
2624 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2625         .name           = "usb_otg_ss4",
2626         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2627         .clkdm_name     = "l3init_clkdm",
2628         .main_clk       = "dpll_core_h13x2_ck",
2629         .prcm = {
2630                 .omap4 = {
2631                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2632                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2633                         .modulemode   = MODULEMODE_HWCTRL,
2634                 },
2635         },
2636 };
2637
2638 /*
2639  * 'vcp' class
2640  *
2641  */
2642
2643 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2644         .name   = "vcp",
2645 };
2646
2647 /* vcp1 */
2648 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2649         .name           = "vcp1",
2650         .class          = &dra7xx_vcp_hwmod_class,
2651         .clkdm_name     = "l3main1_clkdm",
2652         .main_clk       = "l3_iclk_div",
2653         .prcm = {
2654                 .omap4 = {
2655                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2656                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2657                 },
2658         },
2659 };
2660
2661 /* vcp2 */
2662 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2663         .name           = "vcp2",
2664         .class          = &dra7xx_vcp_hwmod_class,
2665         .clkdm_name     = "l3main1_clkdm",
2666         .main_clk       = "l3_iclk_div",
2667         .prcm = {
2668                 .omap4 = {
2669                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2670                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2671                 },
2672         },
2673 };
2674
2675 /*
2676  * 'wd_timer' class
2677  *
2678  */
2679
2680 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2681         .rev_offs       = 0x0000,
2682         .sysc_offs      = 0x0010,
2683         .syss_offs      = 0x0014,
2684         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2685                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2686         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2687                            SIDLE_SMART_WKUP),
2688         .sysc_fields    = &omap_hwmod_sysc_type1,
2689 };
2690
2691 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2692         .name           = "wd_timer",
2693         .sysc           = &dra7xx_wd_timer_sysc,
2694         .pre_shutdown   = &omap2_wd_timer_disable,
2695         .reset          = &omap2_wd_timer_reset,
2696 };
2697
2698 /* wd_timer2 */
2699 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2700         .name           = "wd_timer2",
2701         .class          = &dra7xx_wd_timer_hwmod_class,
2702         .clkdm_name     = "wkupaon_clkdm",
2703         .main_clk       = "sys_32k_ck",
2704         .prcm = {
2705                 .omap4 = {
2706                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2707                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2708                         .modulemode   = MODULEMODE_SWCTRL,
2709                 },
2710         },
2711 };
2712
2713
2714 /*
2715  * Interfaces
2716  */
2717
2718 /* l3_main_1 -> dmm */
2719 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2720         .master         = &dra7xx_l3_main_1_hwmod,
2721         .slave          = &dra7xx_dmm_hwmod,
2722         .clk            = "l3_iclk_div",
2723         .user           = OCP_USER_SDMA,
2724 };
2725
2726 /* l3_main_2 -> l3_instr */
2727 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2728         .master         = &dra7xx_l3_main_2_hwmod,
2729         .slave          = &dra7xx_l3_instr_hwmod,
2730         .clk            = "l3_iclk_div",
2731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2732 };
2733
2734 /* l4_cfg -> l3_main_1 */
2735 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2736         .master         = &dra7xx_l4_cfg_hwmod,
2737         .slave          = &dra7xx_l3_main_1_hwmod,
2738         .clk            = "l3_iclk_div",
2739         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2740 };
2741
2742 /* mpu -> l3_main_1 */
2743 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2744         .master         = &dra7xx_mpu_hwmod,
2745         .slave          = &dra7xx_l3_main_1_hwmod,
2746         .clk            = "l3_iclk_div",
2747         .user           = OCP_USER_MPU,
2748 };
2749
2750 /* l3_main_1 -> l3_main_2 */
2751 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2752         .master         = &dra7xx_l3_main_1_hwmod,
2753         .slave          = &dra7xx_l3_main_2_hwmod,
2754         .clk            = "l3_iclk_div",
2755         .user           = OCP_USER_MPU,
2756 };
2757
2758 /* l4_cfg -> l3_main_2 */
2759 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2760         .master         = &dra7xx_l4_cfg_hwmod,
2761         .slave          = &dra7xx_l3_main_2_hwmod,
2762         .clk            = "l3_iclk_div",
2763         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2764 };
2765
2766 /* l3_main_1 -> l4_cfg */
2767 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2768         .master         = &dra7xx_l3_main_1_hwmod,
2769         .slave          = &dra7xx_l4_cfg_hwmod,
2770         .clk            = "l3_iclk_div",
2771         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2772 };
2773
2774 /* l3_main_1 -> l4_per1 */
2775 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2776         .master         = &dra7xx_l3_main_1_hwmod,
2777         .slave          = &dra7xx_l4_per1_hwmod,
2778         .clk            = "l3_iclk_div",
2779         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2780 };
2781
2782 /* l3_main_1 -> l4_per2 */
2783 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2784         .master         = &dra7xx_l3_main_1_hwmod,
2785         .slave          = &dra7xx_l4_per2_hwmod,
2786         .clk            = "l3_iclk_div",
2787         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2788 };
2789
2790 /* l3_main_1 -> l4_per3 */
2791 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2792         .master         = &dra7xx_l3_main_1_hwmod,
2793         .slave          = &dra7xx_l4_per3_hwmod,
2794         .clk            = "l3_iclk_div",
2795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2796 };
2797
2798 /* l3_main_1 -> l4_wkup */
2799 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2800         .master         = &dra7xx_l3_main_1_hwmod,
2801         .slave          = &dra7xx_l4_wkup_hwmod,
2802         .clk            = "wkupaon_iclk_mux",
2803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2804 };
2805
2806 /* l4_per2 -> atl */
2807 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2808         .master         = &dra7xx_l4_per2_hwmod,
2809         .slave          = &dra7xx_atl_hwmod,
2810         .clk            = "l3_iclk_div",
2811         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2812 };
2813
2814 /* l3_main_1 -> bb2d */
2815 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2816         .master         = &dra7xx_l3_main_1_hwmod,
2817         .slave          = &dra7xx_bb2d_hwmod,
2818         .clk            = "l3_iclk_div",
2819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2820 };
2821
2822 /* l4_wkup -> counter_32k */
2823 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2824         .master         = &dra7xx_l4_wkup_hwmod,
2825         .slave          = &dra7xx_counter_32k_hwmod,
2826         .clk            = "wkupaon_iclk_mux",
2827         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2828 };
2829
2830 /* l4_wkup -> ctrl_module_wkup */
2831 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2832         .master         = &dra7xx_l4_wkup_hwmod,
2833         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
2834         .clk            = "wkupaon_iclk_mux",
2835         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2836 };
2837
2838 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2839         .master         = &dra7xx_l4_per2_hwmod,
2840         .slave          = &dra7xx_gmac_hwmod,
2841         .clk            = "dpll_gmac_ck",
2842         .user           = OCP_USER_MPU,
2843 };
2844
2845 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2846         .master         = &dra7xx_gmac_hwmod,
2847         .slave          = &dra7xx_mdio_hwmod,
2848         .user           = OCP_USER_MPU,
2849 };
2850
2851 /* l4_wkup -> dcan1 */
2852 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2853         .master         = &dra7xx_l4_wkup_hwmod,
2854         .slave          = &dra7xx_dcan1_hwmod,
2855         .clk            = "wkupaon_iclk_mux",
2856         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2857 };
2858
2859 /* l4_per2 -> dcan2 */
2860 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2861         .master         = &dra7xx_l4_per2_hwmod,
2862         .slave          = &dra7xx_dcan2_hwmod,
2863         .clk            = "l3_iclk_div",
2864         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2865 };
2866
2867 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2868         {
2869                 .pa_start       = 0x4a056000,
2870                 .pa_end         = 0x4a056fff,
2871                 .flags          = ADDR_TYPE_RT
2872         },
2873         { }
2874 };
2875
2876 /* l4_cfg -> dma_system */
2877 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2878         .master         = &dra7xx_l4_cfg_hwmod,
2879         .slave          = &dra7xx_dma_system_hwmod,
2880         .clk            = "l3_iclk_div",
2881         .addr           = dra7xx_dma_system_addrs,
2882         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2883 };
2884
2885 /* l3_main_1 -> tpcc */
2886 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2887         .master         = &dra7xx_l3_main_1_hwmod,
2888         .slave          = &dra7xx_tpcc_hwmod,
2889         .clk            = "l3_iclk_div",
2890         .user           = OCP_USER_MPU,
2891 };
2892
2893 /* l3_main_1 -> tptc0 */
2894 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
2895         .master         = &dra7xx_l3_main_1_hwmod,
2896         .slave          = &dra7xx_tptc0_hwmod,
2897         .clk            = "l3_iclk_div",
2898         .user           = OCP_USER_MPU,
2899 };
2900
2901 /* l3_main_1 -> tptc1 */
2902 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
2903         .master         = &dra7xx_l3_main_1_hwmod,
2904         .slave          = &dra7xx_tptc1_hwmod,
2905         .clk            = "l3_iclk_div",
2906         .user           = OCP_USER_MPU,
2907 };
2908
2909 /* l3_main_1 -> dss */
2910 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2911         .master         = &dra7xx_l3_main_1_hwmod,
2912         .slave          = &dra7xx_dss_hwmod,
2913         .clk            = "l3_iclk_div",
2914         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2915 };
2916
2917 /* l3_main_1 -> dispc */
2918 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2919         .master         = &dra7xx_l3_main_1_hwmod,
2920         .slave          = &dra7xx_dss_dispc_hwmod,
2921         .clk            = "l3_iclk_div",
2922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2923 };
2924
2925 /* l3_main_1 -> dispc */
2926 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2927         .master         = &dra7xx_l3_main_1_hwmod,
2928         .slave          = &dra7xx_dss_hdmi_hwmod,
2929         .clk            = "l3_iclk_div",
2930         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2931 };
2932
2933 /* l4_per2 -> mcasp1 */
2934 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
2935         .master         = &dra7xx_l4_per2_hwmod,
2936         .slave          = &dra7xx_mcasp1_hwmod,
2937         .clk            = "l4_root_clk_div",
2938         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2939 };
2940
2941 /* l3_main_1 -> mcasp1 */
2942 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
2943         .master         = &dra7xx_l3_main_1_hwmod,
2944         .slave          = &dra7xx_mcasp1_hwmod,
2945         .clk            = "l3_iclk_div",
2946         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2947 };
2948
2949 /* l4_per2 -> mcasp2 */
2950 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
2951         .master         = &dra7xx_l4_per2_hwmod,
2952         .slave          = &dra7xx_mcasp2_hwmod,
2953         .clk            = "l4_root_clk_div",
2954         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2955 };
2956
2957 /* l3_main_1 -> mcasp2 */
2958 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
2959         .master         = &dra7xx_l3_main_1_hwmod,
2960         .slave          = &dra7xx_mcasp2_hwmod,
2961         .clk            = "l3_iclk_div",
2962         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2963 };
2964
2965 /* l4_per2 -> mcasp3 */
2966 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
2967         .master         = &dra7xx_l4_per2_hwmod,
2968         .slave          = &dra7xx_mcasp3_hwmod,
2969         .clk            = "l4_root_clk_div",
2970         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2971 };
2972
2973 /* l3_main_1 -> mcasp3 */
2974 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
2975         .master         = &dra7xx_l3_main_1_hwmod,
2976         .slave          = &dra7xx_mcasp3_hwmod,
2977         .clk            = "l3_iclk_div",
2978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2979 };
2980
2981 /* l4_per2 -> mcasp4 */
2982 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
2983         .master         = &dra7xx_l4_per2_hwmod,
2984         .slave          = &dra7xx_mcasp4_hwmod,
2985         .clk            = "l4_root_clk_div",
2986         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2987 };
2988
2989 /* l4_per2 -> mcasp5 */
2990 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
2991         .master         = &dra7xx_l4_per2_hwmod,
2992         .slave          = &dra7xx_mcasp5_hwmod,
2993         .clk            = "l4_root_clk_div",
2994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2995 };
2996
2997 /* l4_per2 -> mcasp6 */
2998 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
2999         .master         = &dra7xx_l4_per2_hwmod,
3000         .slave          = &dra7xx_mcasp6_hwmod,
3001         .clk            = "l4_root_clk_div",
3002         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3003 };
3004
3005 /* l4_per2 -> mcasp7 */
3006 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3007         .master         = &dra7xx_l4_per2_hwmod,
3008         .slave          = &dra7xx_mcasp7_hwmod,
3009         .clk            = "l4_root_clk_div",
3010         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3011 };
3012
3013 /* l4_per2 -> mcasp8 */
3014 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3015         .master         = &dra7xx_l4_per2_hwmod,
3016         .slave          = &dra7xx_mcasp8_hwmod,
3017         .clk            = "l4_root_clk_div",
3018         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3019 };
3020
3021 /* l4_per1 -> elm */
3022 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3023         .master         = &dra7xx_l4_per1_hwmod,
3024         .slave          = &dra7xx_elm_hwmod,
3025         .clk            = "l3_iclk_div",
3026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3027 };
3028
3029 /* l4_wkup -> gpio1 */
3030 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3031         .master         = &dra7xx_l4_wkup_hwmod,
3032         .slave          = &dra7xx_gpio1_hwmod,
3033         .clk            = "wkupaon_iclk_mux",
3034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3035 };
3036
3037 /* l4_per1 -> gpio2 */
3038 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3039         .master         = &dra7xx_l4_per1_hwmod,
3040         .slave          = &dra7xx_gpio2_hwmod,
3041         .clk            = "l3_iclk_div",
3042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3043 };
3044
3045 /* l4_per1 -> gpio3 */
3046 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3047         .master         = &dra7xx_l4_per1_hwmod,
3048         .slave          = &dra7xx_gpio3_hwmod,
3049         .clk            = "l3_iclk_div",
3050         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3051 };
3052
3053 /* l4_per1 -> gpio4 */
3054 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3055         .master         = &dra7xx_l4_per1_hwmod,
3056         .slave          = &dra7xx_gpio4_hwmod,
3057         .clk            = "l3_iclk_div",
3058         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3059 };
3060
3061 /* l4_per1 -> gpio5 */
3062 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3063         .master         = &dra7xx_l4_per1_hwmod,
3064         .slave          = &dra7xx_gpio5_hwmod,
3065         .clk            = "l3_iclk_div",
3066         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3067 };
3068
3069 /* l4_per1 -> gpio6 */
3070 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3071         .master         = &dra7xx_l4_per1_hwmod,
3072         .slave          = &dra7xx_gpio6_hwmod,
3073         .clk            = "l3_iclk_div",
3074         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3075 };
3076
3077 /* l4_per1 -> gpio7 */
3078 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3079         .master         = &dra7xx_l4_per1_hwmod,
3080         .slave          = &dra7xx_gpio7_hwmod,
3081         .clk            = "l3_iclk_div",
3082         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3083 };
3084
3085 /* l4_per1 -> gpio8 */
3086 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3087         .master         = &dra7xx_l4_per1_hwmod,
3088         .slave          = &dra7xx_gpio8_hwmod,
3089         .clk            = "l3_iclk_div",
3090         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3091 };
3092
3093 /* l3_main_1 -> gpmc */
3094 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3095         .master         = &dra7xx_l3_main_1_hwmod,
3096         .slave          = &dra7xx_gpmc_hwmod,
3097         .clk            = "l3_iclk_div",
3098         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3099 };
3100
3101 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3102         {
3103                 .pa_start       = 0x480b2000,
3104                 .pa_end         = 0x480b201f,
3105                 .flags          = ADDR_TYPE_RT
3106         },
3107         { }
3108 };
3109
3110 /* l4_per1 -> hdq1w */
3111 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3112         .master         = &dra7xx_l4_per1_hwmod,
3113         .slave          = &dra7xx_hdq1w_hwmod,
3114         .clk            = "l3_iclk_div",
3115         .addr           = dra7xx_hdq1w_addrs,
3116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3117 };
3118
3119 /* l4_per1 -> i2c1 */
3120 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3121         .master         = &dra7xx_l4_per1_hwmod,
3122         .slave          = &dra7xx_i2c1_hwmod,
3123         .clk            = "l3_iclk_div",
3124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3125 };
3126
3127 /* l4_per1 -> i2c2 */
3128 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3129         .master         = &dra7xx_l4_per1_hwmod,
3130         .slave          = &dra7xx_i2c2_hwmod,
3131         .clk            = "l3_iclk_div",
3132         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3133 };
3134
3135 /* l4_per1 -> i2c3 */
3136 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3137         .master         = &dra7xx_l4_per1_hwmod,
3138         .slave          = &dra7xx_i2c3_hwmod,
3139         .clk            = "l3_iclk_div",
3140         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3141 };
3142
3143 /* l4_per1 -> i2c4 */
3144 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3145         .master         = &dra7xx_l4_per1_hwmod,
3146         .slave          = &dra7xx_i2c4_hwmod,
3147         .clk            = "l3_iclk_div",
3148         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3149 };
3150
3151 /* l4_per1 -> i2c5 */
3152 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3153         .master         = &dra7xx_l4_per1_hwmod,
3154         .slave          = &dra7xx_i2c5_hwmod,
3155         .clk            = "l3_iclk_div",
3156         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3157 };
3158
3159 /* l4_cfg -> mailbox1 */
3160 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3161         .master         = &dra7xx_l4_cfg_hwmod,
3162         .slave          = &dra7xx_mailbox1_hwmod,
3163         .clk            = "l3_iclk_div",
3164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3165 };
3166
3167 /* l4_per3 -> mailbox2 */
3168 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3169         .master         = &dra7xx_l4_per3_hwmod,
3170         .slave          = &dra7xx_mailbox2_hwmod,
3171         .clk            = "l3_iclk_div",
3172         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3173 };
3174
3175 /* l4_per3 -> mailbox3 */
3176 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3177         .master         = &dra7xx_l4_per3_hwmod,
3178         .slave          = &dra7xx_mailbox3_hwmod,
3179         .clk            = "l3_iclk_div",
3180         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3181 };
3182
3183 /* l4_per3 -> mailbox4 */
3184 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3185         .master         = &dra7xx_l4_per3_hwmod,
3186         .slave          = &dra7xx_mailbox4_hwmod,
3187         .clk            = "l3_iclk_div",
3188         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3189 };
3190
3191 /* l4_per3 -> mailbox5 */
3192 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3193         .master         = &dra7xx_l4_per3_hwmod,
3194         .slave          = &dra7xx_mailbox5_hwmod,
3195         .clk            = "l3_iclk_div",
3196         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3197 };
3198
3199 /* l4_per3 -> mailbox6 */
3200 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3201         .master         = &dra7xx_l4_per3_hwmod,
3202         .slave          = &dra7xx_mailbox6_hwmod,
3203         .clk            = "l3_iclk_div",
3204         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3205 };
3206
3207 /* l4_per3 -> mailbox7 */
3208 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3209         .master         = &dra7xx_l4_per3_hwmod,
3210         .slave          = &dra7xx_mailbox7_hwmod,
3211         .clk            = "l3_iclk_div",
3212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3213 };
3214
3215 /* l4_per3 -> mailbox8 */
3216 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3217         .master         = &dra7xx_l4_per3_hwmod,
3218         .slave          = &dra7xx_mailbox8_hwmod,
3219         .clk            = "l3_iclk_div",
3220         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3221 };
3222
3223 /* l4_per3 -> mailbox9 */
3224 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3225         .master         = &dra7xx_l4_per3_hwmod,
3226         .slave          = &dra7xx_mailbox9_hwmod,
3227         .clk            = "l3_iclk_div",
3228         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3229 };
3230
3231 /* l4_per3 -> mailbox10 */
3232 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3233         .master         = &dra7xx_l4_per3_hwmod,
3234         .slave          = &dra7xx_mailbox10_hwmod,
3235         .clk            = "l3_iclk_div",
3236         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3237 };
3238
3239 /* l4_per3 -> mailbox11 */
3240 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3241         .master         = &dra7xx_l4_per3_hwmod,
3242         .slave          = &dra7xx_mailbox11_hwmod,
3243         .clk            = "l3_iclk_div",
3244         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3245 };
3246
3247 /* l4_per3 -> mailbox12 */
3248 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3249         .master         = &dra7xx_l4_per3_hwmod,
3250         .slave          = &dra7xx_mailbox12_hwmod,
3251         .clk            = "l3_iclk_div",
3252         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3253 };
3254
3255 /* l4_per3 -> mailbox13 */
3256 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3257         .master         = &dra7xx_l4_per3_hwmod,
3258         .slave          = &dra7xx_mailbox13_hwmod,
3259         .clk            = "l3_iclk_div",
3260         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3261 };
3262
3263 /* l4_per1 -> mcspi1 */
3264 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3265         .master         = &dra7xx_l4_per1_hwmod,
3266         .slave          = &dra7xx_mcspi1_hwmod,
3267         .clk            = "l3_iclk_div",
3268         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3269 };
3270
3271 /* l4_per1 -> mcspi2 */
3272 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3273         .master         = &dra7xx_l4_per1_hwmod,
3274         .slave          = &dra7xx_mcspi2_hwmod,
3275         .clk            = "l3_iclk_div",
3276         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3277 };
3278
3279 /* l4_per1 -> mcspi3 */
3280 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3281         .master         = &dra7xx_l4_per1_hwmod,
3282         .slave          = &dra7xx_mcspi3_hwmod,
3283         .clk            = "l3_iclk_div",
3284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3285 };
3286
3287 /* l4_per1 -> mcspi4 */
3288 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3289         .master         = &dra7xx_l4_per1_hwmod,
3290         .slave          = &dra7xx_mcspi4_hwmod,
3291         .clk            = "l3_iclk_div",
3292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3293 };
3294
3295 /* l4_per1 -> mmc1 */
3296 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3297         .master         = &dra7xx_l4_per1_hwmod,
3298         .slave          = &dra7xx_mmc1_hwmod,
3299         .clk            = "l3_iclk_div",
3300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3301 };
3302
3303 /* l4_per1 -> mmc2 */
3304 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3305         .master         = &dra7xx_l4_per1_hwmod,
3306         .slave          = &dra7xx_mmc2_hwmod,
3307         .clk            = "l3_iclk_div",
3308         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3309 };
3310
3311 /* l4_per1 -> mmc3 */
3312 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3313         .master         = &dra7xx_l4_per1_hwmod,
3314         .slave          = &dra7xx_mmc3_hwmod,
3315         .clk            = "l3_iclk_div",
3316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3317 };
3318
3319 /* l4_per1 -> mmc4 */
3320 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3321         .master         = &dra7xx_l4_per1_hwmod,
3322         .slave          = &dra7xx_mmc4_hwmod,
3323         .clk            = "l3_iclk_div",
3324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3325 };
3326
3327 /* l4_cfg -> mpu */
3328 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3329         .master         = &dra7xx_l4_cfg_hwmod,
3330         .slave          = &dra7xx_mpu_hwmod,
3331         .clk            = "l3_iclk_div",
3332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3333 };
3334
3335 /* l4_cfg -> ocp2scp1 */
3336 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3337         .master         = &dra7xx_l4_cfg_hwmod,
3338         .slave          = &dra7xx_ocp2scp1_hwmod,
3339         .clk            = "l4_root_clk_div",
3340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3341 };
3342
3343 /* l4_cfg -> ocp2scp3 */
3344 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3345         .master         = &dra7xx_l4_cfg_hwmod,
3346         .slave          = &dra7xx_ocp2scp3_hwmod,
3347         .clk            = "l4_root_clk_div",
3348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3349 };
3350
3351 /* l3_main_1 -> pciess1 */
3352 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3353         .master         = &dra7xx_l3_main_1_hwmod,
3354         .slave          = &dra7xx_pciess1_hwmod,
3355         .clk            = "l3_iclk_div",
3356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3357 };
3358
3359 /* l4_cfg -> pciess1 */
3360 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3361         .master         = &dra7xx_l4_cfg_hwmod,
3362         .slave          = &dra7xx_pciess1_hwmod,
3363         .clk            = "l4_root_clk_div",
3364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3365 };
3366
3367 /* l3_main_1 -> pciess2 */
3368 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3369         .master         = &dra7xx_l3_main_1_hwmod,
3370         .slave          = &dra7xx_pciess2_hwmod,
3371         .clk            = "l3_iclk_div",
3372         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3373 };
3374
3375 /* l4_cfg -> pciess2 */
3376 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3377         .master         = &dra7xx_l4_cfg_hwmod,
3378         .slave          = &dra7xx_pciess2_hwmod,
3379         .clk            = "l4_root_clk_div",
3380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3381 };
3382
3383 /* l3_main_1 -> qspi */
3384 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3385         .master         = &dra7xx_l3_main_1_hwmod,
3386         .slave          = &dra7xx_qspi_hwmod,
3387         .clk            = "l3_iclk_div",
3388         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3389 };
3390
3391 /* l4_per3 -> rtcss */
3392 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3393         .master         = &dra7xx_l4_per3_hwmod,
3394         .slave          = &dra7xx_rtcss_hwmod,
3395         .clk            = "l4_root_clk_div",
3396         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3397 };
3398
3399 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3400         {
3401                 .name           = "sysc",
3402                 .pa_start       = 0x4a141100,
3403                 .pa_end         = 0x4a141107,
3404                 .flags          = ADDR_TYPE_RT
3405         },
3406         { }
3407 };
3408
3409 /* l4_cfg -> sata */
3410 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3411         .master         = &dra7xx_l4_cfg_hwmod,
3412         .slave          = &dra7xx_sata_hwmod,
3413         .clk            = "l3_iclk_div",
3414         .addr           = dra7xx_sata_addrs,
3415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3416 };
3417
3418 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3419         {
3420                 .pa_start       = 0x4a0dd000,
3421                 .pa_end         = 0x4a0dd07f,
3422                 .flags          = ADDR_TYPE_RT
3423         },
3424         { }
3425 };
3426
3427 /* l4_cfg -> smartreflex_core */
3428 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3429         .master         = &dra7xx_l4_cfg_hwmod,
3430         .slave          = &dra7xx_smartreflex_core_hwmod,
3431         .clk            = "l4_root_clk_div",
3432         .addr           = dra7xx_smartreflex_core_addrs,
3433         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3434 };
3435
3436 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3437         {
3438                 .pa_start       = 0x4a0d9000,
3439                 .pa_end         = 0x4a0d907f,
3440                 .flags          = ADDR_TYPE_RT
3441         },
3442         { }
3443 };
3444
3445 /* l4_cfg -> smartreflex_mpu */
3446 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3447         .master         = &dra7xx_l4_cfg_hwmod,
3448         .slave          = &dra7xx_smartreflex_mpu_hwmod,
3449         .clk            = "l4_root_clk_div",
3450         .addr           = dra7xx_smartreflex_mpu_addrs,
3451         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3452 };
3453
3454 /* l4_cfg -> spinlock */
3455 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3456         .master         = &dra7xx_l4_cfg_hwmod,
3457         .slave          = &dra7xx_spinlock_hwmod,
3458         .clk            = "l3_iclk_div",
3459         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3460 };
3461
3462 /* l4_wkup -> timer1 */
3463 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3464         .master         = &dra7xx_l4_wkup_hwmod,
3465         .slave          = &dra7xx_timer1_hwmod,
3466         .clk            = "wkupaon_iclk_mux",
3467         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3468 };
3469
3470 /* l4_per1 -> timer2 */
3471 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3472         .master         = &dra7xx_l4_per1_hwmod,
3473         .slave          = &dra7xx_timer2_hwmod,
3474         .clk            = "l3_iclk_div",
3475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3476 };
3477
3478 /* l4_per1 -> timer3 */
3479 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3480         .master         = &dra7xx_l4_per1_hwmod,
3481         .slave          = &dra7xx_timer3_hwmod,
3482         .clk            = "l3_iclk_div",
3483         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3484 };
3485
3486 /* l4_per1 -> timer4 */
3487 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3488         .master         = &dra7xx_l4_per1_hwmod,
3489         .slave          = &dra7xx_timer4_hwmod,
3490         .clk            = "l3_iclk_div",
3491         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3492 };
3493
3494 /* l4_per3 -> timer5 */
3495 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3496         .master         = &dra7xx_l4_per3_hwmod,
3497         .slave          = &dra7xx_timer5_hwmod,
3498         .clk            = "l3_iclk_div",
3499         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3500 };
3501
3502 /* l4_per3 -> timer6 */
3503 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3504         .master         = &dra7xx_l4_per3_hwmod,
3505         .slave          = &dra7xx_timer6_hwmod,
3506         .clk            = "l3_iclk_div",
3507         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3508 };
3509
3510 /* l4_per3 -> timer7 */
3511 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3512         .master         = &dra7xx_l4_per3_hwmod,
3513         .slave          = &dra7xx_timer7_hwmod,
3514         .clk            = "l3_iclk_div",
3515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3516 };
3517
3518 /* l4_per3 -> timer8 */
3519 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3520         .master         = &dra7xx_l4_per3_hwmod,
3521         .slave          = &dra7xx_timer8_hwmod,
3522         .clk            = "l3_iclk_div",
3523         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3524 };
3525
3526 /* l4_per1 -> timer9 */
3527 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3528         .master         = &dra7xx_l4_per1_hwmod,
3529         .slave          = &dra7xx_timer9_hwmod,
3530         .clk            = "l3_iclk_div",
3531         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3532 };
3533
3534 /* l4_per1 -> timer10 */
3535 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3536         .master         = &dra7xx_l4_per1_hwmod,
3537         .slave          = &dra7xx_timer10_hwmod,
3538         .clk            = "l3_iclk_div",
3539         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3540 };
3541
3542 /* l4_per1 -> timer11 */
3543 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3544         .master         = &dra7xx_l4_per1_hwmod,
3545         .slave          = &dra7xx_timer11_hwmod,
3546         .clk            = "l3_iclk_div",
3547         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3548 };
3549
3550 /* l4_wkup -> timer12 */
3551 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3552         .master         = &dra7xx_l4_wkup_hwmod,
3553         .slave          = &dra7xx_timer12_hwmod,
3554         .clk            = "wkupaon_iclk_mux",
3555         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3556 };
3557
3558 /* l4_per3 -> timer13 */
3559 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3560         .master         = &dra7xx_l4_per3_hwmod,
3561         .slave          = &dra7xx_timer13_hwmod,
3562         .clk            = "l3_iclk_div",
3563         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3564 };
3565
3566 /* l4_per3 -> timer14 */
3567 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3568         .master         = &dra7xx_l4_per3_hwmod,
3569         .slave          = &dra7xx_timer14_hwmod,
3570         .clk            = "l3_iclk_div",
3571         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3572 };
3573
3574 /* l4_per3 -> timer15 */
3575 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3576         .master         = &dra7xx_l4_per3_hwmod,
3577         .slave          = &dra7xx_timer15_hwmod,
3578         .clk            = "l3_iclk_div",
3579         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3580 };
3581
3582 /* l4_per3 -> timer16 */
3583 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3584         .master         = &dra7xx_l4_per3_hwmod,
3585         .slave          = &dra7xx_timer16_hwmod,
3586         .clk            = "l3_iclk_div",
3587         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3588 };
3589
3590 /* l4_per1 -> uart1 */
3591 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3592         .master         = &dra7xx_l4_per1_hwmod,
3593         .slave          = &dra7xx_uart1_hwmod,
3594         .clk            = "l3_iclk_div",
3595         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3596 };
3597
3598 /* l4_per1 -> uart2 */
3599 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3600         .master         = &dra7xx_l4_per1_hwmod,
3601         .slave          = &dra7xx_uart2_hwmod,
3602         .clk            = "l3_iclk_div",
3603         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3604 };
3605
3606 /* l4_per1 -> uart3 */
3607 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3608         .master         = &dra7xx_l4_per1_hwmod,
3609         .slave          = &dra7xx_uart3_hwmod,
3610         .clk            = "l3_iclk_div",
3611         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3612 };
3613
3614 /* l4_per1 -> uart4 */
3615 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3616         .master         = &dra7xx_l4_per1_hwmod,
3617         .slave          = &dra7xx_uart4_hwmod,
3618         .clk            = "l3_iclk_div",
3619         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3620 };
3621
3622 /* l4_per1 -> uart5 */
3623 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3624         .master         = &dra7xx_l4_per1_hwmod,
3625         .slave          = &dra7xx_uart5_hwmod,
3626         .clk            = "l3_iclk_div",
3627         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3628 };
3629
3630 /* l4_per1 -> uart6 */
3631 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3632         .master         = &dra7xx_l4_per1_hwmod,
3633         .slave          = &dra7xx_uart6_hwmod,
3634         .clk            = "l3_iclk_div",
3635         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3636 };
3637
3638 /* l4_per2 -> uart7 */
3639 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3640         .master         = &dra7xx_l4_per2_hwmod,
3641         .slave          = &dra7xx_uart7_hwmod,
3642         .clk            = "l3_iclk_div",
3643         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3644 };
3645
3646 /* l4_per2 -> uart8 */
3647 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3648         .master         = &dra7xx_l4_per2_hwmod,
3649         .slave          = &dra7xx_uart8_hwmod,
3650         .clk            = "l3_iclk_div",
3651         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3652 };
3653
3654 /* l4_per2 -> uart9 */
3655 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3656         .master         = &dra7xx_l4_per2_hwmod,
3657         .slave          = &dra7xx_uart9_hwmod,
3658         .clk            = "l3_iclk_div",
3659         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3660 };
3661
3662 /* l4_wkup -> uart10 */
3663 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3664         .master         = &dra7xx_l4_wkup_hwmod,
3665         .slave          = &dra7xx_uart10_hwmod,
3666         .clk            = "wkupaon_iclk_mux",
3667         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3668 };
3669
3670 /* l4_per3 -> usb_otg_ss1 */
3671 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3672         .master         = &dra7xx_l4_per3_hwmod,
3673         .slave          = &dra7xx_usb_otg_ss1_hwmod,
3674         .clk            = "dpll_core_h13x2_ck",
3675         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3676 };
3677
3678 /* l4_per3 -> usb_otg_ss2 */
3679 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3680         .master         = &dra7xx_l4_per3_hwmod,
3681         .slave          = &dra7xx_usb_otg_ss2_hwmod,
3682         .clk            = "dpll_core_h13x2_ck",
3683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3684 };
3685
3686 /* l4_per3 -> usb_otg_ss3 */
3687 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3688         .master         = &dra7xx_l4_per3_hwmod,
3689         .slave          = &dra7xx_usb_otg_ss3_hwmod,
3690         .clk            = "dpll_core_h13x2_ck",
3691         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3692 };
3693
3694 /* l4_per3 -> usb_otg_ss4 */
3695 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3696         .master         = &dra7xx_l4_per3_hwmod,
3697         .slave          = &dra7xx_usb_otg_ss4_hwmod,
3698         .clk            = "dpll_core_h13x2_ck",
3699         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3700 };
3701
3702 /* l3_main_1 -> vcp1 */
3703 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3704         .master         = &dra7xx_l3_main_1_hwmod,
3705         .slave          = &dra7xx_vcp1_hwmod,
3706         .clk            = "l3_iclk_div",
3707         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3708 };
3709
3710 /* l4_per2 -> vcp1 */
3711 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3712         .master         = &dra7xx_l4_per2_hwmod,
3713         .slave          = &dra7xx_vcp1_hwmod,
3714         .clk            = "l3_iclk_div",
3715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3716 };
3717
3718 /* l3_main_1 -> vcp2 */
3719 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3720         .master         = &dra7xx_l3_main_1_hwmod,
3721         .slave          = &dra7xx_vcp2_hwmod,
3722         .clk            = "l3_iclk_div",
3723         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3724 };
3725
3726 /* l4_per2 -> vcp2 */
3727 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3728         .master         = &dra7xx_l4_per2_hwmod,
3729         .slave          = &dra7xx_vcp2_hwmod,
3730         .clk            = "l3_iclk_div",
3731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3732 };
3733
3734 /* l4_wkup -> wd_timer2 */
3735 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3736         .master         = &dra7xx_l4_wkup_hwmod,
3737         .slave          = &dra7xx_wd_timer2_hwmod,
3738         .clk            = "wkupaon_iclk_mux",
3739         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3740 };
3741
3742 /* l4_per2 -> epwmss0 */
3743 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3744         .master         = &dra7xx_l4_per2_hwmod,
3745         .slave          = &dra7xx_epwmss0_hwmod,
3746         .clk            = "l4_root_clk_div",
3747         .user           = OCP_USER_MPU,
3748 };
3749
3750 /* l4_per2 -> epwmss1 */
3751 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3752         .master         = &dra7xx_l4_per2_hwmod,
3753         .slave          = &dra7xx_epwmss1_hwmod,
3754         .clk            = "l4_root_clk_div",
3755         .user           = OCP_USER_MPU,
3756 };
3757
3758 /* l4_per2 -> epwmss2 */
3759 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3760         .master         = &dra7xx_l4_per2_hwmod,
3761         .slave          = &dra7xx_epwmss2_hwmod,
3762         .clk            = "l4_root_clk_div",
3763         .user           = OCP_USER_MPU,
3764 };
3765
3766 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3767         &dra7xx_l3_main_1__dmm,
3768         &dra7xx_l3_main_2__l3_instr,
3769         &dra7xx_l4_cfg__l3_main_1,
3770         &dra7xx_mpu__l3_main_1,
3771         &dra7xx_l3_main_1__l3_main_2,
3772         &dra7xx_l4_cfg__l3_main_2,
3773         &dra7xx_l3_main_1__l4_cfg,
3774         &dra7xx_l3_main_1__l4_per1,
3775         &dra7xx_l3_main_1__l4_per2,
3776         &dra7xx_l3_main_1__l4_per3,
3777         &dra7xx_l3_main_1__l4_wkup,
3778         &dra7xx_l4_per2__atl,
3779         &dra7xx_l3_main_1__bb2d,
3780         &dra7xx_l4_wkup__counter_32k,
3781         &dra7xx_l4_wkup__ctrl_module_wkup,
3782         &dra7xx_l4_wkup__dcan1,
3783         &dra7xx_l4_per2__dcan2,
3784         &dra7xx_l4_per2__cpgmac0,
3785         &dra7xx_l4_per2__mcasp1,
3786         &dra7xx_l3_main_1__mcasp1,
3787         &dra7xx_l4_per2__mcasp2,
3788         &dra7xx_l3_main_1__mcasp2,
3789         &dra7xx_l4_per2__mcasp3,
3790         &dra7xx_l3_main_1__mcasp3,
3791         &dra7xx_l4_per2__mcasp4,
3792         &dra7xx_l4_per2__mcasp5,
3793         &dra7xx_l4_per2__mcasp6,
3794         &dra7xx_l4_per2__mcasp7,
3795         &dra7xx_l4_per2__mcasp8,
3796         &dra7xx_gmac__mdio,
3797         &dra7xx_l4_cfg__dma_system,
3798         &dra7xx_l3_main_1__tpcc,
3799         &dra7xx_l3_main_1__tptc0,
3800         &dra7xx_l3_main_1__tptc1,
3801         &dra7xx_l3_main_1__dss,
3802         &dra7xx_l3_main_1__dispc,
3803         &dra7xx_l3_main_1__hdmi,
3804         &dra7xx_l4_per1__elm,
3805         &dra7xx_l4_wkup__gpio1,
3806         &dra7xx_l4_per1__gpio2,
3807         &dra7xx_l4_per1__gpio3,
3808         &dra7xx_l4_per1__gpio4,
3809         &dra7xx_l4_per1__gpio5,
3810         &dra7xx_l4_per1__gpio6,
3811         &dra7xx_l4_per1__gpio7,
3812         &dra7xx_l4_per1__gpio8,
3813         &dra7xx_l3_main_1__gpmc,
3814         &dra7xx_l4_per1__hdq1w,
3815         &dra7xx_l4_per1__i2c1,
3816         &dra7xx_l4_per1__i2c2,
3817         &dra7xx_l4_per1__i2c3,
3818         &dra7xx_l4_per1__i2c4,
3819         &dra7xx_l4_per1__i2c5,
3820         &dra7xx_l4_cfg__mailbox1,
3821         &dra7xx_l4_per3__mailbox2,
3822         &dra7xx_l4_per3__mailbox3,
3823         &dra7xx_l4_per3__mailbox4,
3824         &dra7xx_l4_per3__mailbox5,
3825         &dra7xx_l4_per3__mailbox6,
3826         &dra7xx_l4_per3__mailbox7,
3827         &dra7xx_l4_per3__mailbox8,
3828         &dra7xx_l4_per3__mailbox9,
3829         &dra7xx_l4_per3__mailbox10,
3830         &dra7xx_l4_per3__mailbox11,
3831         &dra7xx_l4_per3__mailbox12,
3832         &dra7xx_l4_per3__mailbox13,
3833         &dra7xx_l4_per1__mcspi1,
3834         &dra7xx_l4_per1__mcspi2,
3835         &dra7xx_l4_per1__mcspi3,
3836         &dra7xx_l4_per1__mcspi4,
3837         &dra7xx_l4_per1__mmc1,
3838         &dra7xx_l4_per1__mmc2,
3839         &dra7xx_l4_per1__mmc3,
3840         &dra7xx_l4_per1__mmc4,
3841         &dra7xx_l4_cfg__mpu,
3842         &dra7xx_l4_cfg__ocp2scp1,
3843         &dra7xx_l4_cfg__ocp2scp3,
3844         &dra7xx_l3_main_1__pciess1,
3845         &dra7xx_l4_cfg__pciess1,
3846         &dra7xx_l3_main_1__pciess2,
3847         &dra7xx_l4_cfg__pciess2,
3848         &dra7xx_l3_main_1__qspi,
3849         &dra7xx_l4_per3__rtcss,
3850         &dra7xx_l4_cfg__sata,
3851         &dra7xx_l4_cfg__smartreflex_core,
3852         &dra7xx_l4_cfg__smartreflex_mpu,
3853         &dra7xx_l4_cfg__spinlock,
3854         &dra7xx_l4_wkup__timer1,
3855         &dra7xx_l4_per1__timer2,
3856         &dra7xx_l4_per1__timer3,
3857         &dra7xx_l4_per1__timer4,
3858         &dra7xx_l4_per3__timer5,
3859         &dra7xx_l4_per3__timer6,
3860         &dra7xx_l4_per3__timer7,
3861         &dra7xx_l4_per3__timer8,
3862         &dra7xx_l4_per1__timer9,
3863         &dra7xx_l4_per1__timer10,
3864         &dra7xx_l4_per1__timer11,
3865         &dra7xx_l4_per3__timer13,
3866         &dra7xx_l4_per3__timer14,
3867         &dra7xx_l4_per3__timer15,
3868         &dra7xx_l4_per3__timer16,
3869         &dra7xx_l4_per1__uart1,
3870         &dra7xx_l4_per1__uart2,
3871         &dra7xx_l4_per1__uart3,
3872         &dra7xx_l4_per1__uart4,
3873         &dra7xx_l4_per1__uart5,
3874         &dra7xx_l4_per1__uart6,
3875         &dra7xx_l4_per2__uart7,
3876         &dra7xx_l4_per2__uart8,
3877         &dra7xx_l4_per2__uart9,
3878         &dra7xx_l4_wkup__uart10,
3879         &dra7xx_l4_per3__usb_otg_ss1,
3880         &dra7xx_l4_per3__usb_otg_ss2,
3881         &dra7xx_l4_per3__usb_otg_ss3,
3882         &dra7xx_l3_main_1__vcp1,
3883         &dra7xx_l4_per2__vcp1,
3884         &dra7xx_l3_main_1__vcp2,
3885         &dra7xx_l4_per2__vcp2,
3886         &dra7xx_l4_wkup__wd_timer2,
3887         &dra7xx_l4_per2__epwmss0,
3888         &dra7xx_l4_per2__epwmss1,
3889         &dra7xx_l4_per2__epwmss2,
3890         NULL,
3891 };
3892
3893 /* GP-only hwmod links */
3894 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
3895         &dra7xx_l4_wkup__timer12,
3896         NULL,
3897 };
3898
3899 /* SoC variant specific hwmod links */
3900 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3901         &dra7xx_l4_per3__usb_otg_ss4,
3902         NULL,
3903 };
3904
3905 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3906         NULL,
3907 };
3908
3909 int __init dra7xx_hwmod_init(void)
3910 {
3911         int ret;
3912
3913         omap_hwmod_init();
3914         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3915
3916         if (!ret && soc_is_dra74x())
3917                 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3918         else if (!ret && soc_is_dra72x())
3919                 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3920
3921         if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
3922                 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
3923
3924         return ret;
3925 }