2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/platform_device.h>
43 #include <linux/platform_data/dmtimer-omap.h>
44 #include <linux/sched_clock.h>
46 #include <asm/mach/time.h>
47 #include <asm/smp_twd.h>
49 #include "omap_hwmod.h"
50 #include "omap_device.h"
51 #include <plat/counter-32k.h>
52 #include <plat/dmtimer.h>
58 #include "powerdomain.h"
59 #include "omap-secure.h"
61 #define REALTIME_COUNTER_BASE 0x48243200
62 #define INCREMENTER_NUMERATOR_OFFSET 0x10
63 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
64 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
68 static struct omap_dm_timer clkev;
69 static struct clock_event_device clockevent_gpt;
71 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
72 static unsigned long arch_timer_freq;
74 void set_cntfreq(void)
76 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
80 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
82 struct clock_event_device *evt = &clockevent_gpt;
84 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
86 evt->event_handler(evt);
90 static struct irqaction omap2_gp_timer_irq = {
92 .flags = IRQF_TIMER | IRQF_IRQPOLL,
93 .handler = omap2_gp_timer_interrupt,
96 static int omap2_gp_timer_set_next_event(unsigned long cycles,
97 struct clock_event_device *evt)
99 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
100 0xffffffff - cycles, OMAP_TIMER_POSTED);
105 static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
107 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
111 static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
115 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
117 period = clkev.rate / HZ;
119 /* Looks like we need to first set the load value separately */
120 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
122 __omap_dm_timer_load_start(&clkev,
123 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
124 0xffffffff - period, OMAP_TIMER_POSTED);
128 static struct clock_event_device clockevent_gpt = {
129 .features = CLOCK_EVT_FEAT_PERIODIC |
130 CLOCK_EVT_FEAT_ONESHOT,
132 .set_next_event = omap2_gp_timer_set_next_event,
133 .set_state_shutdown = omap2_gp_timer_shutdown,
134 .set_state_periodic = omap2_gp_timer_set_periodic,
135 .set_state_oneshot = omap2_gp_timer_shutdown,
136 .tick_resume = omap2_gp_timer_shutdown,
139 static const struct of_device_id omap_timer_match[] __initconst = {
140 { .compatible = "ti,omap2420-timer", },
141 { .compatible = "ti,omap3430-timer", },
142 { .compatible = "ti,omap4430-timer", },
143 { .compatible = "ti,omap5430-timer", },
144 { .compatible = "ti,dm814-timer", },
145 { .compatible = "ti,dm816-timer", },
146 { .compatible = "ti,am335x-timer", },
147 { .compatible = "ti,am335x-timer-1ms", },
152 * omap_get_timer_dt - get a timer using device-tree
153 * @match - device-tree match structure for matching a device type
154 * @property - optional timer property to match
156 * Helper function to get a timer during early boot using device-tree for use
157 * as kernel system timer. Optionally, the property argument can be used to
158 * select a timer with a specific property. Once a timer is found then mark
159 * the timer node in device-tree as disabled, to prevent the kernel from
160 * registering this timer as a platform device and so no one else can use it.
162 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
163 const char *property)
165 struct device_node *np;
167 for_each_matching_node(np, match) {
168 if (!of_device_is_available(np))
171 if (property && !of_get_property(np, property, NULL))
174 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
175 of_get_property(np, "ti,timer-dsp", NULL) ||
176 of_get_property(np, "ti,timer-pwm", NULL) ||
177 of_get_property(np, "ti,timer-secure", NULL)))
180 if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
181 struct property *prop;
183 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
186 prop->name = "status";
187 prop->value = "disabled";
188 prop->length = strlen(prop->value);
189 of_add_property(np, prop);
198 * omap_dmtimer_init - initialisation function when device tree is used
200 * For secure OMAP3 devices, timers with device type "timer-secure" cannot
201 * be used by the kernel as they are reserved. Therefore, to prevent the
202 * kernel registering these devices remove them dynamically from the device
205 static void __init omap_dmtimer_init(void)
207 struct device_node *np;
209 if (!cpu_is_omap34xx())
212 /* If we are a secure device, remove any secure timer nodes */
213 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
214 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
220 * omap_dm_timer_get_errata - get errata flags for a timer
222 * Get the timer errata flags that are specific to the OMAP device being used.
224 static u32 __init omap_dm_timer_get_errata(void)
226 if (cpu_is_omap24xx())
229 return OMAP_TIMER_ERRATA_I103_I767;
232 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
233 const char *fck_source,
234 const char *property,
235 const char **timer_name,
238 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
239 const char *oh_name = NULL;
240 struct device_node *np;
241 struct omap_hwmod *oh;
242 struct resource irq, mem;
246 if (of_have_populated_dt()) {
247 np = omap_get_timer_dt(omap_timer_match, property);
251 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
255 timer->irq = irq_of_parse_and_map(np, 0);
259 timer->io_base = of_iomap(np, 0);
263 if (omap_dm_timer_reserve_systimer(timer->id))
266 sprintf(name, "timer%d", timer->id);
270 oh = omap_hwmod_lookup(oh_name);
274 *timer_name = oh->name;
276 if (!of_have_populated_dt()) {
277 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
281 timer->irq = irq.start;
283 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
288 /* Static mapping, never released */
289 timer->io_base = ioremap(mem.start, mem.end - mem.start);
295 /* After the dmtimer is using hwmod these clocks won't be needed */
296 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
297 if (IS_ERR(timer->fclk))
298 return PTR_ERR(timer->fclk);
300 src = clk_get(NULL, fck_source);
304 WARN(clk_set_parent(timer->fclk, src) < 0,
305 "Cannot set timer parent clock, no PLL clock driver?");
309 omap_hwmod_setup_one(oh_name);
310 omap_hwmod_enable(oh);
311 __omap_dm_timer_init_regs(timer);
314 __omap_dm_timer_enable_posted(timer);
316 /* Check that the intended posted configuration matches the actual */
317 if (posted != timer->posted)
320 timer->rate = clk_get_rate(timer->fclk);
326 #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
327 void tick_broadcast(const struct cpumask *mask)
332 static void __init omap2_gp_clockevent_init(int gptimer_id,
333 const char *fck_source,
334 const char *property)
338 clkev.id = gptimer_id;
339 clkev.errata = omap_dm_timer_get_errata();
342 * For clock-event timers we never read the timer counter and
343 * so we are not impacted by errata i103 and i767. Therefore,
344 * we can safely ignore this errata for clock-event timers.
346 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
348 res = omap_dm_timer_init_one(&clkev, fck_source, property,
349 &clockevent_gpt.name, OMAP_TIMER_POSTED);
352 omap2_gp_timer_irq.dev_id = &clkev;
353 setup_irq(clkev.irq, &omap2_gp_timer_irq);
355 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
357 clockevent_gpt.cpumask = cpu_possible_mask;
358 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
359 clockevents_config_and_register(&clockevent_gpt, clkev.rate,
360 3, /* Timer internal resynch latency */
363 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
367 /* Clocksource code */
368 static struct omap_dm_timer clksrc;
369 static bool use_gptimer_clksrc __initdata;
374 static cycle_t clocksource_read_cycles(struct clocksource *cs)
376 return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
377 OMAP_TIMER_NONPOSTED);
380 static struct clocksource clocksource_gpt = {
382 .read = clocksource_read_cycles,
383 .mask = CLOCKSOURCE_MASK(32),
384 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
387 static u64 notrace dmtimer_read_sched_clock(void)
390 return __omap_dm_timer_read_counter(&clksrc,
391 OMAP_TIMER_NONPOSTED);
396 static const struct of_device_id omap_counter_match[] __initconst = {
397 { .compatible = "ti,omap-counter32k", },
401 /* Setup free-running counter for clocksource */
402 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
405 struct device_node *np = NULL;
406 struct omap_hwmod *oh;
407 const char *oh_name = "counter_32k";
410 * If device-tree is present, then search the DT blob
411 * to see if the 32kHz counter is supported.
413 if (of_have_populated_dt()) {
414 np = omap_get_timer_dt(omap_counter_match, NULL);
418 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
424 * First check hwmod data is available for sync32k counter
426 oh = omap_hwmod_lookup(oh_name);
427 if (!oh || oh->slaves_cnt == 0)
430 omap_hwmod_setup_one(oh_name);
432 ret = omap_hwmod_enable(oh);
434 pr_warn("%s: failed to enable counter_32k module (%d)\n",
439 if (!of_have_populated_dt()) {
442 vbase = omap_hwmod_get_mpu_rt_va(oh);
444 ret = omap_init_clocksource_32k(vbase);
446 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
454 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
455 const char *fck_source,
456 const char *property)
460 clksrc.id = gptimer_id;
461 clksrc.errata = omap_dm_timer_get_errata();
463 res = omap_dm_timer_init_one(&clksrc, fck_source, property,
464 &clocksource_gpt.name,
465 OMAP_TIMER_NONPOSTED);
468 __omap_dm_timer_load_start(&clksrc,
469 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
470 OMAP_TIMER_NONPOSTED);
471 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
473 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
474 pr_err("Could not register clocksource %s\n",
475 clocksource_gpt.name);
477 pr_info("OMAP clocksource: %s at %lu Hz\n",
478 clocksource_gpt.name, clksrc.rate);
481 static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
482 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
483 const char *clksrc_prop, bool gptimer)
487 omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
489 /* Enable the use of clocksource="gp_timer" kernel parameter */
490 if (use_gptimer_clksrc || gptimer)
491 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
494 omap2_sync32k_clocksource_init();
497 void __init omap_init_time(void)
499 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
500 2, "timer_sys_ck", NULL, false);
505 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
506 void __init omap3_secure_sync32k_timer_init(void)
508 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
509 2, "timer_sys_ck", NULL, false);
513 #endif /* CONFIG_ARCH_OMAP3 */
515 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
516 void __init omap3_gptimer_timer_init(void)
518 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
519 1, "timer_sys_ck", "ti,timer-alwon", true);
525 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
526 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
527 static void __init omap4_sync32k_timer_init(void)
529 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
530 2, "sys_clkin_ck", NULL, false);
533 void __init omap4_local_timer_init(void)
535 omap4_sync32k_timer_init();
540 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
543 * The realtime counter also called master counter, is a free-running
544 * counter, which is related to real time. It produces the count used
545 * by the CPU local timer peripherals in the MPU cluster. The timer counts
546 * at a rate of 6.144 MHz. Because the device operates on different clocks
547 * in different power modes, the master counter shifts operation between
548 * clocks, adjusting the increment per clock in hardware accordingly to
549 * maintain a constant count rate.
551 static void __init realtime_counter_init(void)
553 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
555 static struct clk *sys_clk;
558 unsigned long long num, den;
560 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
562 pr_err("%s: ioremap failed\n", __func__);
565 sys_clk = clk_get(NULL, "sys_clkin");
566 if (IS_ERR(sys_clk)) {
567 pr_err("%s: failed to get system clock handle\n", __func__);
572 rate = clk_get_rate(sys_clk);
574 if (soc_is_dra7xx()) {
576 * Errata i856 says the 32.768KHz crystal does not start at
577 * power on, so the CPU falls back to an emulated 32KHz clock
578 * based on sysclk / 610 instead. This causes the master counter
579 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
580 * (OR sysclk * 75 / 244)
582 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
583 * Of course any board built without a populated 32.768KHz
584 * crystal would also need this fix even if the CPU is fixed
587 * Either case can be detected by using the two speedselect bits
588 * If they are not 0, then the 32.768KHz clock driving the
589 * coarse counter that corrects the fine counter every time it
590 * ticks is actually rate/610 rather than 32.768KHz and we
591 * should compensate to avoid the 570ppm (at 20MHz, much worse
592 * at other rates) too fast system time.
594 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
595 if (reg & DRA7_SPEEDSELECT_MASK) {
602 /* Numerator/denumerator values refer TRM Realtime Counter section */
630 /* Program it for 38.4 MHz */
637 /* Program numerator and denumerator registers */
638 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
639 NUMERATOR_DENUMERATOR_MASK;
641 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
643 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
644 NUMERATOR_DENUMERATOR_MASK;
646 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
648 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
655 void __init omap5_realtime_timer_init(void)
657 omap4_sync32k_timer_init();
658 realtime_counter_init();
662 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
665 * omap_timer_init - build and register timer device with an
666 * associated timer hwmod
667 * @oh: timer hwmod pointer to be used to build timer device
668 * @user: parameter that can be passed from calling hwmod API
670 * Called by omap_hwmod_for_each_by_class to register each of the timer
671 * devices present in the system. The number of timer devices is known
672 * by parsing through the hwmod database for a given class name. At the
673 * end of function call memory is allocated for timer device and it is
674 * registered to the framework ready to be proved by the driver.
676 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
680 char *name = "omap_timer";
681 struct dmtimer_platform_data *pdata;
682 struct platform_device *pdev;
683 struct omap_timer_capability_dev_attr *timer_dev_attr;
685 pr_debug("%s: %s\n", __func__, oh->name);
687 /* on secure device, do not register secure timer */
688 timer_dev_attr = oh->dev_attr;
689 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
690 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
693 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
695 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
700 * Extract the IDs from name field in hwmod database
701 * and use the same for constructing ids' for the
702 * timer devices. In a way, we are avoiding usage of
703 * static variable witin the function to do the same.
704 * CAUTION: We have to be careful and make sure the
705 * name in hwmod database does not change in which case
706 * we might either make corresponding change here or
707 * switch back static variable mechanism.
709 sscanf(oh->name, "timer%2d", &id);
712 pdata->timer_capability = timer_dev_attr->timer_capability;
714 pdata->timer_errata = omap_dm_timer_get_errata();
715 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
717 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata));
720 pr_err("%s: Can't build omap_device for %s: %s.\n",
721 __func__, name, oh->name);
731 * omap2_dm_timer_init - top level regular device initialization
733 * Uses dedicated hwmod api to parse through hwmod database for
734 * given class name and then build and register the timer device.
736 static int __init omap2_dm_timer_init(void)
740 /* If dtb is there, the devices will be created dynamically */
741 if (of_have_populated_dt())
744 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
746 pr_err("%s: device registration failed.\n", __func__);
752 omap_arch_initcall(omap2_dm_timer_init);
755 * omap2_override_clocksource - clocksource override with user configuration
757 * Allows user to override default clocksource, using kernel parameter
758 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
760 * Note that, here we are using same standard kernel parameter "clocksource=",
761 * and not introducing any OMAP specific interface.
763 static int __init omap2_override_clocksource(char *str)
768 * For OMAP architecture, we only have two options
769 * - sync_32k (default)
770 * - gp_timer (sys_clk based)
772 if (!strcmp(str, "gp_timer"))
773 use_gptimer_clksrc = true;
777 early_param("clocksource", omap2_override_clocksource);