arch/arm/mach-shmobile/platsmp-apmu.c

   1 /*
   2  * SMP support for SoCs with APMU
   3  *
   4  * Copyright (C) 2014  Renesas Electronics Corporation
   5  * Copyright (C) 2013  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/cpu_pm.h>
  12 #include <linux/delay.h>
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/ioport.h>
  16 #include <linux/of_address.h>
  17 #include <linux/smp.h>
  18 #include <linux/suspend.h>
  19 #include <linux/threads.h>
  20 #include <asm/cacheflush.h>
  21 #include <asm/cp15.h>
  22 #include <asm/proc-fns.h>
  23 #include <asm/smp_plat.h>
  24 #include <asm/suspend.h>
  25 #include "common.h"
  26 #include "platsmp-apmu.h"
  27 #include "rcar-gen2.h"
  28
  29 static struct {
  30         void __iomem *iomem;
  31         int bit;
  32 } apmu_cpus[NR_CPUS];
  33
  34 #define WUPCR_OFFS 0x10
  35 #define PSTR_OFFS 0x40
  36 #define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
  37
  38 static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
  39 {
  40         /* request power on */
  41         writel_relaxed(BIT(bit), p + WUPCR_OFFS);
  42
  43         /* wait for APMU to finish */
  44         while (readl_relaxed(p + WUPCR_OFFS) != 0)
  45                 ;
  46
  47         return 0;
  48 }
  49
  50 static int __maybe_unused apmu_power_off(void __iomem *p, int bit)
  51 {
  52         /* request Core Standby for next WFI */
  53         writel_relaxed(3, p + CPUNCR_OFFS(bit));
  54         return 0;
  55 }
  56
  57 static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit)
  58 {
  59         int k;
  60
  61         for (k = 0; k < 1000; k++) {
  62                 if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3)
  63                         return 1;
  64
  65                 mdelay(1);
  66         }
  67
  68         return 0;
  69 }
  70
  71 static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu))
  72 {
  73         void __iomem *p = apmu_cpus[cpu].iomem;
  74
  75         return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL;
  76 }
  77
  78 #ifdef CONFIG_SMP
  79 static void apmu_init_cpu(struct resource *res, int cpu, int bit)
  80 {
  81         if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)
  82                 return;
  83
  84         apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
  85         apmu_cpus[cpu].bit = bit;
  86
  87         pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
  88 }
  89
  90 static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit),
  91                            struct rcar_apmu_config *apmu_config, int num)
  92 {
  93         int id;
  94         int k;
  95         int bit, index;
  96         bool is_allowed;
  97
  98         for (k = 0; k < num; k++) {
  99                 /* only enable the cluster that includes the boot CPU */
 100                 is_allowed = false;
 101                 for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
 102                         id = apmu_config[k].cpus[bit];
 103                         if (id >= 0) {
 104                                 if (id == cpu_logical_map(0))
 105                                         is_allowed = true;
 106                         }
 107                 }
 108                 if (!is_allowed)
 109                         continue;
 110
 111                 for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
 112                         id = apmu_config[k].cpus[bit];
 113                         if (id >= 0) {
 114                                 index = get_logical_index(id);
 115                                 if (index >= 0)
 116                                         fn(&apmu_config[k].iomem, index, bit);
 117                         }
 118                 }
 119         }
 120 }
 121
 122 static const struct of_device_id apmu_ids[] = {
 123         { .compatible = "renesas,apmu" },
 124         { /*sentinel*/ }
 125 };
 126
 127 static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit))
 128 {
 129         struct device_node *np_apmu, *np_cpu;
 130         struct resource res;
 131         int bit, index;
 132         u32 id;
 133
 134         for_each_matching_node(np_apmu, apmu_ids) {
 135                 /* only enable the cluster that includes the boot CPU */
 136                 bool is_allowed = false;
 137
 138                 for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
 139                         np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
 140                         if (np_cpu) {
 141                                 if (!of_property_read_u32(np_cpu, "reg", &id)) {
 142                                         if (id == cpu_logical_map(0)) {
 143                                                 is_allowed = true;
 144                                                 of_node_put(np_cpu);
 145                                                 break;
 146                                         }
 147
 148                                 }
 149                                 of_node_put(np_cpu);
 150                         }
 151                 }
 152                 if (!is_allowed)
 153                         continue;
 154
 155                 for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
 156                         np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
 157                         if (np_cpu) {
 158                                 if (!of_property_read_u32(np_cpu, "reg", &id)) {
 159                                         index = get_logical_index(id);
 160                                         if ((index >= 0) &&
 161                                             !of_address_to_resource(np_apmu,
 162                                                                     0, &res))
 163                                                 fn(&res, index, bit);
 164                                 }
 165                                 of_node_put(np_cpu);
 166                         }
 167                 }
 168         }
 169 }
 170
 171 static void __init shmobile_smp_apmu_setup_boot(void)
 172 {
 173         /* install boot code shared by all CPUs */
 174         shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
 175 }
 176
 177 void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
 178                                            struct rcar_apmu_config *apmu_config,
 179                                            int num)
 180 {
 181         shmobile_smp_apmu_setup_boot();
 182         apmu_parse_cfg(apmu_init_cpu, apmu_config, num);
 183 }
 184
 185 int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
 186 {
 187         /* For this particular CPU register boot vector */
 188         shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
 189
 190         return apmu_wrap(cpu, apmu_power_on);
 191 }
 192
 193 static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus)
 194 {
 195         shmobile_smp_apmu_setup_boot();
 196         apmu_parse_dt(apmu_init_cpu);
 197         rcar_gen2_pm_init();
 198 }
 199
 200 static int shmobile_smp_apmu_boot_secondary_md21(unsigned int cpu,
 201                                                  struct task_struct *idle)
 202 {
 203         /* Error out when hardware debug mode is enabled */
 204         if (rcar_gen2_read_mode_pins() & BIT(21)) {
 205                 pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu);
 206                 return -ENOTSUPP;
 207         }
 208
 209         return shmobile_smp_apmu_boot_secondary(cpu, idle);
 210 }
 211
 212 static struct smp_operations apmu_smp_ops __initdata = {
 213         .smp_prepare_cpus       = shmobile_smp_apmu_prepare_cpus_dt,
 214         .smp_boot_secondary     = shmobile_smp_apmu_boot_secondary_md21,
 215 #ifdef CONFIG_HOTPLUG_CPU
 216         .cpu_can_disable        = shmobile_smp_cpu_can_disable,
 217         .cpu_die                = shmobile_smp_apmu_cpu_die,
 218         .cpu_kill               = shmobile_smp_apmu_cpu_kill,
 219 #endif
 220 };
 221
 222 CPU_METHOD_OF_DECLARE(shmobile_smp_apmu, "renesas,apmu", &apmu_smp_ops);
 223 #endif /* CONFIG_SMP */
 224
 225 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND)
 226 /* nicked from arch/arm/mach-exynos/hotplug.c */
 227 static inline void cpu_enter_lowpower_a15(void)
 228 {
 229         unsigned int v;
 230
 231         asm volatile(
 232         "       mrc     p15, 0, %0, c1, c0, 0\n"
 233         "       bic     %0, %0, %1\n"
 234         "       mcr     p15, 0, %0, c1, c0, 0\n"
 235                 : "=&r" (v)
 236                 : "Ir" (CR_C)
 237                 : "cc");
 238
 239         flush_cache_louis();
 240
 241         asm volatile(
 242         /*
 243          * Turn off coherency
 244          */
 245         "       mrc     p15, 0, %0, c1, c0, 1\n"
 246         "       bic     %0, %0, %1\n"
 247         "       mcr     p15, 0, %0, c1, c0, 1\n"
 248                 : "=&r" (v)
 249                 : "Ir" (0x40)
 250                 : "cc");
 251
 252         isb();
 253         dsb();
 254 }
 255
 256 static void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu)
 257 {
 258
 259         /* Select next sleep mode using the APMU */
 260         apmu_wrap(cpu, apmu_power_off);
 261
 262         /* Do ARM specific CPU shutdown */
 263         cpu_enter_lowpower_a15();
 264 }
 265
 266 static inline void cpu_leave_lowpower(void)
 267 {
 268         unsigned int v;
 269
 270         asm volatile("mrc    p15, 0, %0, c1, c0, 0\n"
 271                      "       orr     %0, %0, %1\n"
 272                      "       mcr     p15, 0, %0, c1, c0, 0\n"
 273                      "       mrc     p15, 0, %0, c1, c0, 1\n"
 274                      "       orr     %0, %0, %2\n"
 275                      "       mcr     p15, 0, %0, c1, c0, 1\n"
 276                      : "=&r" (v)
 277                      : "Ir" (CR_C), "Ir" (0x40)
 278                      : "cc");
 279 }
 280 #endif
 281
 282 #if defined(CONFIG_HOTPLUG_CPU)
 283 void shmobile_smp_apmu_cpu_die(unsigned int cpu)
 284 {
 285         /* For this particular CPU deregister boot vector */
 286         shmobile_smp_hook(cpu, 0, 0);
 287
 288         /* Shutdown CPU core */
 289         shmobile_smp_apmu_cpu_shutdown(cpu);
 290
 291         /* jump to shared mach-shmobile sleep / reset code */
 292         shmobile_smp_sleep();
 293 }
 294
 295 int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
 296 {
 297         return apmu_wrap(cpu, apmu_power_off_poll);
 298 }
 299 #endif
 300
 301 #if defined(CONFIG_SUSPEND)
 302 static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
 303 {
 304         shmobile_smp_hook(cpu, virt_to_phys(cpu_resume), 0);
 305         shmobile_smp_apmu_cpu_shutdown(cpu);
 306         cpu_do_idle(); /* WFI selects Core Standby */
 307         return 1;
 308 }
 309
 310 static int shmobile_smp_apmu_enter_suspend(suspend_state_t state)
 311 {
 312         cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend);
 313         cpu_leave_lowpower();
 314         return 0;
 315 }
 316
 317 void __init shmobile_smp_apmu_suspend_init(void)
 318 {
 319         shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend;
 320 }
 321 #endif