2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/bootmem.h>
13 #include <linux/module.h>
15 #include <linux/genalloc.h>
16 #include <linux/gfp.h>
17 #include <linux/errno.h>
18 #include <linux/list.h>
19 #include <linux/init.h>
20 #include <linux/device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-contiguous.h>
23 #include <linux/highmem.h>
24 #include <linux/memblock.h>
25 #include <linux/slab.h>
26 #include <linux/iommu.h>
28 #include <linux/vmalloc.h>
29 #include <linux/sizes.h>
30 #include <linux/cma.h>
32 #include <asm/memory.h>
33 #include <asm/highmem.h>
34 #include <asm/cacheflush.h>
35 #include <asm/tlbflush.h>
36 #include <asm/mach/arch.h>
37 #include <asm/dma-iommu.h>
38 #include <asm/mach/map.h>
39 #include <asm/system_info.h>
40 #include <asm/dma-contiguous.h>
45 struct arm_dma_alloc_args {
55 struct arm_dma_free_args {
66 struct arm_dma_allocator {
67 void *(*alloc)(struct arm_dma_alloc_args *args,
68 struct page **ret_page);
69 void (*free)(struct arm_dma_free_args *args);
72 struct arm_dma_buffer {
73 struct list_head list;
75 struct arm_dma_allocator *allocator;
78 static LIST_HEAD(arm_dma_bufs);
79 static DEFINE_SPINLOCK(arm_dma_bufs_lock);
81 static struct arm_dma_buffer *arm_dma_buffer_find(void *virt)
83 struct arm_dma_buffer *buf, *found = NULL;
86 spin_lock_irqsave(&arm_dma_bufs_lock, flags);
87 list_for_each_entry(buf, &arm_dma_bufs, list) {
88 if (buf->virt == virt) {
94 spin_unlock_irqrestore(&arm_dma_bufs_lock, flags);
99 * The DMA API is built upon the notion of "buffer ownership". A buffer
100 * is either exclusively owned by the CPU (and therefore may be accessed
101 * by it) or exclusively owned by the DMA device. These helper functions
102 * represent the transitions between these two ownership states.
104 * Note, however, that on later ARMs, this notion does not work due to
105 * speculative prefetches. We model our approach on the assumption that
106 * the CPU does do speculative prefetches, which means we clean caches
107 * before transfers and delay cache invalidation until transfer completion.
110 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
111 size_t, enum dma_data_direction);
112 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
113 size_t, enum dma_data_direction);
116 * arm_dma_map_page - map a portion of a page for streaming DMA
117 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
118 * @page: page that buffer resides in
119 * @offset: offset into page for start of buffer
120 * @size: size of buffer to map
121 * @dir: DMA transfer direction
123 * Ensure that any data held in the cache is appropriately discarded
126 * The device owns this memory once this call has completed. The CPU
127 * can regain ownership by calling dma_unmap_page().
129 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
130 unsigned long offset, size_t size, enum dma_data_direction dir,
133 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
134 __dma_page_cpu_to_dev(page, offset, size, dir);
135 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
138 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
139 unsigned long offset, size_t size, enum dma_data_direction dir,
142 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
146 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
147 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
148 * @handle: DMA address of buffer
149 * @size: size of buffer (same as passed to dma_map_page)
150 * @dir: DMA transfer direction (same as passed to dma_map_page)
152 * Unmap a page streaming mode DMA translation. The handle and size
153 * must match what was provided in the previous dma_map_page() call.
154 * All other usages are undefined.
156 * After this call, reads by the CPU to the buffer are guaranteed to see
157 * whatever the device wrote there.
159 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
160 size_t size, enum dma_data_direction dir, unsigned long attrs)
162 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
163 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
164 handle & ~PAGE_MASK, size, dir);
167 static void arm_dma_sync_single_for_cpu(struct device *dev,
168 dma_addr_t handle, size_t size, enum dma_data_direction dir)
170 unsigned int offset = handle & (PAGE_SIZE - 1);
171 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
172 __dma_page_dev_to_cpu(page, offset, size, dir);
175 static void arm_dma_sync_single_for_device(struct device *dev,
176 dma_addr_t handle, size_t size, enum dma_data_direction dir)
178 unsigned int offset = handle & (PAGE_SIZE - 1);
179 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
180 __dma_page_cpu_to_dev(page, offset, size, dir);
183 struct dma_map_ops arm_dma_ops = {
184 .alloc = arm_dma_alloc,
185 .free = arm_dma_free,
186 .mmap = arm_dma_mmap,
187 .get_sgtable = arm_dma_get_sgtable,
188 .map_page = arm_dma_map_page,
189 .unmap_page = arm_dma_unmap_page,
190 .map_sg = arm_dma_map_sg,
191 .unmap_sg = arm_dma_unmap_sg,
192 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
193 .sync_single_for_device = arm_dma_sync_single_for_device,
194 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
195 .sync_sg_for_device = arm_dma_sync_sg_for_device,
197 EXPORT_SYMBOL(arm_dma_ops);
199 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
200 dma_addr_t *handle, gfp_t gfp, unsigned long attrs);
201 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
202 dma_addr_t handle, unsigned long attrs);
203 static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma,
204 void *cpu_addr, dma_addr_t dma_addr, size_t size,
205 unsigned long attrs);
207 struct dma_map_ops arm_coherent_dma_ops = {
208 .alloc = arm_coherent_dma_alloc,
209 .free = arm_coherent_dma_free,
210 .mmap = arm_coherent_dma_mmap,
211 .get_sgtable = arm_dma_get_sgtable,
212 .map_page = arm_coherent_dma_map_page,
213 .map_sg = arm_dma_map_sg,
215 EXPORT_SYMBOL(arm_coherent_dma_ops);
217 static int __dma_supported(struct device *dev, u64 mask, bool warn)
219 unsigned long max_dma_pfn;
222 * If the mask allows for more memory than we can address,
223 * and we actually have that much memory, then we must
224 * indicate that DMA to this device is not supported.
226 if (sizeof(mask) != sizeof(dma_addr_t) &&
227 mask > (dma_addr_t)~0 &&
228 dma_to_pfn(dev, ~0) < max_pfn - 1) {
230 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
232 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
237 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
240 * Translate the device's DMA mask to a PFN limit. This
241 * PFN number includes the page which we can DMA to.
243 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
245 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
247 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
255 static u64 get_coherent_dma_mask(struct device *dev)
257 u64 mask = (u64)DMA_BIT_MASK(32);
260 mask = dev->coherent_dma_mask;
263 * Sanity check the DMA mask - it must be non-zero, and
264 * must be able to be satisfied by a DMA allocation.
267 dev_warn(dev, "coherent DMA mask is unset\n");
271 if (!__dma_supported(dev, mask, true))
278 static void __dma_clear_buffer(struct page *page, size_t size, int coherent_flag)
281 * Ensure that the allocated pages are zeroed, and that any data
282 * lurking in the kernel direct-mapped region is invalidated.
284 if (PageHighMem(page)) {
285 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
286 phys_addr_t end = base + size;
288 void *ptr = kmap_atomic(page);
289 memset(ptr, 0, PAGE_SIZE);
290 if (coherent_flag != COHERENT)
291 dmac_flush_range(ptr, ptr + PAGE_SIZE);
296 if (coherent_flag != COHERENT)
297 outer_flush_range(base, end);
299 void *ptr = page_address(page);
300 memset(ptr, 0, size);
301 if (coherent_flag != COHERENT) {
302 dmac_flush_range(ptr, ptr + size);
303 outer_flush_range(__pa(ptr), __pa(ptr) + size);
309 * Allocate a DMA buffer for 'dev' of size 'size' using the
310 * specified gfp mask. Note that 'size' must be page aligned.
312 static struct page *__dma_alloc_buffer(struct device *dev, size_t size,
313 gfp_t gfp, int coherent_flag)
315 unsigned long order = get_order(size);
316 struct page *page, *p, *e;
318 page = alloc_pages(gfp, order);
323 * Now split the huge page and free the excess pages
325 split_page(page, order);
326 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
329 __dma_clear_buffer(page, size, coherent_flag);
335 * Free a DMA buffer. 'size' must be page aligned.
337 static void __dma_free_buffer(struct page *page, size_t size)
339 struct page *e = page + (size >> PAGE_SHIFT);
349 static void *__alloc_from_contiguous(struct device *dev, size_t size,
350 pgprot_t prot, struct page **ret_page,
351 const void *caller, bool want_vaddr,
354 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
355 pgprot_t prot, struct page **ret_page,
356 const void *caller, bool want_vaddr);
359 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
363 * DMA allocation can be mapped to user space, so lets
364 * set VM_USERMAP flags too.
366 return dma_common_contiguous_remap(page, size,
367 VM_ARM_DMA_CONSISTENT | VM_USERMAP,
371 static void __dma_free_remap(void *cpu_addr, size_t size)
373 dma_common_free_remap(cpu_addr, size,
374 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
377 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
378 static struct gen_pool *atomic_pool;
380 static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;
382 static int __init early_coherent_pool(char *p)
384 atomic_pool_size = memparse(p, &p);
387 early_param("coherent_pool", early_coherent_pool);
389 void __init init_dma_coherent_pool_size(unsigned long size)
392 * Catch any attempt to set the pool size too late.
397 * Set architecture specific coherent pool size only if
398 * it has not been changed by kernel command line parameter.
400 if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE)
401 atomic_pool_size = size;
405 * Initialise the coherent pool for atomic allocations.
407 static int __init atomic_pool_init(void)
409 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
410 gfp_t gfp = GFP_KERNEL | GFP_DMA;
414 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
418 * The atomic pool is only used for non-coherent allocations
419 * so we must pass NORMAL for coherent_flag.
421 if (dev_get_cma_area(NULL))
422 ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot,
423 &page, atomic_pool_init, true, NORMAL);
425 ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot,
426 &page, atomic_pool_init, true);
430 ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr,
432 atomic_pool_size, -1);
434 goto destroy_genpool;
436 gen_pool_set_algo(atomic_pool,
437 gen_pool_first_fit_order_align,
439 pr_info("DMA: preallocated %zu KiB pool for atomic coherent allocations\n",
440 atomic_pool_size / 1024);
445 gen_pool_destroy(atomic_pool);
448 pr_err("DMA: failed to allocate %zu KiB pool for atomic coherent allocation\n",
449 atomic_pool_size / 1024);
453 * CMA is activated by core_initcall, so we must be called after it.
455 postcore_initcall(atomic_pool_init);
457 struct dma_contig_early_reserve {
462 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
464 static int dma_mmu_remap_num __initdata;
466 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
468 dma_mmu_remap[dma_mmu_remap_num].base = base;
469 dma_mmu_remap[dma_mmu_remap_num].size = size;
473 void __init dma_contiguous_remap(void)
476 for (i = 0; i < dma_mmu_remap_num; i++) {
477 phys_addr_t start = dma_mmu_remap[i].base;
478 phys_addr_t end = start + dma_mmu_remap[i].size;
482 if (end > arm_lowmem_limit)
483 end = arm_lowmem_limit;
487 map.pfn = __phys_to_pfn(start);
488 map.virtual = __phys_to_virt(start);
489 map.length = end - start;
490 map.type = MT_MEMORY_DMA_READY;
493 * Clear previous low-memory mapping to ensure that the
494 * TLB does not see any conflicting entries, then flush
495 * the TLB of the old entries before creating new mappings.
497 * This ensures that any speculatively loaded TLB entries
498 * (even though they may be rare) can not cause any problems,
499 * and ensures that this code is architecturally compliant.
501 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
503 pmd_clear(pmd_off_k(addr));
505 flush_tlb_kernel_range(__phys_to_virt(start),
506 __phys_to_virt(end));
508 iotable_init(&map, 1);
512 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
515 struct page *page = virt_to_page(addr);
516 pgprot_t prot = *(pgprot_t *)data;
518 set_pte_ext(pte, mk_pte(page, prot), 0);
522 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
524 unsigned long start = (unsigned long) page_address(page);
525 unsigned end = start + size;
527 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
528 flush_tlb_kernel_range(start, end);
531 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
532 pgprot_t prot, struct page **ret_page,
533 const void *caller, bool want_vaddr)
538 * __alloc_remap_buffer is only called when the device is
541 page = __dma_alloc_buffer(dev, size, gfp, NORMAL);
547 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
549 __dma_free_buffer(page, size);
558 static void *__alloc_from_pool(size_t size, struct page **ret_page)
564 WARN(1, "coherent pool not initialised!\n");
568 val = gen_pool_alloc(atomic_pool, size);
570 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
572 *ret_page = phys_to_page(phys);
579 static bool __in_atomic_pool(void *start, size_t size)
581 return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
584 static int __free_from_pool(void *start, size_t size)
586 if (!__in_atomic_pool(start, size))
589 gen_pool_free(atomic_pool, (unsigned long)start, size);
594 static void *__alloc_from_contiguous(struct device *dev, size_t size,
595 pgprot_t prot, struct page **ret_page,
596 const void *caller, bool want_vaddr,
599 unsigned long order = get_order(size);
600 size_t count = size >> PAGE_SHIFT;
604 page = dma_alloc_from_contiguous(dev, count, order);
608 __dma_clear_buffer(page, size, coherent_flag);
613 if (PageHighMem(page)) {
614 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
616 dma_release_from_contiguous(dev, page, count);
620 __dma_remap(page, size, prot);
621 ptr = page_address(page);
629 static void __free_from_contiguous(struct device *dev, struct page *page,
630 void *cpu_addr, size_t size, bool want_vaddr)
633 if (PageHighMem(page))
634 __dma_free_remap(cpu_addr, size);
636 __dma_remap(page, size, PAGE_KERNEL);
638 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
641 static inline pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot)
643 prot = (attrs & DMA_ATTR_WRITE_COMBINE) ?
644 pgprot_writecombine(prot) :
645 pgprot_dmacoherent(prot);
651 #else /* !CONFIG_MMU */
655 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
656 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL
657 #define __alloc_from_pool(size, ret_page) NULL
658 #define __alloc_from_contiguous(dev, size, prot, ret, c, wv, coherent_flag) NULL
659 #define __free_from_pool(cpu_addr, size) do { } while (0)
660 #define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0)
661 #define __dma_free_remap(cpu_addr, size) do { } while (0)
663 #endif /* CONFIG_MMU */
665 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
666 struct page **ret_page)
669 /* __alloc_simple_buffer is only called when the device is coherent */
670 page = __dma_alloc_buffer(dev, size, gfp, COHERENT);
675 return page_address(page);
678 static void *simple_allocator_alloc(struct arm_dma_alloc_args *args,
679 struct page **ret_page)
681 return __alloc_simple_buffer(args->dev, args->size, args->gfp,
685 static void simple_allocator_free(struct arm_dma_free_args *args)
687 __dma_free_buffer(args->page, args->size);
690 static struct arm_dma_allocator simple_allocator = {
691 .alloc = simple_allocator_alloc,
692 .free = simple_allocator_free,
695 static void *cma_allocator_alloc(struct arm_dma_alloc_args *args,
696 struct page **ret_page)
698 return __alloc_from_contiguous(args->dev, args->size, args->prot,
699 ret_page, args->caller,
700 args->want_vaddr, args->coherent_flag);
703 static void cma_allocator_free(struct arm_dma_free_args *args)
705 __free_from_contiguous(args->dev, args->page, args->cpu_addr,
706 args->size, args->want_vaddr);
709 static struct arm_dma_allocator cma_allocator = {
710 .alloc = cma_allocator_alloc,
711 .free = cma_allocator_free,
714 static void *pool_allocator_alloc(struct arm_dma_alloc_args *args,
715 struct page **ret_page)
717 return __alloc_from_pool(args->size, ret_page);
720 static void pool_allocator_free(struct arm_dma_free_args *args)
722 __free_from_pool(args->cpu_addr, args->size);
725 static struct arm_dma_allocator pool_allocator = {
726 .alloc = pool_allocator_alloc,
727 .free = pool_allocator_free,
730 static void *remap_allocator_alloc(struct arm_dma_alloc_args *args,
731 struct page **ret_page)
733 return __alloc_remap_buffer(args->dev, args->size, args->gfp,
734 args->prot, ret_page, args->caller,
738 static void remap_allocator_free(struct arm_dma_free_args *args)
740 if (args->want_vaddr)
741 __dma_free_remap(args->cpu_addr, args->size);
743 __dma_free_buffer(args->page, args->size);
746 static struct arm_dma_allocator remap_allocator = {
747 .alloc = remap_allocator_alloc,
748 .free = remap_allocator_free,
751 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
752 gfp_t gfp, pgprot_t prot, bool is_coherent,
753 unsigned long attrs, const void *caller)
755 u64 mask = get_coherent_dma_mask(dev);
756 struct page *page = NULL;
758 bool allowblock, cma;
759 struct arm_dma_buffer *buf;
760 struct arm_dma_alloc_args args = {
762 .size = PAGE_ALIGN(size),
766 .want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0),
767 .coherent_flag = is_coherent ? COHERENT : NORMAL,
770 #ifdef CONFIG_DMA_API_DEBUG
771 u64 limit = (mask + 1) & ~mask;
772 if (limit && size >= limit) {
773 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
782 buf = kzalloc(sizeof(*buf),
783 gfp & ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM));
787 if (mask < 0xffffffffULL)
791 * Following is a work-around (a.k.a. hack) to prevent pages
792 * with __GFP_COMP being passed to split_page() which cannot
793 * handle them. The real problem is that this flag probably
794 * should be 0 on ARM as it is not supported on this
795 * platform; see CONFIG_HUGETLBFS.
797 gfp &= ~(__GFP_COMP);
800 *handle = DMA_ERROR_CODE;
801 allowblock = gfpflags_allow_blocking(gfp);
802 cma = allowblock ? dev_get_cma_area(dev) : false;
805 buf->allocator = &cma_allocator;
806 else if (nommu() || is_coherent)
807 buf->allocator = &simple_allocator;
809 buf->allocator = &remap_allocator;
811 buf->allocator = &pool_allocator;
813 addr = buf->allocator->alloc(&args, &page);
818 *handle = pfn_to_dma(dev, page_to_pfn(page));
819 buf->virt = args.want_vaddr ? addr : page;
821 spin_lock_irqsave(&arm_dma_bufs_lock, flags);
822 list_add(&buf->list, &arm_dma_bufs);
823 spin_unlock_irqrestore(&arm_dma_bufs_lock, flags);
828 return args.want_vaddr ? addr : page;
832 * Allocate DMA-coherent memory space and return both the kernel remapped
833 * virtual and bus address for that space.
835 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
836 gfp_t gfp, unsigned long attrs)
838 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
840 return __dma_alloc(dev, size, handle, gfp, prot, false,
841 attrs, __builtin_return_address(0));
844 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
845 dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
847 return __dma_alloc(dev, size, handle, gfp, PAGE_KERNEL, true,
848 attrs, __builtin_return_address(0));
851 static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
852 void *cpu_addr, dma_addr_t dma_addr, size_t size,
857 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
858 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
859 unsigned long pfn = dma_to_pfn(dev, dma_addr);
860 unsigned long off = vma->vm_pgoff;
862 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
865 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
866 ret = remap_pfn_range(vma, vma->vm_start,
868 vma->vm_end - vma->vm_start,
871 #endif /* CONFIG_MMU */
877 * Create userspace mapping for the DMA-coherent memory.
879 static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma,
880 void *cpu_addr, dma_addr_t dma_addr, size_t size,
883 return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
886 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
887 void *cpu_addr, dma_addr_t dma_addr, size_t size,
891 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
892 #endif /* CONFIG_MMU */
893 return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
897 * Free a buffer as defined by the above mapping.
899 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
900 dma_addr_t handle, unsigned long attrs,
903 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
904 struct arm_dma_buffer *buf;
905 struct arm_dma_free_args args = {
907 .size = PAGE_ALIGN(size),
908 .cpu_addr = cpu_addr,
910 .want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0),
913 buf = arm_dma_buffer_find(cpu_addr);
914 if (WARN(!buf, "Freeing invalid buffer %p\n", cpu_addr))
917 buf->allocator->free(&args);
921 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
922 dma_addr_t handle, unsigned long attrs)
924 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
927 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
928 dma_addr_t handle, unsigned long attrs)
930 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
934 * The whole dma_get_sgtable() idea is fundamentally unsafe - it seems
935 * that the intention is to allow exporting memory allocated via the
936 * coherent DMA APIs through the dma_buf API, which only accepts a
937 * scattertable. This presents a couple of problems:
938 * 1. Not all memory allocated via the coherent DMA APIs is backed by
940 * 2. Passing coherent DMA memory into the streaming APIs is not allowed
941 * as we will try to flush the memory through a different alias to that
942 * actually being used (and the flushes are redundant.)
944 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
945 void *cpu_addr, dma_addr_t handle, size_t size,
948 unsigned long pfn = dma_to_pfn(dev, handle);
952 /* If the PFN is not valid, we do not have a struct page */
956 page = pfn_to_page(pfn);
958 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
962 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
966 static void dma_cache_maint_page(struct page *page, unsigned long offset,
967 size_t size, enum dma_data_direction dir,
968 void (*op)(const void *, size_t, int))
973 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
977 * A single sg entry may refer to multiple physically contiguous
978 * pages. But we still need to process highmem pages individually.
979 * If highmem is not configured then the bulk of this loop gets
986 page = pfn_to_page(pfn);
988 if (PageHighMem(page)) {
989 if (len + offset > PAGE_SIZE)
990 len = PAGE_SIZE - offset;
992 if (cache_is_vipt_nonaliasing()) {
993 vaddr = kmap_atomic(page);
994 op(vaddr + offset, len, dir);
995 kunmap_atomic(vaddr);
997 vaddr = kmap_high_get(page);
999 op(vaddr + offset, len, dir);
1004 vaddr = page_address(page) + offset;
1005 op(vaddr, len, dir);
1014 * Make an area consistent for devices.
1015 * Note: Drivers should NOT use this function directly, as it will break
1016 * platforms with CONFIG_DMABOUNCE.
1017 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
1019 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
1020 size_t size, enum dma_data_direction dir)
1024 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
1026 paddr = page_to_phys(page) + off;
1027 if (dir == DMA_FROM_DEVICE) {
1028 outer_inv_range(paddr, paddr + size);
1030 outer_clean_range(paddr, paddr + size);
1032 /* FIXME: non-speculating: flush on bidirectional mappings? */
1035 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
1036 size_t size, enum dma_data_direction dir)
1038 phys_addr_t paddr = page_to_phys(page) + off;
1040 /* FIXME: non-speculating: not required */
1041 /* in any case, don't bother invalidating if DMA to device */
1042 if (dir != DMA_TO_DEVICE) {
1043 outer_inv_range(paddr, paddr + size);
1045 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
1049 * Mark the D-cache clean for these pages to avoid extra flushing.
1051 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
1055 pfn = page_to_pfn(page) + off / PAGE_SIZE;
1059 left -= PAGE_SIZE - off;
1061 while (left >= PAGE_SIZE) {
1062 page = pfn_to_page(pfn++);
1063 set_bit(PG_dcache_clean, &page->flags);
1070 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
1071 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1072 * @sg: list of buffers
1073 * @nents: number of buffers to map
1074 * @dir: DMA transfer direction
1076 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1077 * This is the scatter-gather version of the dma_map_single interface.
1078 * Here the scatter gather list elements are each tagged with the
1079 * appropriate dma address and length. They are obtained via
1080 * sg_dma_{address,length}.
1082 * Device ownership issues as mentioned for dma_map_single are the same
1085 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1086 enum dma_data_direction dir, unsigned long attrs)
1088 struct dma_map_ops *ops = get_dma_ops(dev);
1089 struct scatterlist *s;
1092 for_each_sg(sg, s, nents, i) {
1093 #ifdef CONFIG_NEED_SG_DMA_LENGTH
1094 s->dma_length = s->length;
1096 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
1097 s->length, dir, attrs);
1098 if (dma_mapping_error(dev, s->dma_address))
1104 for_each_sg(sg, s, i, j)
1105 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
1110 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1111 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1112 * @sg: list of buffers
1113 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1114 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1116 * Unmap a set of streaming mode DMA translations. Again, CPU access
1117 * rules concerning calls here are the same as for dma_unmap_single().
1119 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1120 enum dma_data_direction dir, unsigned long attrs)
1122 struct dma_map_ops *ops = get_dma_ops(dev);
1123 struct scatterlist *s;
1127 for_each_sg(sg, s, nents, i)
1128 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
1132 * arm_dma_sync_sg_for_cpu
1133 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1134 * @sg: list of buffers
1135 * @nents: number of buffers to map (returned from dma_map_sg)
1136 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1138 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1139 int nents, enum dma_data_direction dir)
1141 struct dma_map_ops *ops = get_dma_ops(dev);
1142 struct scatterlist *s;
1145 for_each_sg(sg, s, nents, i)
1146 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
1151 * arm_dma_sync_sg_for_device
1152 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1153 * @sg: list of buffers
1154 * @nents: number of buffers to map (returned from dma_map_sg)
1155 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1157 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1158 int nents, enum dma_data_direction dir)
1160 struct dma_map_ops *ops = get_dma_ops(dev);
1161 struct scatterlist *s;
1164 for_each_sg(sg, s, nents, i)
1165 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
1170 * Return whether the given device DMA address mask can be supported
1171 * properly. For example, if your device can only drive the low 24-bits
1172 * during bus mastering, then you would pass 0x00ffffff as the mask
1175 int dma_supported(struct device *dev, u64 mask)
1177 return __dma_supported(dev, mask, false);
1179 EXPORT_SYMBOL(dma_supported);
1181 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1183 static int __init dma_debug_do_init(void)
1185 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1188 core_initcall(dma_debug_do_init);
1190 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1194 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping);
1196 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1199 unsigned int order = get_order(size);
1200 unsigned int align = 0;
1201 unsigned int count, start;
1202 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1203 unsigned long flags;
1207 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1208 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1210 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1211 align = (1 << order) - 1;
1213 spin_lock_irqsave(&mapping->lock, flags);
1214 for (i = 0; i < mapping->nr_bitmaps; i++) {
1215 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1216 mapping->bits, 0, count, align);
1218 if (start > mapping->bits)
1221 bitmap_set(mapping->bitmaps[i], start, count);
1226 * No unused range found. Try to extend the existing mapping
1227 * and perform a second attempt to reserve an IO virtual
1228 * address range of size bytes.
1230 if (i == mapping->nr_bitmaps) {
1231 if (extend_iommu_mapping(mapping)) {
1232 spin_unlock_irqrestore(&mapping->lock, flags);
1233 return DMA_ERROR_CODE;
1236 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1237 mapping->bits, 0, count, align);
1239 if (start > mapping->bits) {
1240 spin_unlock_irqrestore(&mapping->lock, flags);
1241 return DMA_ERROR_CODE;
1244 bitmap_set(mapping->bitmaps[i], start, count);
1246 spin_unlock_irqrestore(&mapping->lock, flags);
1248 iova = mapping->base + (mapping_size * i);
1249 iova += start << PAGE_SHIFT;
1254 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1255 dma_addr_t addr, size_t size)
1257 unsigned int start, count;
1258 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1259 unsigned long flags;
1260 dma_addr_t bitmap_base;
1266 bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size;
1267 BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
1269 bitmap_base = mapping->base + mapping_size * bitmap_index;
1271 start = (addr - bitmap_base) >> PAGE_SHIFT;
1273 if (addr + size > bitmap_base + mapping_size) {
1275 * The address range to be freed reaches into the iova
1276 * range of the next bitmap. This should not happen as
1277 * we don't allow this in __alloc_iova (at the
1282 count = size >> PAGE_SHIFT;
1284 spin_lock_irqsave(&mapping->lock, flags);
1285 bitmap_clear(mapping->bitmaps[bitmap_index], start, count);
1286 spin_unlock_irqrestore(&mapping->lock, flags);
1289 /* We'll try 2M, 1M, 64K, and finally 4K; array must end with 0! */
1290 static const int iommu_order_array[] = { 9, 8, 4, 0 };
1292 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1293 gfp_t gfp, unsigned long attrs,
1296 struct page **pages;
1297 int count = size >> PAGE_SHIFT;
1298 int array_size = count * sizeof(struct page *);
1302 if (array_size <= PAGE_SIZE)
1303 pages = kzalloc(array_size, GFP_KERNEL);
1305 pages = vzalloc(array_size);
1309 if (attrs & DMA_ATTR_FORCE_CONTIGUOUS)
1311 unsigned long order = get_order(size);
1314 page = dma_alloc_from_contiguous(dev, count, order);
1318 __dma_clear_buffer(page, size, coherent_flag);
1320 for (i = 0; i < count; i++)
1321 pages[i] = page + i;
1326 /* Go straight to 4K chunks if caller says it's OK. */
1327 if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES)
1328 order_idx = ARRAY_SIZE(iommu_order_array) - 1;
1331 * IOMMU can map any pages, so himem can also be used here
1333 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1338 order = iommu_order_array[order_idx];
1340 /* Drop down when we get small */
1341 if (__fls(count) < order) {
1347 /* See if it's easy to allocate a high-order chunk */
1348 pages[i] = alloc_pages(gfp | __GFP_NORETRY, order);
1350 /* Go down a notch at first sign of pressure */
1356 pages[i] = alloc_pages(gfp, 0);
1362 split_page(pages[i], order);
1365 pages[i + j] = pages[i] + j;
1368 __dma_clear_buffer(pages[i], PAGE_SIZE << order, coherent_flag);
1370 count -= 1 << order;
1377 __free_pages(pages[i], 0);
1382 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1383 size_t size, unsigned long attrs)
1385 int count = size >> PAGE_SHIFT;
1388 if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
1389 dma_release_from_contiguous(dev, pages[0], count);
1391 for (i = 0; i < count; i++)
1393 __free_pages(pages[i], 0);
1401 * Create a CPU mapping for a specified pages
1404 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1407 return dma_common_pages_remap(pages, size,
1408 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
1412 * Create a mapping in device IO address space for specified pages
1415 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1417 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1418 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1419 dma_addr_t dma_addr, iova;
1422 dma_addr = __alloc_iova(mapping, size);
1423 if (dma_addr == DMA_ERROR_CODE)
1427 for (i = 0; i < count; ) {
1430 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1431 phys_addr_t phys = page_to_phys(pages[i]);
1432 unsigned int len, j;
1434 for (j = i + 1; j < count; j++, next_pfn++)
1435 if (page_to_pfn(pages[j]) != next_pfn)
1438 len = (j - i) << PAGE_SHIFT;
1439 ret = iommu_map(mapping->domain, iova, phys, len,
1440 IOMMU_READ|IOMMU_WRITE);
1448 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1449 __free_iova(mapping, dma_addr, size);
1450 return DMA_ERROR_CODE;
1453 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1455 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1458 * add optional in-page offset from iova to size and align
1459 * result to page size
1461 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1464 iommu_unmap(mapping->domain, iova, size);
1465 __free_iova(mapping, iova, size);
1469 static struct page **__atomic_get_pages(void *addr)
1474 phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr);
1475 page = phys_to_page(phys);
1477 return (struct page **)page;
1480 static struct page **__iommu_get_pages(void *cpu_addr, unsigned long attrs)
1482 struct vm_struct *area;
1484 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1485 return __atomic_get_pages(cpu_addr);
1487 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING)
1490 area = find_vm_area(cpu_addr);
1491 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1496 static void *__iommu_alloc_simple(struct device *dev, size_t size, gfp_t gfp,
1497 dma_addr_t *handle, int coherent_flag)
1502 if (coherent_flag == COHERENT)
1503 addr = __alloc_simple_buffer(dev, size, gfp, &page);
1505 addr = __alloc_from_pool(size, &page);
1509 *handle = __iommu_create_mapping(dev, &page, size);
1510 if (*handle == DMA_ERROR_CODE)
1516 __free_from_pool(addr, size);
1520 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1521 dma_addr_t handle, size_t size, int coherent_flag)
1523 __iommu_remove_mapping(dev, handle, size);
1524 if (coherent_flag == COHERENT)
1525 __dma_free_buffer(virt_to_page(cpu_addr), size);
1527 __free_from_pool(cpu_addr, size);
1530 static void *__arm_iommu_alloc_attrs(struct device *dev, size_t size,
1531 dma_addr_t *handle, gfp_t gfp, unsigned long attrs,
1534 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
1535 struct page **pages;
1538 *handle = DMA_ERROR_CODE;
1539 size = PAGE_ALIGN(size);
1541 if (coherent_flag == COHERENT || !gfpflags_allow_blocking(gfp))
1542 return __iommu_alloc_simple(dev, size, gfp, handle,
1546 * Following is a work-around (a.k.a. hack) to prevent pages
1547 * with __GFP_COMP being passed to split_page() which cannot
1548 * handle them. The real problem is that this flag probably
1549 * should be 0 on ARM as it is not supported on this
1550 * platform; see CONFIG_HUGETLBFS.
1552 gfp &= ~(__GFP_COMP);
1554 pages = __iommu_alloc_buffer(dev, size, gfp, attrs, coherent_flag);
1558 *handle = __iommu_create_mapping(dev, pages, size);
1559 if (*handle == DMA_ERROR_CODE)
1562 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING)
1565 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1566 __builtin_return_address(0));
1573 __iommu_remove_mapping(dev, *handle, size);
1575 __iommu_free_buffer(dev, pages, size, attrs);
1579 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1580 dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
1582 return __arm_iommu_alloc_attrs(dev, size, handle, gfp, attrs, NORMAL);
1585 static void *arm_coherent_iommu_alloc_attrs(struct device *dev, size_t size,
1586 dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
1588 return __arm_iommu_alloc_attrs(dev, size, handle, gfp, attrs, COHERENT);
1591 static int __arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1592 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1593 unsigned long attrs)
1595 unsigned long uaddr = vma->vm_start;
1596 unsigned long usize = vma->vm_end - vma->vm_start;
1597 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1598 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1599 unsigned long off = vma->vm_pgoff;
1604 if (off >= nr_pages || (usize >> PAGE_SHIFT) > nr_pages - off)
1610 int ret = vm_insert_page(vma, uaddr, *pages++);
1612 pr_err("Remapping memory failed: %d\n", ret);
1617 } while (usize > 0);
1621 static int arm_iommu_mmap_attrs(struct device *dev,
1622 struct vm_area_struct *vma, void *cpu_addr,
1623 dma_addr_t dma_addr, size_t size, unsigned long attrs)
1625 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1627 return __arm_iommu_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, attrs);
1630 static int arm_coherent_iommu_mmap_attrs(struct device *dev,
1631 struct vm_area_struct *vma, void *cpu_addr,
1632 dma_addr_t dma_addr, size_t size, unsigned long attrs)
1634 return __arm_iommu_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, attrs);
1638 * free a page as defined by the above mapping.
1639 * Must not be called with IRQs disabled.
1641 void __arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1642 dma_addr_t handle, unsigned long attrs, int coherent_flag)
1644 struct page **pages;
1645 size = PAGE_ALIGN(size);
1647 if (coherent_flag == COHERENT || __in_atomic_pool(cpu_addr, size)) {
1648 __iommu_free_atomic(dev, cpu_addr, handle, size, coherent_flag);
1652 pages = __iommu_get_pages(cpu_addr, attrs);
1654 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1658 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0) {
1659 dma_common_free_remap(cpu_addr, size,
1660 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
1663 __iommu_remove_mapping(dev, handle, size);
1664 __iommu_free_buffer(dev, pages, size, attrs);
1667 void arm_iommu_free_attrs(struct device *dev, size_t size,
1668 void *cpu_addr, dma_addr_t handle, unsigned long attrs)
1670 __arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, NORMAL);
1673 void arm_coherent_iommu_free_attrs(struct device *dev, size_t size,
1674 void *cpu_addr, dma_addr_t handle, unsigned long attrs)
1676 __arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, COHERENT);
1679 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1680 void *cpu_addr, dma_addr_t dma_addr,
1681 size_t size, unsigned long attrs)
1683 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1684 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1689 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1693 static int __dma_direction_to_prot(enum dma_data_direction dir)
1698 case DMA_BIDIRECTIONAL:
1699 prot = IOMMU_READ | IOMMU_WRITE;
1704 case DMA_FROM_DEVICE:
1715 * Map a part of the scatter-gather list into contiguous io address space
1717 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1718 size_t size, dma_addr_t *handle,
1719 enum dma_data_direction dir, unsigned long attrs,
1722 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1723 dma_addr_t iova, iova_base;
1726 struct scatterlist *s;
1729 size = PAGE_ALIGN(size);
1730 *handle = DMA_ERROR_CODE;
1732 iova_base = iova = __alloc_iova(mapping, size);
1733 if (iova == DMA_ERROR_CODE)
1736 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1737 phys_addr_t phys = page_to_phys(sg_page(s));
1738 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1740 if (!is_coherent && (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
1741 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1743 prot = __dma_direction_to_prot(dir);
1745 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1748 count += len >> PAGE_SHIFT;
1751 *handle = iova_base;
1755 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1756 __free_iova(mapping, iova_base, size);
1760 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1761 enum dma_data_direction dir, unsigned long attrs,
1764 struct scatterlist *s = sg, *dma = sg, *start = sg;
1766 unsigned int offset = s->offset;
1767 unsigned int size = s->offset + s->length;
1768 unsigned int max = dma_get_max_seg_size(dev);
1770 for (i = 1; i < nents; i++) {
1773 s->dma_address = DMA_ERROR_CODE;
1776 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1777 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1778 dir, attrs, is_coherent) < 0)
1781 dma->dma_address += offset;
1782 dma->dma_length = size - offset;
1784 size = offset = s->offset;
1791 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1795 dma->dma_address += offset;
1796 dma->dma_length = size - offset;
1801 for_each_sg(sg, s, count, i)
1802 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1807 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1808 * @dev: valid struct device pointer
1809 * @sg: list of buffers
1810 * @nents: number of buffers to map
1811 * @dir: DMA transfer direction
1813 * Map a set of i/o coherent buffers described by scatterlist in streaming
1814 * mode for DMA. The scatter gather list elements are merged together (if
1815 * possible) and tagged with the appropriate dma address and length. They are
1816 * obtained via sg_dma_{address,length}.
1818 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1819 int nents, enum dma_data_direction dir, unsigned long attrs)
1821 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1825 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1826 * @dev: valid struct device pointer
1827 * @sg: list of buffers
1828 * @nents: number of buffers to map
1829 * @dir: DMA transfer direction
1831 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1832 * The scatter gather list elements are merged together (if possible) and
1833 * tagged with the appropriate dma address and length. They are obtained via
1834 * sg_dma_{address,length}.
1836 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1837 int nents, enum dma_data_direction dir, unsigned long attrs)
1839 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1842 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1843 int nents, enum dma_data_direction dir,
1844 unsigned long attrs, bool is_coherent)
1846 struct scatterlist *s;
1849 for_each_sg(sg, s, nents, i) {
1851 __iommu_remove_mapping(dev, sg_dma_address(s),
1853 if (!is_coherent && (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
1854 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1860 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1861 * @dev: valid struct device pointer
1862 * @sg: list of buffers
1863 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1864 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1866 * Unmap a set of streaming mode DMA translations. Again, CPU access
1867 * rules concerning calls here are the same as for dma_unmap_single().
1869 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1870 int nents, enum dma_data_direction dir,
1871 unsigned long attrs)
1873 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1877 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1878 * @dev: valid struct device pointer
1879 * @sg: list of buffers
1880 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1881 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1883 * Unmap a set of streaming mode DMA translations. Again, CPU access
1884 * rules concerning calls here are the same as for dma_unmap_single().
1886 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1887 enum dma_data_direction dir,
1888 unsigned long attrs)
1890 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1894 * arm_iommu_sync_sg_for_cpu
1895 * @dev: valid struct device pointer
1896 * @sg: list of buffers
1897 * @nents: number of buffers to map (returned from dma_map_sg)
1898 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1900 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1901 int nents, enum dma_data_direction dir)
1903 struct scatterlist *s;
1906 for_each_sg(sg, s, nents, i)
1907 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1912 * arm_iommu_sync_sg_for_device
1913 * @dev: valid struct device pointer
1914 * @sg: list of buffers
1915 * @nents: number of buffers to map (returned from dma_map_sg)
1916 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1918 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1919 int nents, enum dma_data_direction dir)
1921 struct scatterlist *s;
1924 for_each_sg(sg, s, nents, i)
1925 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1930 * arm_coherent_iommu_map_page
1931 * @dev: valid struct device pointer
1932 * @page: page that buffer resides in
1933 * @offset: offset into page for start of buffer
1934 * @size: size of buffer to map
1935 * @dir: DMA transfer direction
1937 * Coherent IOMMU aware version of arm_dma_map_page()
1939 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1940 unsigned long offset, size_t size, enum dma_data_direction dir,
1941 unsigned long attrs)
1943 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1944 dma_addr_t dma_addr;
1945 int ret, prot, len = PAGE_ALIGN(size + offset);
1947 dma_addr = __alloc_iova(mapping, len);
1948 if (dma_addr == DMA_ERROR_CODE)
1951 prot = __dma_direction_to_prot(dir);
1953 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1957 return dma_addr + offset;
1959 __free_iova(mapping, dma_addr, len);
1960 return DMA_ERROR_CODE;
1964 * arm_iommu_map_page
1965 * @dev: valid struct device pointer
1966 * @page: page that buffer resides in
1967 * @offset: offset into page for start of buffer
1968 * @size: size of buffer to map
1969 * @dir: DMA transfer direction
1971 * IOMMU aware version of arm_dma_map_page()
1973 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1974 unsigned long offset, size_t size, enum dma_data_direction dir,
1975 unsigned long attrs)
1977 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
1978 __dma_page_cpu_to_dev(page, offset, size, dir);
1980 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1984 * arm_coherent_iommu_unmap_page
1985 * @dev: valid struct device pointer
1986 * @handle: DMA address of buffer
1987 * @size: size of buffer (same as passed to dma_map_page)
1988 * @dir: DMA transfer direction (same as passed to dma_map_page)
1990 * Coherent IOMMU aware version of arm_dma_unmap_page()
1992 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1993 size_t size, enum dma_data_direction dir, unsigned long attrs)
1995 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1996 dma_addr_t iova = handle & PAGE_MASK;
1997 int offset = handle & ~PAGE_MASK;
1998 int len = PAGE_ALIGN(size + offset);
2003 iommu_unmap(mapping->domain, iova, len);
2004 __free_iova(mapping, iova, len);
2008 * arm_iommu_unmap_page
2009 * @dev: valid struct device pointer
2010 * @handle: DMA address of buffer
2011 * @size: size of buffer (same as passed to dma_map_page)
2012 * @dir: DMA transfer direction (same as passed to dma_map_page)
2014 * IOMMU aware version of arm_dma_unmap_page()
2016 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
2017 size_t size, enum dma_data_direction dir, unsigned long attrs)
2019 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2020 dma_addr_t iova = handle & PAGE_MASK;
2021 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
2022 int offset = handle & ~PAGE_MASK;
2023 int len = PAGE_ALIGN(size + offset);
2028 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
2029 __dma_page_dev_to_cpu(page, offset, size, dir);
2031 iommu_unmap(mapping->domain, iova, len);
2032 __free_iova(mapping, iova, len);
2036 * arm_iommu_map_resource - map a device resource for DMA
2037 * @dev: valid struct device pointer
2038 * @phys_addr: physical address of resource
2039 * @size: size of resource to map
2040 * @dir: DMA transfer direction
2042 static dma_addr_t arm_iommu_map_resource(struct device *dev,
2043 phys_addr_t phys_addr, size_t size,
2044 enum dma_data_direction dir, unsigned long attrs)
2046 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2047 dma_addr_t dma_addr;
2049 phys_addr_t addr = phys_addr & PAGE_MASK;
2050 unsigned int offset = phys_addr & ~PAGE_MASK;
2051 size_t len = PAGE_ALIGN(size + offset);
2053 dma_addr = __alloc_iova(mapping, len);
2054 if (dma_addr == DMA_ERROR_CODE)
2057 prot = __dma_direction_to_prot(dir) | IOMMU_MMIO;
2059 ret = iommu_map(mapping->domain, dma_addr, addr, len, prot);
2063 return dma_addr + offset;
2065 __free_iova(mapping, dma_addr, len);
2066 return DMA_ERROR_CODE;
2070 * arm_iommu_unmap_resource - unmap a device DMA resource
2071 * @dev: valid struct device pointer
2072 * @dma_handle: DMA address to resource
2073 * @size: size of resource to map
2074 * @dir: DMA transfer direction
2076 static void arm_iommu_unmap_resource(struct device *dev, dma_addr_t dma_handle,
2077 size_t size, enum dma_data_direction dir,
2078 unsigned long attrs)
2080 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2081 dma_addr_t iova = dma_handle & PAGE_MASK;
2082 unsigned int offset = dma_handle & ~PAGE_MASK;
2083 size_t len = PAGE_ALIGN(size + offset);
2088 iommu_unmap(mapping->domain, iova, len);
2089 __free_iova(mapping, iova, len);
2092 static void arm_iommu_sync_single_for_cpu(struct device *dev,
2093 dma_addr_t handle, size_t size, enum dma_data_direction dir)
2095 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2096 dma_addr_t iova = handle & PAGE_MASK;
2097 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
2098 unsigned int offset = handle & ~PAGE_MASK;
2103 __dma_page_dev_to_cpu(page, offset, size, dir);
2106 static void arm_iommu_sync_single_for_device(struct device *dev,
2107 dma_addr_t handle, size_t size, enum dma_data_direction dir)
2109 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2110 dma_addr_t iova = handle & PAGE_MASK;
2111 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
2112 unsigned int offset = handle & ~PAGE_MASK;
2117 __dma_page_cpu_to_dev(page, offset, size, dir);
2120 struct dma_map_ops iommu_ops = {
2121 .alloc = arm_iommu_alloc_attrs,
2122 .free = arm_iommu_free_attrs,
2123 .mmap = arm_iommu_mmap_attrs,
2124 .get_sgtable = arm_iommu_get_sgtable,
2126 .map_page = arm_iommu_map_page,
2127 .unmap_page = arm_iommu_unmap_page,
2128 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
2129 .sync_single_for_device = arm_iommu_sync_single_for_device,
2131 .map_sg = arm_iommu_map_sg,
2132 .unmap_sg = arm_iommu_unmap_sg,
2133 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
2134 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
2136 .map_resource = arm_iommu_map_resource,
2137 .unmap_resource = arm_iommu_unmap_resource,
2140 struct dma_map_ops iommu_coherent_ops = {
2141 .alloc = arm_coherent_iommu_alloc_attrs,
2142 .free = arm_coherent_iommu_free_attrs,
2143 .mmap = arm_coherent_iommu_mmap_attrs,
2144 .get_sgtable = arm_iommu_get_sgtable,
2146 .map_page = arm_coherent_iommu_map_page,
2147 .unmap_page = arm_coherent_iommu_unmap_page,
2149 .map_sg = arm_coherent_iommu_map_sg,
2150 .unmap_sg = arm_coherent_iommu_unmap_sg,
2152 .map_resource = arm_iommu_map_resource,
2153 .unmap_resource = arm_iommu_unmap_resource,
2157 * arm_iommu_create_mapping
2158 * @bus: pointer to the bus holding the client device (for IOMMU calls)
2159 * @base: start address of the valid IO address space
2160 * @size: maximum size of the valid IO address space
2162 * Creates a mapping structure which holds information about used/unused
2163 * IO address ranges, which is required to perform memory allocation and
2164 * mapping with IOMMU aware functions.
2166 * The client device need to be attached to the mapping with
2167 * arm_iommu_attach_device function.
2169 struct dma_iommu_mapping *
2170 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size)
2172 unsigned int bits = size >> PAGE_SHIFT;
2173 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
2174 struct dma_iommu_mapping *mapping;
2178 /* currently only 32-bit DMA address space is supported */
2179 if (size > DMA_BIT_MASK(32) + 1)
2180 return ERR_PTR(-ERANGE);
2183 return ERR_PTR(-EINVAL);
2185 if (bitmap_size > PAGE_SIZE) {
2186 extensions = bitmap_size / PAGE_SIZE;
2187 bitmap_size = PAGE_SIZE;
2190 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
2194 mapping->bitmap_size = bitmap_size;
2195 mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *),
2197 if (!mapping->bitmaps)
2200 mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL);
2201 if (!mapping->bitmaps[0])
2204 mapping->nr_bitmaps = 1;
2205 mapping->extensions = extensions;
2206 mapping->base = base;
2207 mapping->bits = BITS_PER_BYTE * bitmap_size;
2209 spin_lock_init(&mapping->lock);
2211 mapping->domain = iommu_domain_alloc(bus);
2212 if (!mapping->domain)
2215 kref_init(&mapping->kref);
2218 kfree(mapping->bitmaps[0]);
2220 kfree(mapping->bitmaps);
2224 return ERR_PTR(err);
2226 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
2228 static void release_iommu_mapping(struct kref *kref)
2231 struct dma_iommu_mapping *mapping =
2232 container_of(kref, struct dma_iommu_mapping, kref);
2234 iommu_domain_free(mapping->domain);
2235 for (i = 0; i < mapping->nr_bitmaps; i++)
2236 kfree(mapping->bitmaps[i]);
2237 kfree(mapping->bitmaps);
2241 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
2245 if (mapping->nr_bitmaps >= mapping->extensions)
2248 next_bitmap = mapping->nr_bitmaps;
2249 mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size,
2251 if (!mapping->bitmaps[next_bitmap])
2254 mapping->nr_bitmaps++;
2259 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
2262 kref_put(&mapping->kref, release_iommu_mapping);
2264 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
2266 static int __arm_iommu_attach_device(struct device *dev,
2267 struct dma_iommu_mapping *mapping)
2271 err = iommu_attach_device(mapping->domain, dev);
2275 kref_get(&mapping->kref);
2276 to_dma_iommu_mapping(dev) = mapping;
2278 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
2283 * arm_iommu_attach_device
2284 * @dev: valid struct device pointer
2285 * @mapping: io address space mapping structure (returned from
2286 * arm_iommu_create_mapping)
2288 * Attaches specified io address space mapping to the provided device.
2289 * This replaces the dma operations (dma_map_ops pointer) with the
2290 * IOMMU aware version.
2292 * More than one client might be attached to the same io address space
2295 int arm_iommu_attach_device(struct device *dev,
2296 struct dma_iommu_mapping *mapping)
2300 err = __arm_iommu_attach_device(dev, mapping);
2304 set_dma_ops(dev, &iommu_ops);
2307 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
2309 static void __arm_iommu_detach_device(struct device *dev)
2311 struct dma_iommu_mapping *mapping;
2313 mapping = to_dma_iommu_mapping(dev);
2315 dev_warn(dev, "Not attached\n");
2319 iommu_detach_device(mapping->domain, dev);
2320 kref_put(&mapping->kref, release_iommu_mapping);
2321 to_dma_iommu_mapping(dev) = NULL;
2323 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
2327 * arm_iommu_detach_device
2328 * @dev: valid struct device pointer
2330 * Detaches the provided device from a previously attached map.
2331 * This voids the dma operations (dma_map_ops pointer)
2333 void arm_iommu_detach_device(struct device *dev)
2335 __arm_iommu_detach_device(dev);
2336 set_dma_ops(dev, NULL);
2338 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
2340 static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent)
2342 return coherent ? &iommu_coherent_ops : &iommu_ops;
2345 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2346 const struct iommu_ops *iommu)
2348 struct dma_iommu_mapping *mapping;
2353 mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
2354 if (IS_ERR(mapping)) {
2355 pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n",
2356 size, dev_name(dev));
2360 if (__arm_iommu_attach_device(dev, mapping)) {
2361 pr_warn("Failed to attached device %s to IOMMU_mapping\n",
2363 arm_iommu_release_mapping(mapping);
2370 static void arm_teardown_iommu_dma_ops(struct device *dev)
2372 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2377 __arm_iommu_detach_device(dev);
2378 arm_iommu_release_mapping(mapping);
2383 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2384 const struct iommu_ops *iommu)
2389 static void arm_teardown_iommu_dma_ops(struct device *dev) { }
2391 #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops
2393 #endif /* CONFIG_ARM_DMA_USE_IOMMU */
2395 static struct dma_map_ops *arm_get_dma_map_ops(bool coherent)
2397 return coherent ? &arm_coherent_dma_ops : &arm_dma_ops;
2400 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
2401 const struct iommu_ops *iommu, bool coherent)
2403 struct dma_map_ops *dma_ops;
2405 dev->archdata.dma_coherent = coherent;
2406 if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu))
2407 dma_ops = arm_get_iommu_dma_map_ops(coherent);
2409 dma_ops = arm_get_dma_map_ops(coherent);
2411 set_dma_ops(dev, dma_ops);
2414 void arch_teardown_dma_ops(struct device *dev)
2416 arm_teardown_iommu_dma_ops(dev);