arch/arm/mm/proc-v7-bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/arm-smccc.h>
   3 #include <linux/kernel.h>
   4 #include <linux/psci.h>
   5 #include <linux/smp.h>
   6
   7 #include <asm/cp15.h>
   8 #include <asm/cputype.h>
   9 #include <asm/proc-fns.h>
  10 #include <asm/spectre.h>
  11 #include <asm/system_misc.h>
  12
  13 #ifdef CONFIG_ARM_PSCI
  14 #define SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED    1
  15 static int __maybe_unused spectre_v2_get_cpu_fw_mitigation_state(void)
  16 {
  17         struct arm_smccc_res res;
  18
  19         arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
  20                              ARM_SMCCC_ARCH_WORKAROUND_1, &res);
  21
  22         switch ((int)res.a0) {
  23         case SMCCC_RET_SUCCESS:
  24                 return SPECTRE_MITIGATED;
  25
  26         case SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED:
  27                 return SPECTRE_UNAFFECTED;
  28
  29         default:
  30                 return SPECTRE_VULNERABLE;
  31         }
  32 }
  33 #else
  34 static int __maybe_unused spectre_v2_get_cpu_fw_mitigation_state(void)
  35 {
  36         return SPECTRE_VULNERABLE;
  37 }
  38 #endif
  39
  40 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
  41 DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn);
  42
  43 extern void cpu_v7_iciallu_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
  44 extern void cpu_v7_bpiall_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
  45 extern void cpu_v7_smc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
  46 extern void cpu_v7_hvc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
  47
  48 static void harden_branch_predictor_bpiall(void)
  49 {
  50         write_sysreg(0, BPIALL);
  51 }
  52
  53 static void harden_branch_predictor_iciallu(void)
  54 {
  55         write_sysreg(0, ICIALLU);
  56 }
  57
  58 static void __maybe_unused call_smc_arch_workaround_1(void)
  59 {
  60         arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
  61 }
  62
  63 static void __maybe_unused call_hvc_arch_workaround_1(void)
  64 {
  65         arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
  66 }
  67
  68 static unsigned int spectre_v2_install_workaround(unsigned int method)
  69 {
  70         const char *spectre_v2_method = NULL;
  71         int cpu = smp_processor_id();
  72
  73         if (per_cpu(harden_branch_predictor_fn, cpu))
  74                 return SPECTRE_MITIGATED;
  75
  76         switch (method) {
  77         case SPECTRE_V2_METHOD_BPIALL:
  78                 per_cpu(harden_branch_predictor_fn, cpu) =
  79                         harden_branch_predictor_bpiall;
  80                 spectre_v2_method = "BPIALL";
  81                 break;
  82
  83         case SPECTRE_V2_METHOD_ICIALLU:
  84                 per_cpu(harden_branch_predictor_fn, cpu) =
  85                         harden_branch_predictor_iciallu;
  86                 spectre_v2_method = "ICIALLU";
  87                 break;
  88
  89         case SPECTRE_V2_METHOD_HVC:
  90                 per_cpu(harden_branch_predictor_fn, cpu) =
  91                         call_hvc_arch_workaround_1;
  92                 cpu_do_switch_mm = cpu_v7_hvc_switch_mm;
  93                 spectre_v2_method = "hypervisor";
  94                 break;
  95
  96         case SPECTRE_V2_METHOD_SMC:
  97                 per_cpu(harden_branch_predictor_fn, cpu) =
  98                         call_smc_arch_workaround_1;
  99                 cpu_do_switch_mm = cpu_v7_smc_switch_mm;
 100                 spectre_v2_method = "firmware";
 101                 break;
 102         }
 103
 104         if (spectre_v2_method)
 105                 pr_info("CPU%u: Spectre v2: using %s workaround\n",
 106                         smp_processor_id(), spectre_v2_method);
 107
 108         return SPECTRE_MITIGATED;
 109 }
 110 #else
 111 static unsigned int spectre_v2_install_workaround(unsigned int method)
 112 {
 113         pr_info("CPU%u: Spectre V2: workarounds disabled by configuration\n",
 114                 smp_processor_id());
 115
 116         return SPECTRE_VULNERABLE;
 117 }
 118 #endif
 119
 120 static void cpu_v7_spectre_v2_init(void)
 121 {
 122         unsigned int state, method = 0;
 123
 124         switch (read_cpuid_part()) {
 125         case ARM_CPU_PART_CORTEX_A8:
 126         case ARM_CPU_PART_CORTEX_A9:
 127         case ARM_CPU_PART_CORTEX_A12:
 128         case ARM_CPU_PART_CORTEX_A17:
 129         case ARM_CPU_PART_CORTEX_A73:
 130         case ARM_CPU_PART_CORTEX_A75:
 131                 state = SPECTRE_MITIGATED;
 132                 method = SPECTRE_V2_METHOD_BPIALL;
 133                 break;
 134
 135         case ARM_CPU_PART_CORTEX_A15:
 136         case ARM_CPU_PART_BRAHMA_B15:
 137                 state = SPECTRE_MITIGATED;
 138                 method = SPECTRE_V2_METHOD_ICIALLU;
 139                 break;
 140
 141         default:
 142                 /* Other ARM CPUs require no workaround */
 143                 if (read_cpuid_implementor() == ARM_CPU_IMP_ARM) {
 144                         state = SPECTRE_UNAFFECTED;
 145                         break;
 146                 }
 147                 /* fallthrough */
 148         /* Cortex A57/A72 require firmware workaround */
 149         case ARM_CPU_PART_CORTEX_A57:
 150         case ARM_CPU_PART_CORTEX_A72: {
 151                 struct arm_smccc_res res;
 152
 153                 state = spectre_v2_get_cpu_fw_mitigation_state();
 154                 if (state != SPECTRE_MITIGATED)
 155                         break;
 156
 157                 if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
 158                         break;
 159
 160                 switch (psci_ops.conduit) {
 161                 case PSCI_CONDUIT_HVC:
 162                         arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 163                                           ARM_SMCCC_ARCH_WORKAROUND_1, &res);
 164                         if ((int)res.a0 != 0)
 165                                 break;
 166                         method = SPECTRE_V2_METHOD_HVC;
 167                         break;
 168
 169                 case PSCI_CONDUIT_SMC:
 170                         arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 171                                           ARM_SMCCC_ARCH_WORKAROUND_1, &res);
 172                         if ((int)res.a0 != 0)
 173                                 break;
 174                         method = SPECTRE_V2_METHOD_SMC;
 175                         break;
 176
 177                 default:
 178                         state = SPECTRE_VULNERABLE;
 179                         break;
 180                 }
 181         }
 182         }
 183
 184         if (state == SPECTRE_MITIGATED)
 185                 state = spectre_v2_install_workaround(method);
 186
 187         spectre_v2_update_state(state, method);
 188 }
 189
 190 #ifdef CONFIG_HARDEN_BRANCH_HISTORY
 191 static int spectre_bhb_method;
 192
 193 static const char *spectre_bhb_method_name(int method)
 194 {
 195         switch (method) {
 196         case SPECTRE_V2_METHOD_LOOP8:
 197                 return "loop";
 198
 199         case SPECTRE_V2_METHOD_BPIALL:
 200                 return "BPIALL";
 201
 202         default:
 203                 return "unknown";
 204         }
 205 }
 206
 207 static int spectre_bhb_install_workaround(int method)
 208 {
 209         if (spectre_bhb_method != method) {
 210                 if (spectre_bhb_method) {
 211                         pr_err("CPU%u: Spectre BHB: method disagreement, system vulnerable\n",
 212                                smp_processor_id());
 213
 214                         return SPECTRE_VULNERABLE;
 215                 }
 216
 217                 if (spectre_bhb_update_vectors(method) == SPECTRE_VULNERABLE)
 218                         return SPECTRE_VULNERABLE;
 219
 220                 spectre_bhb_method = method;
 221         }
 222
 223         pr_info("CPU%u: Spectre BHB: using %s workaround\n",
 224                 smp_processor_id(), spectre_bhb_method_name(method));
 225
 226         return SPECTRE_MITIGATED;
 227 }
 228 #else
 229 static int spectre_bhb_install_workaround(int method)
 230 {
 231         return SPECTRE_VULNERABLE;
 232 }
 233 #endif
 234
 235 static void cpu_v7_spectre_bhb_init(void)
 236 {
 237         unsigned int state, method = 0;
 238
 239         switch (read_cpuid_part()) {
 240         case ARM_CPU_PART_CORTEX_A15:
 241         case ARM_CPU_PART_BRAHMA_B15:
 242         case ARM_CPU_PART_CORTEX_A57:
 243         case ARM_CPU_PART_CORTEX_A72:
 244                 state = SPECTRE_MITIGATED;
 245                 method = SPECTRE_V2_METHOD_LOOP8;
 246                 break;
 247
 248         case ARM_CPU_PART_CORTEX_A73:
 249         case ARM_CPU_PART_CORTEX_A75:
 250                 state = SPECTRE_MITIGATED;
 251                 method = SPECTRE_V2_METHOD_BPIALL;
 252                 break;
 253
 254         default:
 255                 state = SPECTRE_UNAFFECTED;
 256                 break;
 257         }
 258
 259         if (state == SPECTRE_MITIGATED)
 260                 state = spectre_bhb_install_workaround(method);
 261
 262         spectre_v2_update_state(state, method);
 263 }
 264
 265 static __maybe_unused bool cpu_v7_check_auxcr_set(bool *warned,
 266                                                   u32 mask, const char *msg)
 267 {
 268         u32 aux_cr;
 269
 270         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (aux_cr));
 271
 272         if ((aux_cr & mask) != mask) {
 273                 if (!*warned)
 274                         pr_err("CPU%u: %s", smp_processor_id(), msg);
 275                 *warned = true;
 276                 return false;
 277         }
 278         return true;
 279 }
 280
 281 static DEFINE_PER_CPU(bool, spectre_warned);
 282
 283 static bool check_spectre_auxcr(bool *warned, u32 bit)
 284 {
 285         return IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR) &&
 286                 cpu_v7_check_auxcr_set(warned, bit,
 287                                        "Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable\n");
 288 }
 289
 290 void cpu_v7_ca8_ibe(void)
 291 {
 292         if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6)))
 293                 cpu_v7_spectre_v2_init();
 294 }
 295
 296 void cpu_v7_ca15_ibe(void)
 297 {
 298         if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0)))
 299                 cpu_v7_spectre_v2_init();
 300 }
 301
 302 void cpu_v7_bugs_init(void)
 303 {
 304         cpu_v7_spectre_v2_init();
 305         cpu_v7_spectre_bhb_init();
 306 }