GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / mm / proc-v7m.S
1 /*
2  *  linux/arch/arm/mm/proc-v7m.S
3  *
4  *  Copyright (C) 2008 ARM Ltd.
5  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  *  This is the "shell" of the ARMv7-M processor support.
12  */
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/memory.h>
16 #include <asm/v7m.h>
17 #include "proc-macros.S"
18
19 ENTRY(cpu_v7m_proc_init)
20         ret     lr
21 ENDPROC(cpu_v7m_proc_init)
22
23 ENTRY(cpu_v7m_proc_fin)
24         ret     lr
25 ENDPROC(cpu_v7m_proc_fin)
26
27 /*
28  *      cpu_v7m_reset(loc)
29  *
30  *      Perform a soft reset of the system.  Put the CPU into the
31  *      same state as it would be if it had been reset, and branch
32  *      to what would be the reset vector.
33  *
34  *      - loc   - location to jump to for soft reset
35  */
36         .align  5
37 ENTRY(cpu_v7m_reset)
38         ret     r0
39 ENDPROC(cpu_v7m_reset)
40
41 /*
42  *      cpu_v7m_do_idle()
43  *
44  *      Idle the processor (eg, wait for interrupt).
45  *
46  *      IRQs are already disabled.
47  */
48 ENTRY(cpu_v7m_do_idle)
49         wfi
50         ret     lr
51 ENDPROC(cpu_v7m_do_idle)
52
53 ENTRY(cpu_v7m_dcache_clean_area)
54         ret     lr
55 ENDPROC(cpu_v7m_dcache_clean_area)
56
57 /*
58  * There is no MMU, so here is nothing to do.
59  */
60 ENTRY(cpu_v7m_switch_mm)
61         ret     lr
62 ENDPROC(cpu_v7m_switch_mm)
63
64 .globl  cpu_v7m_suspend_size
65 .equ    cpu_v7m_suspend_size, 0
66
67 #ifdef CONFIG_ARM_CPU_SUSPEND
68 ENTRY(cpu_v7m_do_suspend)
69         ret     lr
70 ENDPROC(cpu_v7m_do_suspend)
71
72 ENTRY(cpu_v7m_do_resume)
73         ret     lr
74 ENDPROC(cpu_v7m_do_resume)
75 #endif
76
77 ENTRY(cpu_cm7_dcache_clean_area)
78         dcache_line_size r2, r3
79         movw    r3, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
80         movt    r3, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
81
82 1:      str     r0, [r3]                @ clean D entry
83         add     r0, r0, r2
84         subs    r1, r1, r2
85         bhi     1b
86         dsb
87         ret     lr
88 ENDPROC(cpu_cm7_dcache_clean_area)
89
90 ENTRY(cpu_cm7_proc_fin)
91         movw    r2, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
92         movt    r2, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
93         ldr     r0, [r2]
94         bic     r0, r0, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC)
95         str     r0, [r2]
96         ret     lr
97 ENDPROC(cpu_cm7_proc_fin)
98
99         .section ".init.text", #alloc, #execinstr
100
101 __v7m_cm7_setup:
102         mov     r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP)
103         b       __v7m_setup_cont
104 /*
105  *      __v7m_setup
106  *
107  *      This should be able to cover all ARMv7-M cores.
108  */
109 __v7m_setup:
110         mov     r8, 0
111
112 __v7m_setup_cont:
113         @ Configure the vector table base address
114         ldr     r0, =BASEADDR_V7M_SCB
115         ldr     r12, =vector_table
116         str     r12, [r0, V7M_SCB_VTOR]
117
118         @ enable UsageFault, BusFault and MemManage fault.
119         ldr     r5, [r0, #V7M_SCB_SHCSR]
120         orr     r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
121         str     r5, [r0, #V7M_SCB_SHCSR]
122
123         @ Lower the priority of the SVC and PendSV exceptions
124         mov     r5, #0x80000000
125         str     r5, [r0, V7M_SCB_SHPR2] @ set SVC priority
126         mov     r5, #0x00800000
127         str     r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority
128
129         @ SVC to switch to handler mode. Notice that this requires sp to
130         @ point to writeable memory because the processor saves
131         @ some registers to the stack.
132         badr    r1, 1f
133         ldr     r5, [r12, #11 * 4]      @ read the SVC vector entry
134         str     r1, [r12, #11 * 4]      @ write the temporary SVC vector entry
135         dsb
136         mov     r6, lr                  @ save LR
137         ldr     sp, =init_thread_union + THREAD_START_SP
138         cpsie   i
139         svc     #0
140 1:      cpsid   i
141         /* Calculate exc_ret */
142         orr     r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
143         ldmia   sp, {r0-r3, r12}
144         str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
145         mov     lr, r6                  @ restore LR
146
147         @ Special-purpose control register
148         mov     r1, #1
149         msr     control, r1             @ Thread mode has unpriviledged access
150
151         @ Configure caches (if implemented)
152         teq     r8, #0
153         stmneia sp, {r0-r6, lr}         @ v7m_invalidate_l1 touches r0-r6
154         blne    v7m_invalidate_l1
155         teq     r8, #0                  @ re-evalutae condition
156         ldmneia sp, {r0-r6, lr}
157
158         @ Configure the System Control Register to ensure 8-byte stack alignment
159         @ Note the STKALIGN bit is either RW or RAO.
160         ldr     r0, [r0, V7M_SCB_CCR]   @ system control register
161         orr     r0, #V7M_SCB_CCR_STKALIGN
162         orr     r0, r0, r8
163
164         ret     lr
165 ENDPROC(__v7m_setup)
166
167 /*
168  * Cortex-M7 processor functions
169  */
170         globl_equ       cpu_cm7_proc_init,      cpu_v7m_proc_init
171         globl_equ       cpu_cm7_reset,          cpu_v7m_reset
172         globl_equ       cpu_cm7_do_idle,        cpu_v7m_do_idle
173         globl_equ       cpu_cm7_switch_mm,      cpu_v7m_switch_mm
174
175         define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
176         define_processor_functions cm7, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
177
178         .section ".rodata"
179         string cpu_arch_name, "armv7m"
180         string cpu_elf_name "v7m"
181         string cpu_v7m_name "ARMv7-M"
182
183         .section ".proc.info.init", #alloc
184
185 .macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0,  proc_fns = v7m_processor_functions
186         .long   0                       /* proc_info_list.__cpu_mm_mmu_flags */
187         .long   0                       /* proc_info_list.__cpu_io_mmu_flags */
188         initfn  \initfunc, \name
189         .long   cpu_arch_name
190         .long   cpu_elf_name
191         .long   HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \hwcaps
192         .long   cpu_v7m_name
193         .long   \proc_fns
194         .long   0                       /* proc_info_list.tlb */
195         .long   0                       /* proc_info_list.user */
196         .long   \cache_fns
197 .endm
198
199         /*
200          * Match ARM Cortex-M7 processor.
201          */
202         .type   __v7m_cm7_proc_info, #object
203 __v7m_cm7_proc_info:
204         .long   0x410fc270              /* ARM Cortex-M7 0xC27 */
205         .long   0xff0ffff0              /* Mask off revision, patch release */
206         __v7m_proc __v7m_cm7_proc_info, __v7m_cm7_setup, hwcaps = HWCAP_EDSP, cache_fns = v7m_cache_fns, proc_fns = cm7_processor_functions
207         .size   __v7m_cm7_proc_info, . - __v7m_cm7_proc_info
208
209         /*
210          * Match ARM Cortex-M4 processor.
211          */
212         .type   __v7m_cm4_proc_info, #object
213 __v7m_cm4_proc_info:
214         .long   0x410fc240              /* ARM Cortex-M4 0xC24 */
215         .long   0xff0ffff0              /* Mask off revision, patch release */
216         __v7m_proc __v7m_cm4_proc_info, __v7m_setup, hwcaps = HWCAP_EDSP
217         .size   __v7m_cm4_proc_info, . - __v7m_cm4_proc_info
218
219         /*
220          * Match ARM Cortex-M3 processor.
221          */
222         .type   __v7m_cm3_proc_info, #object
223 __v7m_cm3_proc_info:
224         .long   0x410fc230              /* ARM Cortex-M3 0xC23 */
225         .long   0xff0ffff0              /* Mask off revision, patch release */
226         __v7m_proc __v7m_cm3_proc_info, __v7m_setup
227         .size   __v7m_cm3_proc_info, . - __v7m_cm3_proc_info
228
229         /*
230          * Match any ARMv7-M processor core.
231          */
232         .type   __v7m_proc_info, #object
233 __v7m_proc_info:
234         .long   0x000f0000              @ Required ID value
235         .long   0x000f0000              @ Mask for ID
236         __v7m_proc __v7m_proc_info, __v7m_setup
237         .size   __v7m_proc_info, . - __v7m_proc_info
238