arch/arm64/boot/dts/amlogic/meson-axg.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/axg-audio-clkc.h>
  10 #include <dt-bindings/clock/axg-clkc.h>
  11 #include <dt-bindings/clock/axg-aoclkc.h>
  12 #include <dt-bindings/gpio/meson-axg-gpio.h>
  13 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
  14
  15 / {
  16         compatible = "amlogic,meson-axg";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         reserved-memory {
  23                 #address-cells = <2>;
  24                 #size-cells = <2>;
  25                 ranges;
  26
  27                 /* 16 MiB reserved for Hardware ROM Firmware */
  28                 hwrom_reserved: hwrom@0 {
  29                         reg = <0x0 0x0 0x0 0x1000000>;
  30                         no-map;
  31                 };
  32
  33                 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
  34                 secmon_reserved: secmon@5000000 {
  35                         reg = <0x0 0x05000000 0x0 0x300000>;
  36                         no-map;
  37                 };
  38         };
  39
  40         cpus {
  41                 #address-cells = <0x2>;
  42                 #size-cells = <0x0>;
  43
  44                 cpu0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a53", "arm,armv8";
  47                         reg = <0x0 0x0>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&l2>;
  50                         clocks = <&scpi_dvfs 0>;
  51                 };
  52
  53                 cpu1: cpu@1 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a53", "arm,armv8";
  56                         reg = <0x0 0x1>;
  57                         enable-method = "psci";
  58                         next-level-cache = <&l2>;
  59                         clocks = <&scpi_dvfs 0>;
  60                 };
  61
  62                 cpu2: cpu@2 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53", "arm,armv8";
  65                         reg = <0x0 0x2>;
  66                         enable-method = "psci";
  67                         next-level-cache = <&l2>;
  68                         clocks = <&scpi_dvfs 0>;
  69                 };
  70
  71                 cpu3: cpu@3 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53", "arm,armv8";
  74                         reg = <0x0 0x3>;
  75                         enable-method = "psci";
  76                         next-level-cache = <&l2>;
  77                         clocks = <&scpi_dvfs 0>;
  78                 };
  79
  80                 l2: l2-cache0 {
  81                         compatible = "cache";
  82                 };
  83         };
  84
  85         arm-pmu {
  86                 compatible = "arm,cortex-a53-pmu";
  87                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  88                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  89                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  90                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  91                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  92         };
  93
  94         psci {
  95                 compatible = "arm,psci-1.0";
  96                 method = "smc";
  97         };
  98
  99         tdmif_a: audio-controller@0 {
 100                 compatible = "amlogic,axg-tdm-iface";
 101                 #sound-dai-cells = <0>;
 102                 sound-name-prefix = "TDM_A";
 103                 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
 104                          <&clkc_audio AUD_CLKID_MST_A_SCLK>,
 105                          <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
 106                 clock-names = "mclk", "sclk", "lrclk";
 107                 status = "disabled";
 108         };
 109
 110         tdmif_b: audio-controller@1 {
 111                 compatible = "amlogic,axg-tdm-iface";
 112                 #sound-dai-cells = <0>;
 113                 sound-name-prefix = "TDM_B";
 114                 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
 115                          <&clkc_audio AUD_CLKID_MST_B_SCLK>,
 116                          <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
 117                 clock-names = "mclk", "sclk", "lrclk";
 118                 status = "disabled";
 119         };
 120
 121         tdmif_c: audio-controller@2 {
 122                 compatible = "amlogic,axg-tdm-iface";
 123                 #sound-dai-cells = <0>;
 124                 sound-name-prefix = "TDM_C";
 125                 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
 126                          <&clkc_audio AUD_CLKID_MST_C_SCLK>,
 127                          <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
 128                 clock-names = "mclk", "sclk", "lrclk";
 129                 status = "disabled";
 130         };
 131
 132         timer {
 133                 compatible = "arm,armv8-timer";
 134                 interrupts = <GIC_PPI 13
 135                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 136                              <GIC_PPI 14
 137                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 138                              <GIC_PPI 11
 139                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 140                              <GIC_PPI 10
 141                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 142         };
 143
 144         xtal: xtal-clk {
 145                 compatible = "fixed-clock";
 146                 clock-frequency = <24000000>;
 147                 clock-output-names = "xtal";
 148                 #clock-cells = <0>;
 149         };
 150
 151         ao_alt_xtal: ao_alt_xtal-clk {
 152                 compatible = "fixed-clock";
 153                 clock-frequency = <32000000>;
 154                 clock-output-names = "ao_alt_xtal";
 155                 #clock-cells = <0>;
 156         };
 157
 158         scpi {
 159                 compatible = "arm,scpi-pre-1.0";
 160                 mboxes = <&mailbox 1 &mailbox 2>;
 161                 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
 162
 163                 scpi_clocks: clocks {
 164                         compatible = "arm,scpi-clocks";
 165
 166                         scpi_dvfs: clocks-0 {
 167                                 compatible = "arm,scpi-dvfs-clocks";
 168                                 #clock-cells = <1>;
 169                                 clock-indices = <0>;
 170                                 clock-output-names = "vcpu";
 171                         };
 172                 };
 173
 174                 scpi_sensors: sensors {
 175                         compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
 176                         #thermal-sensor-cells = <1>;
 177                 };
 178         };
 179
 180         soc {
 181                 compatible = "simple-bus";
 182                 #address-cells = <2>;
 183                 #size-cells = <2>;
 184                 ranges;
 185
 186                 apb: apb@ffe00000 {
 187                         compatible = "simple-bus";
 188                         reg = <0x0 0xffe00000 0x0 0x200000>;
 189                         #address-cells = <2>;
 190                         #size-cells = <2>;
 191                         ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
 192
 193                         sd_emmc_b: sd@5000 {
 194                                 compatible = "amlogic,meson-axg-mmc";
 195                                 reg = <0x0 0x5000 0x0 0x800>;
 196                                 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
 197                                 status = "disabled";
 198                                 clocks = <&clkc CLKID_SD_EMMC_B>,
 199                                         <&clkc CLKID_SD_EMMC_B_CLK0>,
 200                                         <&clkc CLKID_FCLK_DIV2>;
 201                                 clock-names = "core", "clkin0", "clkin1";
 202                                 resets = <&reset RESET_SD_EMMC_B>;
 203                         };
 204
 205                         sd_emmc_c: mmc@7000 {
 206                                 compatible = "amlogic,meson-axg-mmc";
 207                                 reg = <0x0 0x7000 0x0 0x800>;
 208                                 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 209                                 status = "disabled";
 210                                 clocks = <&clkc CLKID_SD_EMMC_C>,
 211                                         <&clkc CLKID_SD_EMMC_C_CLK0>,
 212                                         <&clkc CLKID_FCLK_DIV2>;
 213                                 clock-names = "core", "clkin0", "clkin1";
 214                                 resets = <&reset RESET_SD_EMMC_C>;
 215                         };
 216                 };
 217
 218                 audio: bus@ff642000 {
 219                         compatible = "simple-bus";
 220                         reg = <0x0 0xff642000 0x0 0x2000>;
 221                         #address-cells = <2>;
 222                         #size-cells = <2>;
 223                         ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
 224
 225                         clkc_audio: clock-controller@0 {
 226                                 compatible = "amlogic,axg-audio-clkc";
 227                                 reg = <0x0 0x0 0x0 0xb4>;
 228                                 #clock-cells = <1>;
 229
 230                                 clocks = <&clkc CLKID_AUDIO>,
 231                                          <&clkc CLKID_MPLL0>,
 232                                          <&clkc CLKID_MPLL1>,
 233                                          <&clkc CLKID_MPLL2>,
 234                                          <&clkc CLKID_MPLL3>,
 235                                          <&clkc CLKID_HIFI_PLL>,
 236                                          <&clkc CLKID_FCLK_DIV3>,
 237                                          <&clkc CLKID_FCLK_DIV4>,
 238                                          <&clkc CLKID_GP0_PLL>;
 239                                 clock-names = "pclk",
 240                                               "mst_in0",
 241                                               "mst_in1",
 242                                               "mst_in2",
 243                                               "mst_in3",
 244                                               "mst_in4",
 245                                               "mst_in5",
 246                                               "mst_in6",
 247                                               "mst_in7";
 248
 249                                 resets = <&reset RESET_AUDIO>;
 250                         };
 251
 252                         arb: reset-controller@280 {
 253                                 compatible = "amlogic,meson-axg-audio-arb";
 254                                 reg = <0x0 0x280 0x0 0x4>;
 255                                 #reset-cells = <1>;
 256                                 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
 257                         };
 258
 259                         tdmin_a: audio-controller@300 {
 260                                 compatible = "amlogic,axg-tdmin";
 261                                 reg = <0x0 0x300 0x0 0x40>;
 262                                 sound-name-prefix = "TDMIN_A";
 263                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
 264                                          <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
 265                                          <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
 266                                          <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
 267                                          <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
 268                                 clock-names = "pclk", "sclk", "sclk_sel",
 269                                               "lrclk", "lrclk_sel";
 270                                 status = "disabled";
 271                         };
 272
 273                         tdmin_b: audio-controller@340 {
 274                                 compatible = "amlogic,axg-tdmin";
 275                                 reg = <0x0 0x340 0x0 0x40>;
 276                                 sound-name-prefix = "TDMIN_B";
 277                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
 278                                          <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
 279                                          <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
 280                                          <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
 281                                          <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
 282                                 clock-names = "pclk", "sclk", "sclk_sel",
 283                                               "lrclk", "lrclk_sel";
 284                                 status = "disabled";
 285                         };
 286
 287                         tdmin_c: audio-controller@380 {
 288                                 compatible = "amlogic,axg-tdmin";
 289                                 reg = <0x0 0x380 0x0 0x40>;
 290                                 sound-name-prefix = "TDMIN_C";
 291                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
 292                                          <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
 293                                          <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
 294                                          <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
 295                                          <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
 296                                 clock-names = "pclk", "sclk", "sclk_sel",
 297                                               "lrclk", "lrclk_sel";
 298                                 status = "disabled";
 299                         };
 300
 301                         tdmin_lb: audio-controller@3c0 {
 302                                 compatible = "amlogic,axg-tdmin";
 303                                 reg = <0x0 0x3c0 0x0 0x40>;
 304                                 sound-name-prefix = "TDMIN_LB";
 305                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
 306                                          <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
 307                                          <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
 308                                          <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
 309                                          <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
 310                                 clock-names = "pclk", "sclk", "sclk_sel",
 311                                               "lrclk", "lrclk_sel";
 312                                 status = "disabled";
 313                         };
 314
 315                         spdifout: audio-controller@480 {
 316                                 compatible = "amlogic,axg-spdifout";
 317                                 reg = <0x0 0x480 0x0 0x50>;
 318                                 #sound-dai-cells = <0>;
 319                                 sound-name-prefix = "SPDIFOUT";
 320                                 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
 321                                          <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
 322                                 clock-names = "pclk", "mclk";
 323                                 status = "disabled";
 324                         };
 325
 326                         tdmout_a: audio-controller@500 {
 327                                 compatible = "amlogic,axg-tdmout";
 328                                 reg = <0x0 0x500 0x0 0x40>;
 329                                 sound-name-prefix = "TDMOUT_A";
 330                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
 331                                          <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
 332                                          <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
 333                                          <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
 334                                          <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
 335                                 clock-names = "pclk", "sclk", "sclk_sel",
 336                                               "lrclk", "lrclk_sel";
 337                                 status = "disabled";
 338                         };
 339
 340                         tdmout_b: audio-controller@540 {
 341                                 compatible = "amlogic,axg-tdmout";
 342                                 reg = <0x0 0x540 0x0 0x40>;
 343                                 sound-name-prefix = "TDMOUT_B";
 344                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
 345                                          <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
 346                                          <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
 347                                          <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
 348                                          <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
 349                                 clock-names = "pclk", "sclk", "sclk_sel",
 350                                               "lrclk", "lrclk_sel";
 351                                 status = "disabled";
 352                         };
 353
 354                         tdmout_c: audio-controller@580 {
 355                                 compatible = "amlogic,axg-tdmout";
 356                                 reg = <0x0 0x580 0x0 0x40>;
 357                                 sound-name-prefix = "TDMOUT_C";
 358                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
 359                                          <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
 360                                          <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
 361                                          <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
 362                                          <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
 363                                 clock-names = "pclk", "sclk", "sclk_sel",
 364                                               "lrclk", "lrclk_sel";
 365                                 status = "disabled";
 366                         };
 367                 };
 368
 369                 cbus: bus@ffd00000 {
 370                         compatible = "simple-bus";
 371                         reg = <0x0 0xffd00000 0x0 0x25000>;
 372                         #address-cells = <2>;
 373                         #size-cells = <2>;
 374                         ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
 375
 376                         gpio_intc: interrupt-controller@f080 {
 377                                 compatible = "amlogic,meson-gpio-intc";
 378                                 reg = <0x0 0xf080 0x0 0x10>;
 379                                 interrupt-controller;
 380                                 #interrupt-cells = <2>;
 381                                 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
 382                                 status = "disabled";
 383                         };
 384
 385                         pwm_ab: pwm@1b000 {
 386                                 compatible = "amlogic,meson-axg-ee-pwm";
 387                                 reg = <0x0 0x1b000 0x0 0x20>;
 388                                 #pwm-cells = <3>;
 389                                 status = "disabled";
 390                         };
 391
 392                         pwm_cd: pwm@1a000 {
 393                                 compatible = "amlogic,meson-axg-ee-pwm";
 394                                 reg = <0x0 0x1a000 0x0 0x20>;
 395                                 #pwm-cells = <3>;
 396                                 status = "disabled";
 397                         };
 398
 399                         reset: reset-controller@1004 {
 400                                 compatible = "amlogic,meson-axg-reset";
 401                                 reg = <0x0 0x01004 0x0 0x9c>;
 402                                 #reset-cells = <1>;
 403                         };
 404
 405                         spicc0: spi@13000 {
 406                                 compatible = "amlogic,meson-axg-spicc";
 407                                 reg = <0x0 0x13000 0x0 0x3c>;
 408                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 409                                 clocks = <&clkc CLKID_SPICC0>;
 410                                 clock-names = "core";
 411                                 #address-cells = <1>;
 412                                 #size-cells = <0>;
 413                                 status = "disabled";
 414                         };
 415
 416                         spicc1: spi@15000 {
 417                                 compatible = "amlogic,meson-axg-spicc";
 418                                 reg = <0x0 0x15000 0x0 0x3c>;
 419                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 420                                 clocks = <&clkc CLKID_SPICC1>;
 421                                 clock-names = "core";
 422                                 #address-cells = <1>;
 423                                 #size-cells = <0>;
 424                                 status = "disabled";
 425                         };
 426
 427                         i2c0: i2c@1f000 {
 428                                 compatible = "amlogic,meson-axg-i2c";
 429                                 reg = <0x0 0x1f000 0x0 0x20>;
 430                                 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
 431                                 clocks = <&clkc CLKID_I2C>;
 432                                 #address-cells = <1>;
 433                                 #size-cells = <0>;
 434                                 status = "disabled";
 435                         };
 436
 437                         i2c1: i2c@1e000 {
 438                                 compatible = "amlogic,meson-axg-i2c";
 439                                 reg = <0x0 0x1e000 0x0 0x20>;
 440                                 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
 441                                 clocks = <&clkc CLKID_I2C>;
 442                                 #address-cells = <1>;
 443                                 #size-cells = <0>;
 444                                 status = "disabled";
 445                         };
 446
 447                         i2c2: i2c@1d000 {
 448                                 compatible = "amlogic,meson-axg-i2c";
 449                                 reg = <0x0 0x1d000 0x0 0x20>;
 450                                 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
 451                                 clocks = <&clkc CLKID_I2C>;
 452                                 #address-cells = <1>;
 453                                 #size-cells = <0>;
 454                                 status = "disabled";
 455                         };
 456
 457                         i2c3: i2c@1c000 {
 458                                 compatible = "amlogic,meson-axg-i2c";
 459                                 reg = <0x0 0x1c000 0x0 0x20>;
 460                                 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
 461                                 clocks = <&clkc CLKID_I2C>;
 462                                 #address-cells = <1>;
 463                                 #size-cells = <0>;
 464                                 status = "disabled";
 465                         };
 466
 467                         uart_A: serial@24000 {
 468                                 compatible = "amlogic,meson-gx-uart";
 469                                 reg = <0x0 0x24000 0x0 0x18>;
 470                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 471                                 status = "disabled";
 472                                 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 473                                 clock-names = "xtal", "pclk", "baud";
 474                         };
 475
 476                         uart_B: serial@23000 {
 477                                 compatible = "amlogic,meson-gx-uart";
 478                                 reg = <0x0 0x23000 0x0 0x18>;
 479                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 480                                 status = "disabled";
 481                                 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 482                                 clock-names = "xtal", "pclk", "baud";
 483                         };
 484                 };
 485
 486                 ethmac: ethernet@ff3f0000 {
 487                         compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
 488                         reg = <0x0 0xff3f0000 0x0 0x10000
 489                                 0x0 0xff634540 0x0 0x8>;
 490                         interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
 491                         interrupt-names = "macirq";
 492                         clocks = <&clkc CLKID_ETH>,
 493                                  <&clkc CLKID_FCLK_DIV2>,
 494                                  <&clkc CLKID_MPLL2>;
 495                         clock-names = "stmmaceth", "clkin0", "clkin1";
 496                         status = "disabled";
 497                 };
 498
 499                 gic: interrupt-controller@ffc01000 {
 500                         compatible = "arm,gic-400";
 501                         reg = <0x0 0xffc01000 0 0x1000>,
 502                               <0x0 0xffc02000 0 0x2000>,
 503                               <0x0 0xffc04000 0 0x2000>,
 504                               <0x0 0xffc06000 0 0x2000>;
 505                         interrupt-controller;
 506                         interrupts = <GIC_PPI 9
 507                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 508                         #interrupt-cells = <3>;
 509                         #address-cells = <0>;
 510                 };
 511
 512                 hiubus: bus@ff63c000 {
 513                         compatible = "simple-bus";
 514                         reg = <0x0 0xff63c000 0x0 0x1c00>;
 515                         #address-cells = <2>;
 516                         #size-cells = <2>;
 517                         ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
 518
 519                         sysctrl: system-controller@0 {
 520                                 compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
 521                                 reg = <0 0 0 0x400>;
 522
 523                                 clkc: clock-controller {
 524                                         compatible = "amlogic,axg-clkc";
 525                                         #clock-cells = <1>;
 526                                 };
 527                         };
 528                 };
 529
 530                 mailbox: mailbox@ff63dc00 {
 531                         compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
 532                         reg = <0 0xff63dc00 0 0x400>;
 533                         interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
 534                                      <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
 535                                      <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
 536                         #mbox-cells = <1>;
 537                 };
 538
 539                 periphs: periphs@ff634000 {
 540                         compatible = "simple-bus";
 541                         reg = <0x0 0xff634000 0x0 0x2000>;
 542                         #address-cells = <2>;
 543                         #size-cells = <2>;
 544                         ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
 545
 546                         hwrng: rng {
 547                                 compatible = "amlogic,meson-rng";
 548                                 reg = <0x0 0x18 0x0 0x4>;
 549                                 clocks = <&clkc CLKID_RNG0>;
 550                                 clock-names = "core";
 551                         };
 552
 553                         pinctrl_periphs: pinctrl@480 {
 554                                 compatible = "amlogic,meson-axg-periphs-pinctrl";
 555                                 #address-cells = <2>;
 556                                 #size-cells = <2>;
 557                                 ranges;
 558
 559                                 gpio: bank@480 {
 560                                         reg = <0x0 0x00480 0x0 0x40>,
 561                                                 <0x0 0x004e8 0x0 0x14>,
 562                                                 <0x0 0x00520 0x0 0x14>,
 563                                                 <0x0 0x00430 0x0 0x3c>;
 564                                         reg-names = "mux", "pull", "pull-enable", "gpio";
 565                                         gpio-controller;
 566                                         #gpio-cells = <2>;
 567                                         gpio-ranges = <&pinctrl_periphs 0 0 86>;
 568                                 };
 569
 570                                 emmc_pins: emmc {
 571                                         mux {
 572                                                 groups = "emmc_nand_d0",
 573                                                         "emmc_nand_d1",
 574                                                         "emmc_nand_d2",
 575                                                         "emmc_nand_d3",
 576                                                         "emmc_nand_d4",
 577                                                         "emmc_nand_d5",
 578                                                         "emmc_nand_d6",
 579                                                         "emmc_nand_d7",
 580                                                         "emmc_clk",
 581                                                         "emmc_cmd",
 582                                                         "emmc_ds";
 583                                                 function = "emmc";
 584                                         };
 585                                 };
 586
 587                                 emmc_clk_gate_pins: emmc_clk_gate {
 588                                         mux {
 589                                                 groups = "BOOT_8";
 590                                                 function = "gpio_periphs";
 591                                         };
 592                                         cfg-pull-down {
 593                                                 pins = "BOOT_8";
 594                                                 bias-pull-down;
 595                                         };
 596                                 };
 597
 598                                 sdio_pins: sdio {
 599                                         mux {
 600                                                 groups = "sdio_d0",
 601                                                         "sdio_d1",
 602                                                         "sdio_d2",
 603                                                         "sdio_d3",
 604                                                         "sdio_cmd",
 605                                                         "sdio_clk";
 606                                                 function = "sdio";
 607                                         };
 608                                 };
 609
 610                                 sdio_clk_gate_pins: sdio_clk_gate {
 611                                         mux {
 612                                                 groups = "GPIOX_4";
 613                                                 function = "gpio_periphs";
 614                                         };
 615                                         cfg-pull-down {
 616                                                 pins = "GPIOX_4";
 617                                                 bias-pull-down;
 618                                         };
 619                                 };
 620
 621                                 eth_rmii_x_pins: eth-x-rmii {
 622                                         mux {
 623                                                 groups = "eth_mdio_x",
 624                                                        "eth_mdc_x",
 625                                                        "eth_rgmii_rx_clk_x",
 626                                                        "eth_rx_dv_x",
 627                                                        "eth_rxd0_x",
 628                                                        "eth_rxd1_x",
 629                                                        "eth_txen_x",
 630                                                        "eth_txd0_x",
 631                                                        "eth_txd1_x";
 632                                                 function = "eth";
 633                                         };
 634                                 };
 635
 636                                 eth_rmii_y_pins: eth-y-rmii {
 637                                         mux {
 638                                                 groups = "eth_mdio_y",
 639                                                        "eth_mdc_y",
 640                                                        "eth_rgmii_rx_clk_y",
 641                                                        "eth_rx_dv_y",
 642                                                        "eth_rxd0_y",
 643                                                        "eth_rxd1_y",
 644                                                        "eth_txen_y",
 645                                                        "eth_txd0_y",
 646                                                        "eth_txd1_y";
 647                                                 function = "eth";
 648                                         };
 649                                 };
 650
 651                                 eth_rgmii_x_pins: eth-x-rgmii {
 652                                         mux {
 653                                                 groups = "eth_mdio_x",
 654                                                        "eth_mdc_x",
 655                                                        "eth_rgmii_rx_clk_x",
 656                                                        "eth_rx_dv_x",
 657                                                        "eth_rxd0_x",
 658                                                        "eth_rxd1_x",
 659                                                        "eth_rxd2_rgmii",
 660                                                        "eth_rxd3_rgmii",
 661                                                        "eth_rgmii_tx_clk",
 662                                                        "eth_txen_x",
 663                                                        "eth_txd0_x",
 664                                                        "eth_txd1_x",
 665                                                        "eth_txd2_rgmii",
 666                                                        "eth_txd3_rgmii";
 667                                                 function = "eth";
 668                                         };
 669                                 };
 670
 671                                 eth_rgmii_y_pins: eth-y-rgmii {
 672                                         mux {
 673                                                 groups = "eth_mdio_y",
 674                                                        "eth_mdc_y",
 675                                                        "eth_rgmii_rx_clk_y",
 676                                                        "eth_rx_dv_y",
 677                                                        "eth_rxd0_y",
 678                                                        "eth_rxd1_y",
 679                                                        "eth_rxd2_rgmii",
 680                                                        "eth_rxd3_rgmii",
 681                                                        "eth_rgmii_tx_clk",
 682                                                        "eth_txen_y",
 683                                                        "eth_txd0_y",
 684                                                        "eth_txd1_y",
 685                                                        "eth_txd2_rgmii",
 686                                                        "eth_txd3_rgmii";
 687                                                 function = "eth";
 688                                         };
 689                                 };
 690
 691                                 pdm_dclk_a14_pins: pdm_dclk_a14 {
 692                                         mux {
 693                                                 groups = "pdm_dclk_a14";
 694                                                 function = "pdm";
 695                                         };
 696                                 };
 697
 698                                 pdm_dclk_a19_pins: pdm_dclk_a19 {
 699                                         mux {
 700                                                 groups = "pdm_dclk_a19";
 701                                                 function = "pdm";
 702                                         };
 703                                 };
 704
 705                                 pdm_din0_pins: pdm_din0 {
 706                                         mux {
 707                                                 groups = "pdm_din0";
 708                                                 function = "pdm";
 709                                         };
 710                                 };
 711
 712                                 pdm_din1_pins: pdm_din1 {
 713                                         mux {
 714                                                 groups = "pdm_din1";
 715                                                 function = "pdm";
 716                                         };
 717                                 };
 718
 719                                 pdm_din2_pins: pdm_din2 {
 720                                         mux {
 721                                                 groups = "pdm_din2";
 722                                                 function = "pdm";
 723                                         };
 724                                 };
 725
 726                                 pdm_din3_pins: pdm_din3 {
 727                                         mux {
 728                                                 groups = "pdm_din3";
 729                                                 function = "pdm";
 730                                         };
 731                                 };
 732
 733                                 pwm_a_a_pins: pwm_a_a {
 734                                         mux {
 735                                                 groups = "pwm_a_a";
 736                                                 function = "pwm_a";
 737                                         };
 738                                 };
 739
 740                                 pwm_a_x18_pins: pwm_a_x18 {
 741                                         mux {
 742                                                 groups = "pwm_a_x18";
 743                                                 function = "pwm_a";
 744                                         };
 745                                 };
 746
 747                                 pwm_a_x20_pins: pwm_a_x20 {
 748                                         mux {
 749                                                 groups = "pwm_a_x20";
 750                                                 function = "pwm_a";
 751                                         };
 752                                 };
 753
 754                                 pwm_a_z_pins: pwm_a_z {
 755                                         mux {
 756                                                 groups = "pwm_a_z";
 757                                                 function = "pwm_a";
 758                                         };
 759                                 };
 760
 761                                 pwm_b_a_pins: pwm_b_a {
 762                                         mux {
 763                                                 groups = "pwm_b_a";
 764                                                 function = "pwm_b";
 765                                         };
 766                                 };
 767
 768                                 pwm_b_x_pins: pwm_b_x {
 769                                         mux {
 770                                                 groups = "pwm_b_x";
 771                                                 function = "pwm_b";
 772                                         };
 773                                 };
 774
 775                                 pwm_b_z_pins: pwm_b_z {
 776                                         mux {
 777                                                 groups = "pwm_b_z";
 778                                                 function = "pwm_b";
 779                                         };
 780                                 };
 781
 782                                 pwm_c_a_pins: pwm_c_a {
 783                                         mux {
 784                                                 groups = "pwm_c_a";
 785                                                 function = "pwm_c";
 786                                         };
 787                                 };
 788
 789                                 pwm_c_x10_pins: pwm_c_x10 {
 790                                         mux {
 791                                                 groups = "pwm_c_x10";
 792                                                 function = "pwm_c";
 793                                         };
 794                                 };
 795
 796                                 pwm_c_x17_pins: pwm_c_x17 {
 797                                         mux {
 798                                                 groups = "pwm_c_x17";
 799                                                 function = "pwm_c";
 800                                         };
 801                                 };
 802
 803                                 pwm_d_x11_pins: pwm_d_x11 {
 804                                         mux {
 805                                                 groups = "pwm_d_x11";
 806                                                 function = "pwm_d";
 807                                         };
 808                                 };
 809
 810                                 pwm_d_x16_pins: pwm_d_x16 {
 811                                         mux {
 812                                                 groups = "pwm_d_x16";
 813                                                 function = "pwm_d";
 814                                         };
 815                                 };
 816
 817                                 spdif_in_z_pins: spdif_in_z {
 818                                         mux {
 819                                                 groups = "spdif_in_z";
 820                                                 function = "spdif_in";
 821                                         };
 822                                 };
 823
 824                                 spdif_in_a1_pins: spdif_in_a1 {
 825                                         mux {
 826                                                 groups = "spdif_in_a1";
 827                                                 function = "spdif_in";
 828                                         };
 829                                 };
 830
 831                                 spdif_in_a7_pins: spdif_in_a7 {
 832                                         mux {
 833                                                 groups = "spdif_in_a7";
 834                                                 function = "spdif_in";
 835                                         };
 836                                 };
 837
 838                                 spdif_in_a19_pins: spdif_in_a19 {
 839                                         mux {
 840                                                 groups = "spdif_in_a19";
 841                                                 function = "spdif_in";
 842                                         };
 843                                 };
 844
 845                                 spdif_in_a20_pins: spdif_in_a20 {
 846                                         mux {
 847                                                 groups = "spdif_in_a20";
 848                                                 function = "spdif_in";
 849                                         };
 850                                 };
 851
 852                                 spdif_out_z_pins: spdif_out_z {
 853                                         mux {
 854                                                 groups = "spdif_out_z";
 855                                                 function = "spdif_out";
 856                                         };
 857                                 };
 858
 859                                 spdif_out_a1_pins: spdif_out_a1 {
 860                                         mux {
 861                                                 groups = "spdif_out_a1";
 862                                                 function = "spdif_out";
 863                                         };
 864                                 };
 865
 866                                 spdif_out_a11_pins: spdif_out_a11 {
 867                                         mux {
 868                                                 groups = "spdif_out_a11";
 869                                                 function = "spdif_out";
 870                                         };
 871                                 };
 872
 873                                 spdif_out_a19_pins: spdif_out_a19 {
 874                                         mux {
 875                                                 groups = "spdif_out_a19";
 876                                                 function = "spdif_out";
 877                                         };
 878                                 };
 879
 880                                 spdif_out_a20_pins: spdif_out_a20 {
 881                                         mux {
 882                                                 groups = "spdif_out_a20";
 883                                                 function = "spdif_out";
 884                                         };
 885                                 };
 886
 887                                 spi0_pins: spi0 {
 888                                         mux {
 889                                                 groups = "spi0_miso",
 890                                                         "spi0_mosi",
 891                                                         "spi0_clk";
 892                                                 function = "spi0";
 893                                         };
 894                                 };
 895
 896                                 spi0_ss0_pins: spi0_ss0 {
 897                                         mux {
 898                                                 groups = "spi0_ss0";
 899                                                 function = "spi0";
 900                                         };
 901                                 };
 902
 903                                 spi0_ss1_pins: spi0_ss1 {
 904                                         mux {
 905                                                 groups = "spi0_ss1";
 906                                                 function = "spi0";
 907                                         };
 908                                 };
 909
 910                                 spi0_ss2_pins: spi0_ss2 {
 911                                         mux {
 912                                                 groups = "spi0_ss2";
 913                                                 function = "spi0";
 914                                         };
 915                                 };
 916
 917
 918                                 spi1_a_pins: spi1_a {
 919                                         mux {
 920                                                 groups = "spi1_miso_a",
 921                                                         "spi1_mosi_a",
 922                                                         "spi1_clk_a";
 923                                                 function = "spi1";
 924                                         };
 925                                 };
 926
 927                                 spi1_ss0_a_pins: spi1_ss0_a {
 928                                         mux {
 929                                                 groups = "spi1_ss0_a";
 930                                                 function = "spi1";
 931                                         };
 932                                 };
 933
 934                                 spi1_ss1_pins: spi1_ss1 {
 935                                         mux {
 936                                                 groups = "spi1_ss1";
 937                                                 function = "spi1";
 938                                         };
 939                                 };
 940
 941                                 spi1_x_pins: spi1_x {
 942                                         mux {
 943                                                 groups = "spi1_miso_x",
 944                                                         "spi1_mosi_x",
 945                                                         "spi1_clk_x";
 946                                                 function = "spi1";
 947                                         };
 948                                 };
 949
 950                                 spi1_ss0_x_pins: spi1_ss0_x {
 951                                         mux {
 952                                                 groups = "spi1_ss0_x";
 953                                                 function = "spi1";
 954                                         };
 955                                 };
 956
 957                                 i2c0_pins: i2c0 {
 958                                         mux {
 959                                                 groups = "i2c0_sck",
 960                                                         "i2c0_sda";
 961                                                 function = "i2c0";
 962                                         };
 963                                 };
 964
 965                                 i2c1_z_pins: i2c1_z {
 966                                         mux {
 967                                                 groups = "i2c1_sck_z",
 968                                                         "i2c1_sda_z";
 969                                                 function = "i2c1";
 970                                         };
 971                                 };
 972
 973                                 i2c1_x_pins: i2c1_x {
 974                                         mux {
 975                                                 groups = "i2c1_sck_x",
 976                                                         "i2c1_sda_x";
 977                                                 function = "i2c1";
 978                                         };
 979                                 };
 980
 981                                 i2c2_x_pins: i2c2_x {
 982                                         mux {
 983                                                 groups = "i2c2_sck_x",
 984                                                         "i2c2_sda_x";
 985                                                 function = "i2c2";
 986                                         };
 987                                 };
 988
 989                                 i2c2_a_pins: i2c2_a {
 990                                         mux {
 991                                                 groups = "i2c2_sck_a",
 992                                                         "i2c2_sda_a";
 993                                                 function = "i2c2";
 994                                         };
 995                                 };
 996
 997                                 i2c3_a6_pins: i2c3_a6 {
 998                                         mux {
 999                                                 groups = "i2c3_sda_a6",
1000                                                         "i2c3_sck_a7";
1001                                                 function = "i2c3";
1002                                         };
1003                                 };
1004
1005                                 i2c3_a12_pins: i2c3_a12 {
1006                                         mux {
1007                                                 groups = "i2c3_sda_a12",
1008                                                         "i2c3_sck_a13";
1009                                                 function = "i2c3";
1010                                         };
1011                                 };
1012
1013                                 i2c3_a19_pins: i2c3_a19 {
1014                                         mux {
1015                                                 groups = "i2c3_sda_a19",
1016                                                         "i2c3_sck_a20";
1017                                                 function = "i2c3";
1018                                         };
1019                                 };
1020
1021                                 uart_a_pins: uart_a {
1022                                         mux {
1023                                                 groups = "uart_tx_a",
1024                                                         "uart_rx_a";
1025                                                 function = "uart_a";
1026                                         };
1027                                 };
1028
1029                                 uart_a_cts_rts_pins: uart_a_cts_rts {
1030                                         mux {
1031                                                 groups = "uart_cts_a",
1032                                                         "uart_rts_a";
1033                                                 function = "uart_a";
1034                                         };
1035                                 };
1036
1037                                 uart_b_x_pins: uart_b_x {
1038                                         mux {
1039                                                 groups = "uart_tx_b_x",
1040                                                         "uart_rx_b_x";
1041                                                 function = "uart_b";
1042                                         };
1043                                 };
1044
1045                                 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1046                                         mux {
1047                                                 groups = "uart_cts_b_x",
1048                                                         "uart_rts_b_x";
1049                                                 function = "uart_b";
1050                                         };
1051                                 };
1052
1053                                 uart_b_z_pins: uart_b_z {
1054                                         mux {
1055                                                 groups = "uart_tx_b_z",
1056                                                         "uart_rx_b_z";
1057                                                 function = "uart_b";
1058                                         };
1059                                 };
1060
1061                                 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1062                                         mux {
1063                                                 groups = "uart_cts_b_z",
1064                                                         "uart_rts_b_z";
1065                                                 function = "uart_b";
1066                                         };
1067                                 };
1068
1069                                 uart_ao_b_z_pins: uart_ao_b_z {
1070                                         mux {
1071                                                 groups = "uart_ao_tx_b_z",
1072                                                         "uart_ao_rx_b_z";
1073                                                 function = "uart_ao_b_z";
1074                                         };
1075                                 };
1076
1077                                 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1078                                         mux {
1079                                                 groups = "uart_ao_cts_b_z",
1080                                                         "uart_ao_rts_b_z";
1081                                                 function = "uart_ao_b_z";
1082                                         };
1083                                 };
1084
1085                                 mclk_b_pins: mclk_b {
1086                                         mux {
1087                                                 groups = "mclk_b";
1088                                                 function = "mclk_b";
1089                                         };
1090                                 };
1091
1092                                 mclk_c_pins: mclk_c {
1093                                         mux {
1094                                                 groups = "mclk_c";
1095                                                 function = "mclk_c";
1096                                         };
1097                                 };
1098
1099                                 tdma_sclk_pins: tdma_sclk {
1100                                         mux {
1101                                                 groups = "tdma_sclk";
1102                                                 function = "tdma";
1103                                         };
1104                                 };
1105
1106                                 tdma_sclk_slv_pins: tdma_sclk_slv {
1107                                         mux {
1108                                                 groups = "tdma_sclk_slv";
1109                                                 function = "tdma";
1110                                         };
1111                                 };
1112
1113                                 tdma_fs_pins: tdma_fs {
1114                                         mux {
1115                                                 groups = "tdma_fs";
1116                                                 function = "tdma";
1117                                         };
1118                                 };
1119
1120                                 tdma_fs_slv_pins: tdma_fs_slv {
1121                                         mux {
1122                                                 groups = "tdma_fs_slv";
1123                                                 function = "tdma";
1124                                         };
1125                                 };
1126
1127                                 tdma_din0_pins: tdma_din0 {
1128                                         mux {
1129                                                 groups = "tdma_din0";
1130                                                 function = "tdma";
1131                                         };
1132                                 };
1133
1134                                 tdma_dout0_x14_pins: tdma_dout0_x14 {
1135                                         mux {
1136                                                 groups = "tdma_dout0_x14";
1137                                                 function = "tdma";
1138                                         };
1139                                 };
1140
1141                                 tdma_dout0_x15_pins: tdma_dout0_x15 {
1142                                         mux {
1143                                                 groups = "tdma_dout0_x15";
1144                                                 function = "tdma";
1145                                         };
1146                                 };
1147
1148                                 tdma_dout1_pins: tdma_dout1 {
1149                                         mux {
1150                                                 groups = "tdma_dout1";
1151                                                 function = "tdma";
1152                                         };
1153                                 };
1154
1155                                 tdma_din1_pins: tdma_din1 {
1156                                         mux {
1157                                                 groups = "tdma_din1";
1158                                                 function = "tdma";
1159                                         };
1160                                 };
1161
1162                                 tdmb_sclk_pins: tdmb_sclk {
1163                                         mux {
1164                                                 groups = "tdmb_sclk";
1165                                                 function = "tdmb";
1166                                         };
1167                                 };
1168
1169                                 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1170                                         mux {
1171                                                 groups = "tdmb_sclk_slv";
1172                                                 function = "tdmb";
1173                                         };
1174                                 };
1175
1176                                 tdmb_fs_pins: tdmb_fs {
1177                                         mux {
1178                                                 groups = "tdmb_fs";
1179                                                 function = "tdmb";
1180                                         };
1181                                 };
1182
1183                                 tdmb_fs_slv_pins: tdmb_fs_slv {
1184                                         mux {
1185                                                 groups = "tdmb_fs_slv";
1186                                                 function = "tdmb";
1187                                         };
1188                                 };
1189
1190                                 tdmb_din0_pins: tdmb_din0 {
1191                                         mux {
1192                                                 groups = "tdmb_din0";
1193                                                 function = "tdmb";
1194                                         };
1195                                 };
1196
1197                                 tdmb_dout0_pins: tdmb_dout0 {
1198                                         mux {
1199                                                 groups = "tdmb_dout0";
1200                                                 function = "tdmb";
1201                                         };
1202                                 };
1203
1204                                 tdmb_din1_pins: tdmb_din1 {
1205                                         mux {
1206                                                 groups = "tdmb_din1";
1207                                                 function = "tdmb";
1208                                         };
1209                                 };
1210
1211                                 tdmb_dout1_pins: tdmb_dout1 {
1212                                         mux {
1213                                                 groups = "tdmb_dout1";
1214                                                 function = "tdmb";
1215                                         };
1216                                 };
1217
1218                                 tdmb_din2_pins: tdmb_din2 {
1219                                         mux {
1220                                                 groups = "tdmb_din2";
1221                                                 function = "tdmb";
1222                                         };
1223                                 };
1224
1225                                 tdmb_dout2_pins: tdmb_dout2 {
1226                                         mux {
1227                                                 groups = "tdmb_dout2";
1228                                                 function = "tdmb";
1229                                         };
1230                                 };
1231
1232                                 tdmb_din3_pins: tdmb_din3 {
1233                                         mux {
1234                                                 groups = "tdmb_din3";
1235                                                 function = "tdmb";
1236                                         };
1237                                 };
1238
1239                                 tdmb_dout3_pins: tdmb_dout3 {
1240                                         mux {
1241                                                 groups = "tdmb_dout3";
1242                                                 function = "tdmb";
1243                                         };
1244                                 };
1245
1246                                 tdmc_sclk_pins: tdmc_sclk {
1247                                         mux {
1248                                                 groups = "tdmc_sclk";
1249                                                 function = "tdmc";
1250                                         };
1251                                 };
1252
1253                                 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1254                                         mux {
1255                                                 groups = "tdmc_sclk_slv";
1256                                                 function = "tdmc";
1257                                         };
1258                                 };
1259
1260                                 tdmc_fs_pins: tdmc_fs {
1261                                         mux {
1262                                                 groups = "tdmc_fs";
1263                                                 function = "tdmc";
1264                                         };
1265                                 };
1266
1267                                 tdmc_fs_slv_pins: tdmc_fs_slv {
1268                                         mux {
1269                                                 groups = "tdmc_fs_slv";
1270                                                 function = "tdmc";
1271                                         };
1272                                 };
1273
1274                                 tdmc_din0_pins: tdmc_din0 {
1275                                         mux {
1276                                                 groups = "tdmc_din0";
1277                                                 function = "tdmc";
1278                                         };
1279                                 };
1280
1281                                 tdmc_dout0_pins: tdmc_dout0 {
1282                                         mux {
1283                                                 groups = "tdmc_dout0";
1284                                                 function = "tdmc";
1285                                         };
1286                                 };
1287
1288                                 tdmc_din1_pins: tdmc_din1 {
1289                                         mux {
1290                                                 groups = "tdmc_din1";
1291                                                 function = "tdmc";
1292                                         };
1293                                 };
1294
1295                                 tdmc_dout1_pins: tdmc_dout1 {
1296                                         mux {
1297                                                 groups = "tdmc_dout1";
1298                                                 function = "tdmc";
1299                                         };
1300                                 };
1301
1302                                 tdmc_din2_pins: tdmc_din2 {
1303                                         mux {
1304                                                 groups = "tdmc_din2";
1305                                                 function = "tdmc";
1306                                         };
1307                                 };
1308
1309                                 tdmc_dout2_pins: tdmc_dout2 {
1310                                         mux {
1311                                                 groups = "tdmc_dout2";
1312                                                 function = "tdmc";
1313                                         };
1314                                 };
1315
1316                                 tdmc_din3_pins: tdmc_din3 {
1317                                         mux {
1318                                                 groups = "tdmc_din3";
1319                                                 function = "tdmc";
1320                                         };
1321                                 };
1322
1323                                 tdmc_dout3_pins: tdmc_dout3 {
1324                                         mux {
1325                                                 groups = "tdmc_dout3";
1326                                                 function = "tdmc";
1327                                         };
1328                                 };
1329                         };
1330                 };
1331
1332                 sram: sram@fffc0000 {
1333                         compatible = "amlogic,meson-axg-sram", "mmio-sram";
1334                         reg = <0x0 0xfffc0000 0x0 0x20000>;
1335                         #address-cells = <1>;
1336                         #size-cells = <1>;
1337                         ranges = <0 0x0 0xfffc0000 0x20000>;
1338
1339                         cpu_scp_lpri: scp-shmem@0 {
1340                                 compatible = "amlogic,meson-axg-scp-shmem";
1341                                 reg = <0x13000 0x400>;
1342                         };
1343
1344                         cpu_scp_hpri: scp-shmem@200 {
1345                                 compatible = "amlogic,meson-axg-scp-shmem";
1346                                 reg = <0x13400 0x400>;
1347                         };
1348                 };
1349
1350                 aobus: bus@ff800000 {
1351                         compatible = "simple-bus";
1352                         reg = <0x0 0xff800000 0x0 0x100000>;
1353                         #address-cells = <2>;
1354                         #size-cells = <2>;
1355                         ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1356
1357                         sysctrl_AO: sys-ctrl@0 {
1358                                 compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
1359                                 reg =  <0x0 0x0 0x0 0x100>;
1360
1361                                 clkc_AO: clock-controller {
1362                                         compatible = "amlogic,meson-axg-aoclkc";
1363                                         #clock-cells = <1>;
1364                                         #reset-cells = <1>;
1365                                 };
1366                         };
1367
1368                         pinctrl_aobus: pinctrl@14 {
1369                                 compatible = "amlogic,meson-axg-aobus-pinctrl";
1370                                 #address-cells = <2>;
1371                                 #size-cells = <2>;
1372                                 ranges;
1373
1374                                 gpio_ao: bank@14 {
1375                                         reg = <0x0 0x00014 0x0 0x8>,
1376                                                 <0x0 0x0002c 0x0 0x4>,
1377                                                 <0x0 0x00024 0x0 0x8>;
1378                                         reg-names = "mux", "pull", "gpio";
1379                                         gpio-controller;
1380                                         #gpio-cells = <2>;
1381                                         gpio-ranges = <&pinctrl_aobus 0 0 15>;
1382                                 };
1383
1384                                 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1385                                         mux {
1386                                                 groups = "i2c_ao_sck_4";
1387                                                 function = "i2c_ao";
1388                                         };
1389                                 };
1390
1391                                 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1392                                         mux {
1393                                                 groups = "i2c_ao_sck_8";
1394                                                 function = "i2c_ao";
1395                                         };
1396                                 };
1397
1398                                 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1399                                         mux {
1400                                                 groups = "i2c_ao_sck_10";
1401                                                 function = "i2c_ao";
1402                                         };
1403                                 };
1404
1405                                 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1406                                         mux {
1407                                                 groups = "i2c_ao_sda_5";
1408                                                 function = "i2c_ao";
1409                                         };
1410                                 };
1411
1412                                 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1413                                         mux {
1414                                                 groups = "i2c_ao_sda_9";
1415                                                 function = "i2c_ao";
1416                                         };
1417                                 };
1418
1419                                 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1420                                         mux {
1421                                                 groups = "i2c_ao_sda_11";
1422                                                 function = "i2c_ao";
1423                                         };
1424                                 };
1425
1426                                 remote_input_ao_pins: remote_input_ao {
1427                                         mux {
1428                                                 groups = "remote_input_ao";
1429                                                 function = "remote_input_ao";
1430                                         };
1431                                 };
1432
1433                                 uart_ao_a_pins: uart_ao_a {
1434                                         mux {
1435                                                 groups = "uart_ao_tx_a",
1436                                                         "uart_ao_rx_a";
1437                                                 function = "uart_ao_a";
1438                                         };
1439                                 };
1440
1441                                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1442                                         mux {
1443                                                 groups = "uart_ao_cts_a",
1444                                                         "uart_ao_rts_a";
1445                                                 function = "uart_ao_a";
1446                                         };
1447                                 };
1448
1449                                 uart_ao_b_pins: uart_ao_b {
1450                                         mux {
1451                                                 groups = "uart_ao_tx_b",
1452                                                         "uart_ao_rx_b";
1453                                                 function = "uart_ao_b";
1454                                         };
1455                                 };
1456
1457                                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1458                                         mux {
1459                                                 groups = "uart_ao_cts_b",
1460                                                         "uart_ao_rts_b";
1461                                                 function = "uart_ao_b";
1462                                         };
1463                                 };
1464                         };
1465
1466                         sec_AO: ao-secure@140 {
1467                                 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1468                                 reg = <0x0 0x140 0x0 0x140>;
1469                                 amlogic,has-chip-id;
1470                         };
1471
1472                         pwm_AO_ab: pwm@7000 {
1473                                 compatible = "amlogic,meson-axg-ao-pwm";
1474                                 reg = <0x0 0x07000 0x0 0x20>;
1475                                 #pwm-cells = <3>;
1476                                 status = "disabled";
1477                         };
1478
1479                         pwm_AO_cd: pwm@2000 {
1480                                 compatible = "amlogic,meson-axg-ao-pwm";
1481                                 reg = <0x0 0x02000  0x0 0x20>;
1482                                 #pwm-cells = <3>;
1483                                 status = "disabled";
1484                         };
1485
1486                         i2c_AO: i2c@5000 {
1487                                 compatible = "amlogic,meson-axg-i2c";
1488                                 reg = <0x0 0x05000 0x0 0x20>;
1489                                 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1490                                 clocks = <&clkc CLKID_AO_I2C>;
1491                                 #address-cells = <1>;
1492                                 #size-cells = <0>;
1493                                 status = "disabled";
1494                         };
1495
1496                         uart_AO: serial@3000 {
1497                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1498                                 reg = <0x0 0x3000 0x0 0x18>;
1499                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1500                                 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1501                                 clock-names = "xtal", "pclk", "baud";
1502                                 status = "disabled";
1503                         };
1504
1505                         uart_AO_B: serial@4000 {
1506                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1507                                 reg = <0x0 0x4000 0x0 0x18>;
1508                                 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1509                                 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1510                                 clock-names = "xtal", "pclk", "baud";
1511                                 status = "disabled";
1512                         };
1513
1514                         ir: ir@8000 {
1515                                 compatible = "amlogic,meson-gxbb-ir";
1516                                 reg = <0x0 0x8000 0x0 0x20>;
1517                                 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1518                                 status = "disabled";
1519                         };
1520
1521                         saradc: adc@9000 {
1522                                 compatible = "amlogic,meson-axg-saradc",
1523                                         "amlogic,meson-saradc";
1524                                 reg = <0x0 0x9000 0x0 0x38>;
1525                                 #io-channel-cells = <1>;
1526                                 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1527                                 clocks = <&xtal>,
1528                                         <&clkc_AO CLKID_AO_SAR_ADC>,
1529                                         <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1530                                         <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1531                                 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1532                                 status = "disabled";
1533                         };
1534                 };
1535         };
1536 };