arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ARM Ltd. Fast Models
   4  *
   5  * Architecture Envelope Model (AEM) ARMv8-A
   6  * ARMAEMv8AMPCT
   7  *
   8  * RTSM_VE_AEMv8A.lisa
   9  */
  10
  11 /dts-v1/;
  12
  13 /memreserve/ 0x80000000 0x00010000;
  14
  15 #include "rtsm_ve-motherboard.dtsi"
  16
  17 / {
  18         model = "RTSM_VE_AEMv8A";
  19         compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         chosen { };
  25
  26         aliases {
  27                 serial0 = &v2m_serial0;
  28                 serial1 = &v2m_serial1;
  29                 serial2 = &v2m_serial2;
  30                 serial3 = &v2m_serial3;
  31         };
  32
  33         cpus {
  34                 #address-cells = <2>;
  35                 #size-cells = <0>;
  36
  37                 cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "arm,armv8";
  40                         reg = <0x0 0x0>;
  41                         enable-method = "spin-table";
  42                         cpu-release-addr = <0x0 0x8000fff8>;
  43                         next-level-cache = <&L2_0>;
  44                 };
  45                 cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,armv8";
  48                         reg = <0x0 0x1>;
  49                         enable-method = "spin-table";
  50                         cpu-release-addr = <0x0 0x8000fff8>;
  51                         next-level-cache = <&L2_0>;
  52                 };
  53                 cpu@2 {
  54                         device_type = "cpu";
  55                         compatible = "arm,armv8";
  56                         reg = <0x0 0x2>;
  57                         enable-method = "spin-table";
  58                         cpu-release-addr = <0x0 0x8000fff8>;
  59                         next-level-cache = <&L2_0>;
  60                 };
  61                 cpu@3 {
  62                         device_type = "cpu";
  63                         compatible = "arm,armv8";
  64                         reg = <0x0 0x3>;
  65                         enable-method = "spin-table";
  66                         cpu-release-addr = <0x0 0x8000fff8>;
  67                         next-level-cache = <&L2_0>;
  68                 };
  69
  70                 L2_0: l2-cache0 {
  71                         compatible = "cache";
  72                 };
  73         };
  74
  75         memory@80000000 {
  76                 device_type = "memory";
  77                 reg = <0x00000000 0x80000000 0 0x80000000>,
  78                       <0x00000008 0x80000000 0 0x80000000>;
  79         };
  80
  81         gic: interrupt-controller@2c001000 {
  82                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  83                 #interrupt-cells = <3>;
  84                 #address-cells = <0>;
  85                 interrupt-controller;
  86                 reg = <0x0 0x2c001000 0 0x1000>,
  87                       <0x0 0x2c002000 0 0x2000>,
  88                       <0x0 0x2c004000 0 0x2000>,
  89                       <0x0 0x2c006000 0 0x2000>;
  90                 interrupts = <1 9 0xf04>;
  91         };
  92
  93         timer {
  94                 compatible = "arm,armv8-timer";
  95                 interrupts = <1 13 0xf08>,
  96                              <1 14 0xf08>,
  97                              <1 11 0xf08>,
  98                              <1 10 0xf08>;
  99                 clock-frequency = <100000000>;
 100         };
 101
 102         pmu {
 103                 compatible = "arm,armv8-pmuv3";
 104                 interrupts = <0 60 4>,
 105                              <0 61 4>,
 106                              <0 62 4>,
 107                              <0 63 4>;
 108         };
 109
 110         smb@8000000 {
 111                 compatible = "simple-bus";
 112
 113                 #address-cells = <2>;
 114                 #size-cells = <1>;
 115                 ranges = <0 0 0 0x08000000 0x04000000>,
 116                          <1 0 0 0x14000000 0x04000000>,
 117                          <2 0 0 0x18000000 0x04000000>,
 118                          <3 0 0 0x1c000000 0x04000000>,
 119                          <4 0 0 0x0c000000 0x04000000>,
 120                          <5 0 0 0x10000000 0x04000000>;
 121
 122                 #interrupt-cells = <1>;
 123                 interrupt-map-mask = <0 0 63>;
 124                 interrupt-map = <0 0  0 &gic 0  0 4>,
 125                                 <0 0  1 &gic 0  1 4>,
 126                                 <0 0  2 &gic 0  2 4>,
 127                                 <0 0  3 &gic 0  3 4>,
 128                                 <0 0  4 &gic 0  4 4>,
 129                                 <0 0  5 &gic 0  5 4>,
 130                                 <0 0  6 &gic 0  6 4>,
 131                                 <0 0  7 &gic 0  7 4>,
 132                                 <0 0  8 &gic 0  8 4>,
 133                                 <0 0  9 &gic 0  9 4>,
 134                                 <0 0 10 &gic 0 10 4>,
 135                                 <0 0 11 &gic 0 11 4>,
 136                                 <0 0 12 &gic 0 12 4>,
 137                                 <0 0 13 &gic 0 13 4>,
 138                                 <0 0 14 &gic 0 14 4>,
 139                                 <0 0 15 &gic 0 15 4>,
 140                                 <0 0 16 &gic 0 16 4>,
 141                                 <0 0 17 &gic 0 17 4>,
 142                                 <0 0 18 &gic 0 18 4>,
 143                                 <0 0 19 &gic 0 19 4>,
 144                                 <0 0 20 &gic 0 20 4>,
 145                                 <0 0 21 &gic 0 21 4>,
 146                                 <0 0 22 &gic 0 22 4>,
 147                                 <0 0 23 &gic 0 23 4>,
 148                                 <0 0 24 &gic 0 24 4>,
 149                                 <0 0 25 &gic 0 25 4>,
 150                                 <0 0 26 &gic 0 26 4>,
 151                                 <0 0 27 &gic 0 27 4>,
 152                                 <0 0 28 &gic 0 28 4>,
 153                                 <0 0 29 &gic 0 29 4>,
 154                                 <0 0 30 &gic 0 30 4>,
 155                                 <0 0 31 &gic 0 31 4>,
 156                                 <0 0 32 &gic 0 32 4>,
 157                                 <0 0 33 &gic 0 33 4>,
 158                                 <0 0 34 &gic 0 34 4>,
 159                                 <0 0 35 &gic 0 35 4>,
 160                                 <0 0 36 &gic 0 36 4>,
 161                                 <0 0 37 &gic 0 37 4>,
 162                                 <0 0 38 &gic 0 38 4>,
 163                                 <0 0 39 &gic 0 39 4>,
 164                                 <0 0 40 &gic 0 40 4>,
 165                                 <0 0 41 &gic 0 41 4>,
 166                                 <0 0 42 &gic 0 42 4>;
 167         };
 168 };