arch/arm64/boot/dts/broadcom/ns2.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright (c) 2015 Broadcom.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /memreserve/ 0x81000000 0x00200000;
  34
  35 #include <dt-bindings/interrupt-controller/arm-gic.h>
  36 #include <dt-bindings/clock/bcm-ns2.h>
  37
  38 / {
  39         compatible = "brcm,ns2";
  40         interrupt-parent = <&gic>;
  41         #address-cells = <2>;
  42         #size-cells = <2>;
  43
  44         cpus {
  45                 #address-cells = <2>;
  46                 #size-cells = <0>;
  47
  48                 A57_0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a57", "arm,armv8";
  51                         reg = <0 0>;
  52                         enable-method = "psci";
  53                         next-level-cache = <&CLUSTER0_L2>;
  54                 };
  55
  56                 A57_1: cpu@1 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a57", "arm,armv8";
  59                         reg = <0 1>;
  60                         enable-method = "psci";
  61                         next-level-cache = <&CLUSTER0_L2>;
  62                 };
  63
  64                 A57_2: cpu@2 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a57", "arm,armv8";
  67                         reg = <0 2>;
  68                         enable-method = "psci";
  69                         next-level-cache = <&CLUSTER0_L2>;
  70                 };
  71
  72                 A57_3: cpu@3 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a57", "arm,armv8";
  75                         reg = <0 3>;
  76                         enable-method = "psci";
  77                         next-level-cache = <&CLUSTER0_L2>;
  78                 };
  79
  80                 CLUSTER0_L2: l2-cache@000 {
  81                         compatible = "cache";
  82                 };
  83         };
  84
  85         psci {
  86                 compatible = "arm,psci-1.0";
  87                 method = "smc";
  88         };
  89
  90         timer {
  91                 compatible = "arm,armv8-timer";
  92                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
  93                               IRQ_TYPE_LEVEL_LOW)>,
  94                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
  95                               IRQ_TYPE_LEVEL_LOW)>,
  96                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
  97                               IRQ_TYPE_LEVEL_LOW)>,
  98                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
  99                               IRQ_TYPE_LEVEL_LOW)>;
 100         };
 101
 102         pmu {
 103                 compatible = "arm,armv8-pmuv3";
 104                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 106                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 107                              <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 108                 interrupt-affinity = <&A57_0>,
 109                                      <&A57_1>,
 110                                      <&A57_2>,
 111                                      <&A57_3>;
 112         };
 113
 114         pcie0: pcie@20020000 {
 115                 compatible = "brcm,iproc-pcie";
 116                 reg = <0 0x20020000 0 0x1000>;
 117
 118                 #interrupt-cells = <1>;
 119                 interrupt-map-mask = <0 0 0 0>;
 120                 interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
 121
 122                 linux,pci-domain = <0>;
 123
 124                 bus-range = <0x00 0xff>;
 125
 126                 #address-cells = <3>;
 127                 #size-cells = <2>;
 128                 device_type = "pci";
 129                 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
 130
 131                 brcm,pcie-ob;
 132                 brcm,pcie-ob-oarr-size;
 133                 brcm,pcie-ob-axi-offset = <0x00000000>;
 134                 brcm,pcie-ob-window-size = <256>;
 135
 136                 status = "disabled";
 137
 138                 msi-parent = <&msi0>;
 139                 msi0: msi@20020000 {
 140                         compatible = "brcm,iproc-msi";
 141                         msi-controller;
 142                         interrupt-parent = <&gic>;
 143                         interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
 144                                      <GIC_SPI 278 IRQ_TYPE_NONE>,
 145                                      <GIC_SPI 279 IRQ_TYPE_NONE>,
 146                                      <GIC_SPI 280 IRQ_TYPE_NONE>;
 147                         brcm,num-eq-region = <1>;
 148                         brcm,num-msi-msg-region = <1>;
 149                 };
 150         };
 151
 152         pcie4: pcie@50020000 {
 153                 compatible = "brcm,iproc-pcie";
 154                 reg = <0 0x50020000 0 0x1000>;
 155
 156                 #interrupt-cells = <1>;
 157                 interrupt-map-mask = <0 0 0 0>;
 158                 interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
 159
 160                 linux,pci-domain = <4>;
 161
 162                 bus-range = <0x00 0xff>;
 163
 164                 #address-cells = <3>;
 165                 #size-cells = <2>;
 166                 device_type = "pci";
 167                 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
 168
 169                 brcm,pcie-ob;
 170                 brcm,pcie-ob-oarr-size;
 171                 brcm,pcie-ob-axi-offset = <0x30000000>;
 172                 brcm,pcie-ob-window-size = <256>;
 173
 174                 status = "disabled";
 175
 176                 msi-parent = <&msi4>;
 177                 msi4: msi@50020000 {
 178                         compatible = "brcm,iproc-msi";
 179                         msi-controller;
 180                         interrupt-parent = <&gic>;
 181                         interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
 182                                      <GIC_SPI 302 IRQ_TYPE_NONE>,
 183                                      <GIC_SPI 303 IRQ_TYPE_NONE>,
 184                                      <GIC_SPI 304 IRQ_TYPE_NONE>;
 185                 };
 186         };
 187
 188         soc: soc {
 189                 compatible = "simple-bus";
 190                 #address-cells = <1>;
 191                 #size-cells = <1>;
 192                 ranges = <0 0 0 0xffffffff>;
 193
 194                 #include "ns2-clock.dtsi"
 195
 196                 dma0: dma@61360000 {
 197                         compatible = "arm,pl330", "arm,primecell";
 198                         reg = <0x61360000 0x1000>;
 199                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 202                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 203                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 204                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 206                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 207                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 208                         #dma-cells = <1>;
 209                         #dma-channels = <8>;
 210                         #dma-requests = <32>;
 211                         clocks = <&iprocslow>;
 212                         clock-names = "apb_pclk";
 213                 };
 214
 215                 smmu: mmu@64000000 {
 216                         compatible = "arm,mmu-500";
 217                         reg = <0x64000000 0x40000>;
 218                         #global-interrupts = <2>;
 219                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 220                                      <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
 226                                      <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
 227                                      <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 228                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 229                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 239                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 243                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 245                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 248                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 249                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 250                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 251                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 252                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
 253                         mmu-masters;
 254                 };
 255
 256                 pinctrl: pinctrl@6501d130 {
 257                         compatible = "brcm,ns2-pinmux";
 258                         reg = <0x6501d130 0x08>,
 259                               <0x660a0028 0x04>,
 260                               <0x660009b0 0x40>;
 261                 };
 262
 263                 gpio_aon: gpio@65024800 {
 264                         compatible = "brcm,iproc-gpio";
 265                         reg = <0x65024800 0x50>,
 266                               <0x65024008 0x18>;
 267                         ngpios = <6>;
 268                         #gpio-cells = <2>;
 269                         gpio-controller;
 270                 };
 271
 272                 gic: interrupt-controller@65210000 {
 273                         compatible = "arm,gic-400";
 274                         #interrupt-cells = <3>;
 275                         interrupt-controller;
 276                         reg = <0x65210000 0x1000>,
 277                               <0x65220000 0x1000>,
 278                               <0x65240000 0x2000>,
 279                               <0x65260000 0x1000>;
 280                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 281                                       IRQ_TYPE_LEVEL_HIGH)>;
 282                 };
 283
 284                 cci@65590000 {
 285                         compatible = "arm,cci-400";
 286                         #address-cells = <1>;
 287                         #size-cells = <1>;
 288                         reg = <0x65590000 0x1000>;
 289                         ranges = <0 0x65590000 0x10000>;
 290
 291                         pmu@9000 {
 292                                 compatible = "arm,cci-400-pmu,r1",
 293                                              "arm,cci-400-pmu";
 294                                 reg = <0x9000 0x4000>;
 295                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
 296                                              <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 297                                              <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
 298                                              <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
 299                                              <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
 300                                              <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
 301                         };
 302                 };
 303
 304                 pwm: pwm@66010000 {
 305                         compatible = "brcm,iproc-pwm";
 306                         reg = <0x66010000 0x28>;
 307                         clocks = <&osc>;
 308                         #pwm-cells = <3>;
 309                         status = "disabled";
 310                 };
 311
 312                 mdio_mux_iproc: mdio-mux@6602023c {
 313                         compatible = "brcm,mdio-mux-iproc";
 314                         reg = <0x6602023c 0x14>;
 315                         #address-cells = <1>;
 316                         #size-cells = <0>;
 317
 318                         mdio@0 {
 319                                 reg = <0x0>;
 320                                 #address-cells = <1>;
 321                                 #size-cells = <0>;
 322
 323                                 pci_phy0: pci-phy@0 {
 324                                         compatible = "brcm,ns2-pcie-phy";
 325                                         reg = <0x0>;
 326                                         #phy-cells = <0>;
 327                                         status = "disabled";
 328                                 };
 329                         };
 330
 331                         mdio@7 {
 332                                 reg = <0x7>;
 333                                 #address-cells = <1>;
 334                                 #size-cells = <0>;
 335
 336                                 pci_phy1: pci-phy@0 {
 337                                         compatible = "brcm,ns2-pcie-phy";
 338                                         reg = <0x0>;
 339                                         #phy-cells = <0>;
 340                                         status = "disabled";
 341                                 };
 342                         };
 343
 344                         mdio@10 {
 345                                 reg = <0x10>;
 346                                 #address-cells = <1>;
 347                                 #size-cells = <0>;
 348                         };
 349                 };
 350
 351                 timer0: timer@66030000 {
 352                         compatible = "arm,sp804", "arm,primecell";
 353                         reg = <0x66030000 0x1000>;
 354                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
 355                         clocks = <&iprocslow>,
 356                                  <&iprocslow>,
 357                                  <&iprocslow>;
 358                         clock-names = "timer1", "timer2", "apb_pclk";
 359                 };
 360
 361                 timer1: timer@66040000 {
 362                         compatible = "arm,sp804", "arm,primecell";
 363                         reg = <0x66040000 0x1000>;
 364                         interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 365                         clocks = <&iprocslow>,
 366                                  <&iprocslow>,
 367                                  <&iprocslow>;
 368                         clock-names = "timer1", "timer2", "apb_pclk";
 369                 };
 370
 371                 timer2: timer@66050000 {
 372                         compatible = "arm,sp804", "arm,primecell";
 373                         reg = <0x66050000 0x1000>;
 374                         interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
 375                         clocks = <&iprocslow>,
 376                                  <&iprocslow>,
 377                                  <&iprocslow>;
 378                         clock-names = "timer1", "timer2", "apb_pclk";
 379                 };
 380
 381                 timer3: timer@66060000 {
 382                         compatible = "arm,sp804", "arm,primecell";
 383                         reg = <0x66060000 0x1000>;
 384                         interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
 385                         clocks = <&iprocslow>,
 386                                  <&iprocslow>,
 387                                  <&iprocslow>;
 388                         clock-names = "timer1", "timer2", "apb_pclk";
 389                 };
 390
 391                 i2c0: i2c@66080000 {
 392                         compatible = "brcm,iproc-i2c";
 393                         reg = <0x66080000 0x100>;
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                         interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
 397                         clock-frequency = <100000>;
 398                         status = "disabled";
 399                 };
 400
 401                 wdt0: watchdog@66090000 {
 402                         compatible = "arm,sp805", "arm,primecell";
 403                         reg = <0x66090000 0x1000>;
 404                         interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
 405                         clocks = <&iprocslow>, <&iprocslow>;
 406                         clock-names = "wdogclk", "apb_pclk";
 407                 };
 408
 409                 gpio_g: gpio@660a0000 {
 410                         compatible = "brcm,iproc-gpio";
 411                         reg = <0x660a0000 0x50>;
 412                         ngpios = <32>;
 413                         #gpio-cells = <2>;
 414                         gpio-controller;
 415                         interrupt-controller;
 416                         interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
 417                 };
 418
 419                 i2c1: i2c@660b0000 {
 420                         compatible = "brcm,iproc-i2c";
 421                         reg = <0x660b0000 0x100>;
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
 425                         clock-frequency = <100000>;
 426                         status = "disabled";
 427                 };
 428
 429                 uart0: serial@66100000 {
 430                         compatible = "snps,dw-apb-uart";
 431                         reg = <0x66100000 0x100>;
 432                         interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
 433                         clocks = <&iprocslow>;
 434                         reg-shift = <2>;
 435                         reg-io-width = <4>;
 436                         status = "disabled";
 437                 };
 438
 439                 uart1: serial@66110000 {
 440                         compatible = "snps,dw-apb-uart";
 441                         reg = <0x66110000 0x100>;
 442                         interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
 443                         clocks = <&iprocslow>;
 444                         reg-shift = <2>;
 445                         reg-io-width = <4>;
 446                         status = "disabled";
 447                 };
 448
 449                 uart2: serial@66120000 {
 450                         compatible = "snps,dw-apb-uart";
 451                         reg = <0x66120000 0x100>;
 452                         interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
 453                         clocks = <&iprocslow>;
 454                         reg-shift = <2>;
 455                         reg-io-width = <4>;
 456                         status = "disabled";
 457                 };
 458
 459                 uart3: serial@66130000 {
 460                         compatible = "snps,dw-apb-uart";
 461                         reg = <0x66130000 0x100>;
 462                         interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
 463                         reg-shift = <2>;
 464                         reg-io-width = <4>;
 465                         clocks = <&osc>;
 466                         status = "disabled";
 467                 };
 468
 469                 ssp0: ssp@66180000 {
 470                         compatible = "arm,pl022", "arm,primecell";
 471                         reg = <0x66180000 0x1000>;
 472                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&iprocslow>, <&iprocslow>;
 474                         clock-names = "spiclk", "apb_pclk";
 475                         #address-cells = <1>;
 476                         #size-cells = <0>;
 477                         status = "disabled";
 478                 };
 479
 480                 ssp1: ssp@66190000 {
 481                         compatible = "arm,pl022", "arm,primecell";
 482                         reg = <0x66190000 0x1000>;
 483                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 484                         clocks = <&iprocslow>, <&iprocslow>;
 485                         clock-names = "spiclk", "apb_pclk";
 486                         #address-cells = <1>;
 487                         #size-cells = <0>;
 488                         status = "disabled";
 489                 };
 490
 491                 hwrng: hwrng@66220000 {
 492                         compatible = "brcm,iproc-rng200";
 493                         reg = <0x66220000 0x28>;
 494                 };
 495
 496                 sata_phy: sata_phy@663f0100 {
 497                         compatible = "brcm,iproc-ns2-sata-phy";
 498                         reg = <0x663f0100 0x1f00>,
 499                               <0x663f004c 0x10>;
 500                         reg-names = "phy", "phy-ctrl";
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503
 504                         sata_phy0: sata-phy@0 {
 505                                 reg = <0>;
 506                                 #phy-cells = <0>;
 507                                 status = "disabled";
 508                         };
 509
 510                         sata_phy1: sata-phy@1 {
 511                                 reg = <1>;
 512                                 #phy-cells = <0>;
 513                                 status = "disabled";
 514                         };
 515                 };
 516
 517                 sata: sata@663f2000 {
 518                         compatible = "brcm,iproc-ahci", "generic-ahci";
 519                         reg = <0x663f2000 0x1000>;
 520                         reg-names = "ahci";
 521                         interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
 522                         #address-cells = <1>;
 523                         #size-cells = <0>;
 524                         status = "disabled";
 525
 526                         sata0: sata-port@0 {
 527                                 reg = <0>;
 528                                 phys = <&sata_phy0>;
 529                                 phy-names = "sata-phy";
 530                         };
 531
 532                         sata1: sata-port@1 {
 533                                 reg = <1>;
 534                                 phys = <&sata_phy1>;
 535                                 phy-names = "sata-phy";
 536                         };
 537                 };
 538
 539                 sdio0: sdhci@66420000 {
 540                         compatible = "brcm,sdhci-iproc-cygnus";
 541                         reg = <0x66420000 0x100>;
 542                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
 543                         bus-width = <8>;
 544                         clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 545                         status = "disabled";
 546                 };
 547
 548                 sdio1: sdhci@66430000 {
 549                         compatible = "brcm,sdhci-iproc-cygnus";
 550                         reg = <0x66430000 0x100>;
 551                         interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
 552                         bus-width = <8>;
 553                         clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 554                         status = "disabled";
 555                 };
 556
 557                 nand: nand@66460000 {
 558                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 559                         reg = <0x66460000 0x600>,
 560                               <0x67015408 0x600>,
 561                               <0x66460f00 0x20>;
 562                         reg-names = "nand", "iproc-idm", "iproc-ext";
 563                         interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
 564
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567
 568                         brcm,nand-has-wp;
 569                 };
 570         };
 571 };