arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2015-2017 Broadcom.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34
  35 / {
  36         compatible = "brcm,stingray";
  37         interrupt-parent = <&gic>;
  38         #address-cells = <2>;
  39         #size-cells = <2>;
  40
  41         cpus {
  42                 #address-cells = <2>;
  43                 #size-cells = <0>;
  44
  45                 cpu@000 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a72", "arm,armv8";
  48                         reg = <0x0 0x0>;
  49                         enable-method = "psci";
  50                         next-level-cache = <&CLUSTER0_L2>;
  51                 };
  52
  53                 cpu@001 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a72", "arm,armv8";
  56                         reg = <0x0 0x1>;
  57                         enable-method = "psci";
  58                         next-level-cache = <&CLUSTER0_L2>;
  59                 };
  60
  61                 cpu@100 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a72", "arm,armv8";
  64                         reg = <0x0 0x100>;
  65                         enable-method = "psci";
  66                         next-level-cache = <&CLUSTER1_L2>;
  67                 };
  68
  69                 cpu@101 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a72", "arm,armv8";
  72                         reg = <0x0 0x101>;
  73                         enable-method = "psci";
  74                         next-level-cache = <&CLUSTER1_L2>;
  75                 };
  76
  77                 cpu@200 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a72", "arm,armv8";
  80                         reg = <0x0 0x200>;
  81                         enable-method = "psci";
  82                         next-level-cache = <&CLUSTER2_L2>;
  83                 };
  84
  85                 cpu@201 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a72", "arm,armv8";
  88                         reg = <0x0 0x201>;
  89                         enable-method = "psci";
  90                         next-level-cache = <&CLUSTER2_L2>;
  91                 };
  92
  93                 cpu@300 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a72", "arm,armv8";
  96                         reg = <0x0 0x300>;
  97                         enable-method = "psci";
  98                         next-level-cache = <&CLUSTER3_L2>;
  99                 };
 100
 101                 cpu@301 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a72", "arm,armv8";
 104                         reg = <0x0 0x301>;
 105                         enable-method = "psci";
 106                         next-level-cache = <&CLUSTER3_L2>;
 107                 };
 108
 109                 CLUSTER0_L2: l2-cache@000 {
 110                         compatible = "cache";
 111                 };
 112
 113                 CLUSTER1_L2: l2-cache@100 {
 114                         compatible = "cache";
 115                 };
 116
 117                 CLUSTER2_L2: l2-cache@200 {
 118                         compatible = "cache";
 119                 };
 120
 121                 CLUSTER3_L2: l2-cache@300 {
 122                         compatible = "cache";
 123                 };
 124         };
 125
 126         memory: memory@80000000 {
 127                 device_type = "memory";
 128                 reg = <0x00000000 0x80000000 0 0x40000000>;
 129         };
 130
 131         psci {
 132                 compatible = "arm,psci-0.2";
 133                 method = "smc";
 134         };
 135
 136         pmu {
 137                 compatible = "arm,armv8-pmuv3";
 138                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 139         };
 140
 141         timer {
 142                 compatible = "arm,armv8-timer";
 143                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 144                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 145                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 146                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 147         };
 148
 149         scr {
 150                 compatible = "simple-bus";
 151                 #address-cells = <1>;
 152                 #size-cells = <1>;
 153                 ranges = <0x0 0x0 0x61000000 0x05000000>;
 154
 155                 ccn: ccn@00000000 {
 156                         compatible = "arm,ccn-502";
 157                         reg = <0x00000000 0x900000>;
 158                         interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
 159                 };
 160
 161                 gic: interrupt-controller@02c00000 {
 162                         compatible = "arm,gic-v3";
 163                         #interrupt-cells = <3>;
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                         ranges;
 167                         interrupt-controller;
 168                         reg = <0x02c00000 0x010000>, /* GICD */
 169                               <0x02e00000 0x600000>; /* GICR */
 170                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 171
 172                         gic_its: gic-its@63c20000 {
 173                                 compatible = "arm,gic-v3-its";
 174                                 msi-controller;
 175                                 #msi-cells = <1>;
 176                                 reg = <0x02c20000 0x10000>;
 177                         };
 178                 };
 179
 180                 smmu: mmu@03000000 {
 181                         compatible = "arm,mmu-500";
 182                         reg = <0x03000000 0x80000>;
 183                         #global-interrupts = <1>;
 184                         interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
 185                                      <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
 187                                      <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
 188                                      <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
 189                                      <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
 190                                      <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
 191                                      <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
 192                                      <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
 193                                      <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
 194                                      <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
 195                                      <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
 197                                      <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
 202                                      <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
 203                                      <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
 204                                      <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
 206                                      <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
 207                                      <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
 208                                      <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
 209                                      <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
 210                                      <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
 211                                      <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
 212                                      <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
 213                                      <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
 214                                      <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
 217                                      <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
 218                                      <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
 220                                      <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
 226                                      <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
 227                                      <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
 228                                      <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
 229                                      <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
 239                                      <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
 243                                      <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
 245                                      <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
 248                                      <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
 249                         #iommu-cells = <2>;
 250                 };
 251         };
 252
 253         crmu: crmu {
 254                 compatible = "simple-bus";
 255                 #address-cells = <1>;
 256                 #size-cells = <1>;
 257                 ranges = <0x0 0x0 0x66400000 0x100000>;
 258
 259                 #include "stingray-clock.dtsi"
 260
 261                 gpio_crmu: gpio@00024800 {
 262                         compatible = "brcm,iproc-gpio";
 263                         reg = <0x00024800 0x4c>;
 264                         ngpios = <6>;
 265                         #gpio-cells = <2>;
 266                         gpio-controller;
 267                 };
 268         };
 269
 270         #include "stingray-fs4.dtsi"
 271         #include "stingray-sata.dtsi"
 272
 273         hsls {
 274                 compatible = "simple-bus";
 275                 #address-cells = <1>;
 276                 #size-cells = <1>;
 277                 ranges = <0x0 0x0 0x68900000 0x17700000>;
 278
 279                 #include "stingray-pinctrl.dtsi"
 280
 281                 mdio_mux_iproc: mdio-mux@0002023c {
 282                         compatible = "brcm,mdio-mux-iproc";
 283                         reg = <0x0002023c 0x14>;
 284                         #address-cells = <1>;
 285                         #size-cells = <0>;
 286
 287                         mdio@0 { /* PCIe serdes */
 288                                 reg = <0x0>;
 289                                 #address-cells = <1>;
 290                                 #size-cells = <0>;
 291                         };
 292
 293                         mdio@2 { /* SATA */
 294                                 reg = <0x2>;
 295                                 #address-cells = <1>;
 296                                 #size-cells = <0>;
 297                         };
 298
 299                         mdio@3 { /* USB */
 300                                 reg = <0x3>;
 301                                 #address-cells = <1>;
 302                                 #size-cells = <0>;
 303                         };
 304
 305                         mdio@10 { /* RGMII */
 306                                 reg = <0x10>;
 307                                 #address-cells = <1>;
 308                                 #size-cells = <0>;
 309                         };
 310                 };
 311
 312                 pwm: pwm@00010000 {
 313                         compatible = "brcm,iproc-pwm";
 314                         reg = <0x00010000 0x1000>;
 315                         clocks = <&crmu_ref25m>;
 316                         #pwm-cells = <3>;
 317                         status = "disabled";
 318                 };
 319
 320                 timer0: timer@00030000 {
 321                         compatible = "arm,sp804", "arm,primecell";
 322                         reg = <0x00030000 0x1000>;
 323                         interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 324                         clocks = <&hsls_25m_div2_clk>,
 325                                  <&hsls_25m_div2_clk>,
 326                                  <&hsls_div4_clk>;
 327                         clock-names = "timer1", "timer2", "apb_pclk";
 328                         status = "disabled";
 329                 };
 330
 331                 timer1: timer@00040000 {
 332                         compatible = "arm,sp804", "arm,primecell";
 333                         reg = <0x00040000 0x1000>;
 334                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 335                         clocks = <&hsls_25m_div2_clk>,
 336                                  <&hsls_25m_div2_clk>,
 337                                  <&hsls_div4_clk>;
 338                         clock-names = "timer1", "timer2", "apb_pclk";
 339                 };
 340
 341                 timer2: timer@00050000 {
 342                         compatible = "arm,sp804", "arm,primecell";
 343                         reg = <0x00050000 0x1000>;
 344                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
 345                         clocks = <&hsls_25m_div2_clk>,
 346                                  <&hsls_25m_div2_clk>,
 347                                  <&hsls_div4_clk>;
 348                         clock-names = "timer1", "timer2", "apb_pclk";
 349                         status = "disabled";
 350                 };
 351
 352                 timer3: timer@00060000 {
 353                         compatible = "arm,sp804", "arm,primecell";
 354                         reg = <0x00060000 0x1000>;
 355                         interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
 356                         clocks = <&hsls_25m_div2_clk>,
 357                                  <&hsls_25m_div2_clk>,
 358                                  <&hsls_div4_clk>;
 359                         clock-names = "timer1", "timer2", "apb_pclk";
 360                         status = "disabled";
 361                 };
 362
 363                 timer4: timer@00070000 {
 364                         compatible = "arm,sp804", "arm,primecell";
 365                         reg = <0x00070000 0x1000>;
 366                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 367                         clocks = <&hsls_25m_div2_clk>,
 368                                  <&hsls_25m_div2_clk>,
 369                                  <&hsls_div4_clk>;
 370                         clock-names = "timer1", "timer2", "apb_pclk";
 371                         status = "disabled";
 372                 };
 373
 374                 timer5: timer@00080000 {
 375                         compatible = "arm,sp804", "arm,primecell";
 376                         reg = <0x00080000 0x1000>;
 377                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 378                         clocks = <&hsls_25m_div2_clk>,
 379                                  <&hsls_25m_div2_clk>,
 380                                  <&hsls_div4_clk>;
 381                         clock-names = "timer1", "timer2", "apb_pclk";
 382                         status = "disabled";
 383                 };
 384
 385                 timer6: timer@00090000 {
 386                         compatible = "arm,sp804", "arm,primecell";
 387                         reg = <0x00090000 0x1000>;
 388                         interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 389                         clocks = <&hsls_25m_div2_clk>,
 390                                  <&hsls_25m_div2_clk>,
 391                                  <&hsls_div4_clk>;
 392                         clock-names = "timer1", "timer2", "apb_pclk";
 393                         status = "disabled";
 394                 };
 395
 396                 timer7: timer@000a0000 {
 397                         compatible = "arm,sp804", "arm,primecell";
 398                         reg = <0x000a0000 0x1000>;
 399                         interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
 400                         clocks = <&hsls_25m_div2_clk>,
 401                                  <&hsls_25m_div2_clk>,
 402                                  <&hsls_div4_clk>;
 403                         clock-names = "timer1", "timer2", "apb_pclk";
 404                         status = "disabled";
 405                 };
 406
 407                 i2c0: i2c@000b0000 {
 408                         compatible = "brcm,iproc-i2c";
 409                         reg = <0x000b0000 0x100>;
 410                         #address-cells = <1>;
 411                         #size-cells = <0>;
 412                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 413                         clock-frequency = <100000>;
 414                         status = "disabled";
 415                 };
 416
 417                 wdt0: watchdog@000c0000 {
 418                         compatible = "arm,sp805", "arm,primecell";
 419                         reg = <0x000c0000 0x1000>;
 420                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
 422                         clock-names = "wdogclk", "apb_pclk";
 423                 };
 424
 425                 gpio_hsls: gpio@000d0000 {
 426                         compatible = "brcm,iproc-gpio";
 427                         reg = <0x000d0000 0x864>;
 428                         ngpios = <151>;
 429                         #gpio-cells = <2>;
 430                         gpio-controller;
 431                         interrupt-controller;
 432                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 433                         gpio-ranges = <&pinmux 0 0 16>,
 434                                         <&pinmux 16 71 2>,
 435                                         <&pinmux 18 131 8>,
 436                                         <&pinmux 26 83 6>,
 437                                         <&pinmux 32 123 4>,
 438                                         <&pinmux 36 43 24>,
 439                                         <&pinmux 60 89 2>,
 440                                         <&pinmux 62 73 4>,
 441                                         <&pinmux 66 95 28>,
 442                                         <&pinmux 94 127 4>,
 443                                         <&pinmux 98 139 10>,
 444                                         <&pinmux 108 16 27>,
 445                                         <&pinmux 135 77 6>,
 446                                         <&pinmux 141 67 4>,
 447                                         <&pinmux 145 149 6>;
 448                 };
 449
 450                 i2c1: i2c@000e0000 {
 451                         compatible = "brcm,iproc-i2c";
 452                         reg = <0x000e0000 0x100>;
 453                         #address-cells = <1>;
 454                         #size-cells = <0>;
 455                         interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 456                         clock-frequency = <100000>;
 457                         status = "disabled";
 458                 };
 459
 460                 uart0: uart@00100000 {
 461                         device_type = "serial";
 462                         compatible = "snps,dw-apb-uart";
 463                         reg = <0x00100000 0x1000>;
 464                         reg-shift = <2>;
 465                         clock-frequency = <25000000>;
 466                         interrupt-parent = <&gic>;
 467                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 468                         status = "disabled";
 469                 };
 470
 471                 uart1: uart@00110000 {
 472                         device_type = "serial";
 473                         compatible = "snps,dw-apb-uart";
 474                         reg = <0x00110000 0x1000>;
 475                         reg-shift = <2>;
 476                         clock-frequency = <25000000>;
 477                         interrupt-parent = <&gic>;
 478                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 479                         status = "disabled";
 480                 };
 481
 482                 uart2: uart@00120000 {
 483                         device_type = "serial";
 484                         compatible = "snps,dw-apb-uart";
 485                         reg = <0x00120000 0x1000>;
 486                         reg-shift = <2>;
 487                         clock-frequency = <25000000>;
 488                         interrupt-parent = <&gic>;
 489                         interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 490                         status = "disabled";
 491                 };
 492
 493                 uart3: uart@00130000 {
 494                         device_type = "serial";
 495                         compatible = "snps,dw-apb-uart";
 496                         reg = <0x00130000 0x1000>;
 497                         reg-shift = <2>;
 498                         clock-frequency = <25000000>;
 499                         interrupt-parent = <&gic>;
 500                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 501                         status = "disabled";
 502                 };
 503
 504                 ssp0: ssp@00180000 {
 505                         compatible = "arm,pl022", "arm,primecell";
 506                         reg = <0x00180000 0x1000>;
 507                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 508                         clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
 509                         clock-names = "spiclk", "apb_pclk";
 510                         num-cs = <1>;
 511                         #address-cells = <1>;
 512                         #size-cells = <0>;
 513                         status = "disabled";
 514                 };
 515
 516                 ssp1: ssp@00190000 {
 517                         compatible = "arm,pl022", "arm,primecell";
 518                         reg = <0x00190000 0x1000>;
 519                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 520                         clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
 521                         clock-names = "spiclk", "apb_pclk";
 522                         num-cs = <1>;
 523                         #address-cells = <1>;
 524                         #size-cells = <0>;
 525                         status = "disabled";
 526                 };
 527
 528                 hwrng: hwrng@00220000 {
 529                         compatible = "brcm,iproc-rng200";
 530                         reg = <0x00220000 0x28>;
 531                 };
 532
 533                 dma0: dma@00310000 {
 534                         compatible = "arm,pl330", "arm,primecell";
 535                         reg = <0x00310000 0x1000>;
 536                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
 537                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
 538                                      <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 539                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 540                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 541                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 542                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 543                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 544                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 545                         #dma-cells = <1>;
 546                         #dma-channels = <8>;
 547                         #dma-requests = <32>;
 548                         clocks = <&hsls_div2_clk>;
 549                         clock-names = "apb_pclk";
 550                         iommus = <&smmu 0x6000 0x0000>;
 551                 };
 552
 553                 enet: ethernet@00340000{
 554                         compatible = "brcm,amac";
 555                         reg = <0x00340000 0x1000>;
 556                         reg-names = "amac_base";
 557                         dma-coherent;
 558                         interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
 559                         status= "disabled";
 560                 };
 561
 562                 nand: nand@00360000 {
 563                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 564                         reg = <0x00360000 0x600>,
 565                               <0x0050a408 0x600>,
 566                               <0x00360f00 0x20>;
 567                         reg-names = "nand", "iproc-idm", "iproc-ext";
 568                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 569                         #address-cells = <1>;
 570                         #size-cells = <0>;
 571                         brcm,nand-has-wp;
 572                         status = "disabled";
 573                 };
 574
 575                 sdio0: sdhci@003f1000 {
 576                         compatible = "brcm,sdhci-iproc";
 577                         reg = <0x003f1000 0x100>;
 578                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 579                         bus-width = <8>;
 580                         clocks = <&sdio0_clk>;
 581                         iommus = <&smmu 0x6002 0x0000>;
 582                         status = "disabled";
 583                 };
 584
 585                 sdio1: sdhci@003f2000 {
 586                         compatible = "brcm,sdhci-iproc";
 587                         reg = <0x003f2000 0x100>;
 588                         interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 589                         bus-width = <8>;
 590                         clocks = <&sdio1_clk>;
 591                         iommus = <&smmu 0x6003 0x0000>;
 592                         status = "disabled";
 593                 };
 594         };
 595 };