arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
   4  *
   5  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   6  *
   7  * Mingkai Hu <Mingkai.hu@freescale.com>
   8  */
   9
  10 /dts-v1/;
  11 #include "fsl-ls1043a.dtsi"
  12
  13 / {
  14         model = "LS1043A RDB Board";
  15
  16         aliases {
  17                 crypto = &crypto;
  18                 serial0 = &duart0;
  19                 serial1 = &duart1;
  20                 serial2 = &duart2;
  21                 serial3 = &duart3;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26         };
  27 };
  28
  29 &i2c0 {
  30         status = "okay";
  31         ina220@40 {
  32                 compatible = "ti,ina220";
  33                 reg = <0x40>;
  34                 shunt-resistor = <1000>;
  35         };
  36         adt7461a@4c {
  37                 compatible = "adi,adt7461";
  38                 reg = <0x4c>;
  39         };
  40         eeprom@52 {
  41                 compatible = "atmel,24c512";
  42                 reg = <0x52>;
  43         };
  44         eeprom@53 {
  45                 compatible = "atmel,24c512";
  46                 reg = <0x53>;
  47         };
  48         rtc@68 {
  49                 compatible = "pericom,pt7c4338";
  50                 reg = <0x68>;
  51         };
  52 };
  53
  54 &ifc {
  55         status = "okay";
  56         #address-cells = <2>;
  57         #size-cells = <1>;
  58         /* NOR, NAND Flashes and FPGA on board */
  59         ranges = <0x0 0x0 0x0 0x60000000 0x08000000
  60                   0x1 0x0 0x0 0x7e800000 0x00010000
  61                   0x2 0x0 0x0 0x7fb00000 0x00000100>;
  62
  63                 nor@0,0 {
  64                         compatible = "cfi-flash";
  65                         #address-cells = <1>;
  66                         #size-cells = <1>;
  67                         reg = <0x0 0x0 0x8000000>;
  68                         bank-width = <2>;
  69                         device-width = <1>;
  70                 };
  71
  72                 nand@1,0 {
  73                         compatible = "fsl,ifc-nand";
  74                         #address-cells = <1>;
  75                         #size-cells = <1>;
  76                         reg = <0x1 0x0 0x10000>;
  77                 };
  78
  79                 cpld: board-control@2,0 {
  80                         compatible = "fsl,ls1043ardb-cpld";
  81                         reg = <0x2 0x0 0x0000100>;
  82                 };
  83 };
  84
  85 &dspi0 {
  86         bus-num = <0>;
  87         status = "okay";
  88
  89         flash@0 {
  90                 #address-cells = <1>;
  91                 #size-cells = <1>;
  92                 compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
  93                 reg = <0>;
  94                 spi-max-frequency = <1000000>; /* input clock */
  95         };
  96 };
  97
  98 &duart0 {
  99         status = "okay";
 100 };
 101
 102 &duart1 {
 103         status = "okay";
 104 };
 105
 106 #include "fsl-ls1043-post.dtsi"
 107
 108 &fman0 {
 109         ethernet@e0000 {
 110                 phy-handle = <&qsgmii_phy1>;
 111                 phy-connection-type = "qsgmii";
 112         };
 113
 114         ethernet@e2000 {
 115                 phy-handle = <&qsgmii_phy2>;
 116                 phy-connection-type = "qsgmii";
 117         };
 118
 119         ethernet@e4000 {
 120                 phy-handle = <&rgmii_phy1>;
 121                 phy-connection-type = "rgmii-id";
 122         };
 123
 124         ethernet@e6000 {
 125                 phy-handle = <&rgmii_phy2>;
 126                 phy-connection-type = "rgmii-id";
 127         };
 128
 129         ethernet@e8000 {
 130                 phy-handle = <&qsgmii_phy3>;
 131                 phy-connection-type = "qsgmii";
 132         };
 133
 134         ethernet@ea000 {
 135                 phy-handle = <&qsgmii_phy4>;
 136                 phy-connection-type = "qsgmii";
 137         };
 138
 139         ethernet@f0000 { /* 10GEC1 */
 140                 phy-handle = <&aqr105_phy>;
 141                 phy-connection-type = "xgmii";
 142         };
 143
 144         mdio@fc000 {
 145                 rgmii_phy1: ethernet-phy@1 {
 146                         reg = <0x1>;
 147                 };
 148
 149                 rgmii_phy2: ethernet-phy@2 {
 150                         reg = <0x2>;
 151                 };
 152
 153                 qsgmii_phy1: ethernet-phy@4 {
 154                         reg = <0x4>;
 155                 };
 156
 157                 qsgmii_phy2: ethernet-phy@5 {
 158                         reg = <0x5>;
 159                 };
 160
 161                 qsgmii_phy3: ethernet-phy@6 {
 162                         reg = <0x6>;
 163                 };
 164
 165                 qsgmii_phy4: ethernet-phy@7 {
 166                         reg = <0x7>;
 167                 };
 168         };
 169
 170         mdio@fd000 {
 171                 aqr105_phy: ethernet-phy@1 {
 172                         compatible = "ethernet-phy-ieee802.3-c45";
 173                         interrupts = <0 132 4>;
 174                         reg = <0x1>;
 175                 };
 176         };
 177 };