arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

   1 /*
   2  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
   3  *
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  *
   6  * Mingkai Hu <Mingkai.hu@freescale.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPLv2 or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This library is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License as
  15  *     published by the Free Software Foundation; either version 2 of the
  16  *     License, or (at your option) any later version.
  17  *
  18  *     This library is distributed in the hope that it will be useful,
  19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *     GNU General Public License for more details.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include <dt-bindings/thermal/thermal.h>
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49
  50 / {
  51         compatible = "fsl,ls1043a";
  52         interrupt-parent = <&gic>;
  53         #address-cells = <2>;
  54         #size-cells = <2>;
  55
  56         aliases {
  57                 fman0 = &fman0;
  58                 ethernet0 = &enet0;
  59                 ethernet1 = &enet1;
  60                 ethernet2 = &enet2;
  61                 ethernet3 = &enet3;
  62                 ethernet4 = &enet4;
  63                 ethernet5 = &enet5;
  64                 ethernet6 = &enet6;
  65         };
  66
  67         cpus {
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70
  71                 /*
  72                  * We expect the enable-method for cpu's to be "psci", but this
  73                  * is dependent on the SoC FW, which will fill this in.
  74                  *
  75                  * Currently supported enable-method is psci v0.2
  76                  */
  77                 cpu0: cpu@0 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a53";
  80                         reg = <0x0>;
  81                         clocks = <&clockgen 1 0>;
  82                         next-level-cache = <&l2>;
  83                         #cooling-cells = <2>;
  84                 };
  85
  86                 cpu1: cpu@1 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53";
  89                         reg = <0x1>;
  90                         clocks = <&clockgen 1 0>;
  91                         next-level-cache = <&l2>;
  92                 };
  93
  94                 cpu2: cpu@2 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53";
  97                         reg = <0x2>;
  98                         clocks = <&clockgen 1 0>;
  99                         next-level-cache = <&l2>;
 100                 };
 101
 102                 cpu3: cpu@3 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a53";
 105                         reg = <0x3>;
 106                         clocks = <&clockgen 1 0>;
 107                         next-level-cache = <&l2>;
 108                 };
 109
 110                 l2: l2-cache {
 111                         compatible = "cache";
 112                 };
 113         };
 114
 115         memory@80000000 {
 116                 device_type = "memory";
 117                 reg = <0x0 0x80000000 0 0x80000000>;
 118                       /* DRAM space 1, size: 2GiB DRAM */
 119         };
 120
 121         reserved-memory {
 122                 #address-cells = <2>;
 123                 #size-cells = <2>;
 124                 ranges;
 125
 126                 bman_fbpr: bman-fbpr {
 127                         compatible = "shared-dma-pool";
 128                         size = <0 0x1000000>;
 129                         alignment = <0 0x1000000>;
 130                         no-map;
 131                 };
 132
 133                 qman_fqd: qman-fqd {
 134                         compatible = "shared-dma-pool";
 135                         size = <0 0x400000>;
 136                         alignment = <0 0x400000>;
 137                         no-map;
 138                 };
 139
 140                 qman_pfdr: qman-pfdr {
 141                         compatible = "shared-dma-pool";
 142                         size = <0 0x2000000>;
 143                         alignment = <0 0x2000000>;
 144                         no-map;
 145                 };
 146         };
 147
 148         sysclk: sysclk {
 149                 compatible = "fixed-clock";
 150                 #clock-cells = <0>;
 151                 clock-frequency = <100000000>;
 152                 clock-output-names = "sysclk";
 153         };
 154
 155         reboot {
 156                 compatible ="syscon-reboot";
 157                 regmap = <&dcfg>;
 158                 offset = <0xb0>;
 159                 mask = <0x02>;
 160         };
 161
 162         timer {
 163                 compatible = "arm,armv8-timer";
 164                 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
 165                              <1 14 0xf08>, /* Physical Non-Secure PPI */
 166                              <1 11 0xf08>, /* Virtual PPI */
 167                              <1 10 0xf08>; /* Hypervisor PPI */
 168                 fsl,erratum-a008585;
 169         };
 170
 171         pmu {
 172                 compatible = "arm,armv8-pmuv3";
 173                 interrupts = <0 106 0x4>,
 174                              <0 107 0x4>,
 175                              <0 95 0x4>,
 176                              <0 97 0x4>;
 177                 interrupt-affinity = <&cpu0>,
 178                                      <&cpu1>,
 179                                      <&cpu2>,
 180                                      <&cpu3>;
 181         };
 182
 183         gic: interrupt-controller@1400000 {
 184                 compatible = "arm,gic-400";
 185                 #interrupt-cells = <3>;
 186                 interrupt-controller;
 187                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
 188                       <0x0 0x1402000 0 0x2000>, /* GICC */
 189                       <0x0 0x1404000 0 0x2000>, /* GICH */
 190                       <0x0 0x1406000 0 0x2000>; /* GICV */
 191                 interrupts = <1 9 0xf08>;
 192         };
 193
 194         soc: soc {
 195                 compatible = "simple-bus";
 196                 #address-cells = <2>;
 197                 #size-cells = <2>;
 198                 ranges;
 199
 200                 clockgen: clocking@1ee1000 {
 201                         compatible = "fsl,ls1043a-clockgen";
 202                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 203                         #clock-cells = <2>;
 204                         clocks = <&sysclk>;
 205                 };
 206
 207                 scfg: scfg@1570000 {
 208                         compatible = "fsl,ls1043a-scfg", "syscon";
 209                         reg = <0x0 0x1570000 0x0 0x10000>;
 210                         big-endian;
 211                 };
 212
 213                 crypto: crypto@1700000 {
 214                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 215                                      "fsl,sec-v4.0";
 216                         fsl,sec-era = <3>;
 217                         #address-cells = <1>;
 218                         #size-cells = <1>;
 219                         ranges = <0x0 0x00 0x1700000 0x100000>;
 220                         reg = <0x00 0x1700000 0x0 0x100000>;
 221                         interrupts = <0 75 0x4>;
 222                         dma-coherent;
 223
 224                         sec_jr0: jr@10000 {
 225                                 compatible = "fsl,sec-v5.4-job-ring",
 226                                              "fsl,sec-v5.0-job-ring",
 227                                              "fsl,sec-v4.0-job-ring";
 228                                 reg        = <0x10000 0x10000>;
 229                                 interrupts = <0 71 0x4>;
 230                         };
 231
 232                         sec_jr1: jr@20000 {
 233                                 compatible = "fsl,sec-v5.4-job-ring",
 234                                              "fsl,sec-v5.0-job-ring",
 235                                              "fsl,sec-v4.0-job-ring";
 236                                 reg        = <0x20000 0x10000>;
 237                                 interrupts = <0 72 0x4>;
 238                         };
 239
 240                         sec_jr2: jr@30000 {
 241                                 compatible = "fsl,sec-v5.4-job-ring",
 242                                              "fsl,sec-v5.0-job-ring",
 243                                              "fsl,sec-v4.0-job-ring";
 244                                 reg        = <0x30000 0x10000>;
 245                                 interrupts = <0 73 0x4>;
 246                         };
 247
 248                         sec_jr3: jr@40000 {
 249                                 compatible = "fsl,sec-v5.4-job-ring",
 250                                              "fsl,sec-v5.0-job-ring",
 251                                              "fsl,sec-v4.0-job-ring";
 252                                 reg        = <0x40000 0x10000>;
 253                                 interrupts = <0 74 0x4>;
 254                         };
 255                 };
 256
 257                 dcfg: dcfg@1ee0000 {
 258                         compatible = "fsl,ls1043a-dcfg", "syscon";
 259                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 260                         big-endian;
 261                 };
 262
 263                 ifc: ifc@1530000 {
 264                         compatible = "fsl,ifc", "simple-bus";
 265                         reg = <0x0 0x1530000 0x0 0x10000>;
 266                         big-endian;
 267                         interrupts = <0 43 0x4>;
 268                 };
 269
 270                 qspi: quadspi@1550000 {
 271                         compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
 272                         #address-cells = <1>;
 273                         #size-cells = <0>;
 274                         reg = <0x0 0x1550000 0x0 0x10000>,
 275                                 <0x0 0x40000000 0x0 0x4000000>;
 276                         reg-names = "QuadSPI", "QuadSPI-memory";
 277                         interrupts = <0 99 0x4>;
 278                         clock-names = "qspi_en", "qspi";
 279                         clocks = <&clockgen 4 0>, <&clockgen 4 0>;
 280                         big-endian;
 281                         status = "disabled";
 282                 };
 283
 284                 esdhc: esdhc@1560000 {
 285                         compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
 286                         reg = <0x0 0x1560000 0x0 0x10000>;
 287                         interrupts = <0 62 0x4>;
 288                         clock-frequency = <0>;
 289                         voltage-ranges = <1800 1800 3300 3300>;
 290                         sdhci,auto-cmd12;
 291                         big-endian;
 292                         bus-width = <4>;
 293                 };
 294
 295                 ddr: memory-controller@1080000 {
 296                         compatible = "fsl,qoriq-memory-controller";
 297                         reg = <0x0 0x1080000 0x0 0x1000>;
 298                         interrupts = <0 144 0x4>;
 299                         big-endian;
 300                 };
 301
 302                 tmu: tmu@1f00000 {
 303                         compatible = "fsl,qoriq-tmu";
 304                         reg = <0x0 0x1f00000 0x0 0x10000>;
 305                         interrupts = <0 33 0x4>;
 306                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 307                         fsl,tmu-calibration = <0x00000000 0x00000026
 308                                                0x00000001 0x0000002d
 309                                                0x00000002 0x00000032
 310                                                0x00000003 0x00000039
 311                                                0x00000004 0x0000003f
 312                                                0x00000005 0x00000046
 313                                                0x00000006 0x0000004d
 314                                                0x00000007 0x00000054
 315                                                0x00000008 0x0000005a
 316                                                0x00000009 0x00000061
 317                                                0x0000000a 0x0000006a
 318                                                0x0000000b 0x00000071
 319
 320                                                0x00010000 0x00000025
 321                                                0x00010001 0x0000002c
 322                                                0x00010002 0x00000035
 323                                                0x00010003 0x0000003d
 324                                                0x00010004 0x00000045
 325                                                0x00010005 0x0000004e
 326                                                0x00010006 0x00000057
 327                                                0x00010007 0x00000061
 328                                                0x00010008 0x0000006b
 329                                                0x00010009 0x00000076
 330
 331                                                0x00020000 0x00000029
 332                                                0x00020001 0x00000033
 333                                                0x00020002 0x0000003d
 334                                                0x00020003 0x00000049
 335                                                0x00020004 0x00000056
 336                                                0x00020005 0x00000061
 337                                                0x00020006 0x0000006d
 338
 339                                                0x00030000 0x00000021
 340                                                0x00030001 0x0000002a
 341                                                0x00030002 0x0000003c
 342                                                0x00030003 0x0000004e>;
 343                         #thermal-sensor-cells = <1>;
 344                 };
 345
 346                 thermal-zones {
 347                         cpu_thermal: cpu-thermal {
 348                                 polling-delay-passive = <1000>;
 349                                 polling-delay = <5000>;
 350
 351                                 thermal-sensors = <&tmu 3>;
 352
 353                                 trips {
 354                                         cpu_alert: cpu-alert {
 355                                                 temperature = <85000>;
 356                                                 hysteresis = <2000>;
 357                                                 type = "passive";
 358                                         };
 359                                         cpu_crit: cpu-crit {
 360                                                 temperature = <95000>;
 361                                                 hysteresis = <2000>;
 362                                                 type = "critical";
 363                                         };
 364                                 };
 365
 366                                 cooling-maps {
 367                                         map0 {
 368                                                 trip = <&cpu_alert>;
 369                                                 cooling-device =
 370                                                         <&cpu0 THERMAL_NO_LIMIT
 371                                                         THERMAL_NO_LIMIT>;
 372                                         };
 373                                 };
 374                         };
 375                 };
 376
 377                 qman: qman@1880000 {
 378                         compatible = "fsl,qman";
 379                         reg = <0x0 0x1880000 0x0 0x10000>;
 380                         interrupts = <0 45 0x4>;
 381                         memory-region = <&qman_fqd &qman_pfdr>;
 382                 };
 383
 384                 bman: bman@1890000 {
 385                         compatible = "fsl,bman";
 386                         reg = <0x0 0x1890000 0x0 0x10000>;
 387                         interrupts = <0 45 0x4>;
 388                         memory-region = <&bman_fbpr>;
 389                 };
 390
 391                 bportals: bman-portals@508000000 {
 392                         ranges = <0x0 0x5 0x08000000 0x8000000>;
 393                 };
 394
 395                 qportals: qman-portals@500000000 {
 396                         ranges = <0x0 0x5 0x00000000 0x8000000>;
 397                 };
 398
 399                 dspi0: dspi@2100000 {
 400                         compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
 401                         #address-cells = <1>;
 402                         #size-cells = <0>;
 403                         reg = <0x0 0x2100000 0x0 0x10000>;
 404                         interrupts = <0 64 0x4>;
 405                         clock-names = "dspi";
 406                         clocks = <&clockgen 4 0>;
 407                         spi-num-chipselects = <5>;
 408                         big-endian;
 409                         status = "disabled";
 410                 };
 411
 412                 dspi1: dspi@2110000 {
 413                         compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416                         reg = <0x0 0x2110000 0x0 0x10000>;
 417                         interrupts = <0 65 0x4>;
 418                         clock-names = "dspi";
 419                         clocks = <&clockgen 4 0>;
 420                         spi-num-chipselects = <5>;
 421                         big-endian;
 422                         status = "disabled";
 423                 };
 424
 425                 i2c0: i2c@2180000 {
 426                         compatible = "fsl,vf610-i2c";
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                         reg = <0x0 0x2180000 0x0 0x10000>;
 430                         interrupts = <0 56 0x4>;
 431                         clock-names = "i2c";
 432                         clocks = <&clockgen 4 0>;
 433                         dmas = <&edma0 1 39>,
 434                                <&edma0 1 38>;
 435                         dma-names = "tx", "rx";
 436                         status = "disabled";
 437                 };
 438
 439                 i2c1: i2c@2190000 {
 440                         compatible = "fsl,vf610-i2c";
 441                         #address-cells = <1>;
 442                         #size-cells = <0>;
 443                         reg = <0x0 0x2190000 0x0 0x10000>;
 444                         interrupts = <0 57 0x4>;
 445                         clock-names = "i2c";
 446                         clocks = <&clockgen 4 0>;
 447                         status = "disabled";
 448                 };
 449
 450                 i2c2: i2c@21a0000 {
 451                         compatible = "fsl,vf610-i2c";
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                         reg = <0x0 0x21a0000 0x0 0x10000>;
 455                         interrupts = <0 58 0x4>;
 456                         clock-names = "i2c";
 457                         clocks = <&clockgen 4 0>;
 458                         status = "disabled";
 459                 };
 460
 461                 i2c3: i2c@21b0000 {
 462                         compatible = "fsl,vf610-i2c";
 463                         #address-cells = <1>;
 464                         #size-cells = <0>;
 465                         reg = <0x0 0x21b0000 0x0 0x10000>;
 466                         interrupts = <0 59 0x4>;
 467                         clock-names = "i2c";
 468                         clocks = <&clockgen 4 0>;
 469                         status = "disabled";
 470                 };
 471
 472                 duart0: serial@21c0500 {
 473                         compatible = "fsl,ns16550", "ns16550a";
 474                         reg = <0x00 0x21c0500 0x0 0x100>;
 475                         interrupts = <0 54 0x4>;
 476                         clocks = <&clockgen 4 0>;
 477                 };
 478
 479                 duart1: serial@21c0600 {
 480                         compatible = "fsl,ns16550", "ns16550a";
 481                         reg = <0x00 0x21c0600 0x0 0x100>;
 482                         interrupts = <0 54 0x4>;
 483                         clocks = <&clockgen 4 0>;
 484                 };
 485
 486                 duart2: serial@21d0500 {
 487                         compatible = "fsl,ns16550", "ns16550a";
 488                         reg = <0x0 0x21d0500 0x0 0x100>;
 489                         interrupts = <0 55 0x4>;
 490                         clocks = <&clockgen 4 0>;
 491                 };
 492
 493                 duart3: serial@21d0600 {
 494                         compatible = "fsl,ns16550", "ns16550a";
 495                         reg = <0x0 0x21d0600 0x0 0x100>;
 496                         interrupts = <0 55 0x4>;
 497                         clocks = <&clockgen 4 0>;
 498                 };
 499
 500                 gpio1: gpio@2300000 {
 501                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 502                         reg = <0x0 0x2300000 0x0 0x10000>;
 503                         interrupts = <0 66 0x4>;
 504                         gpio-controller;
 505                         #gpio-cells = <2>;
 506                         interrupt-controller;
 507                         #interrupt-cells = <2>;
 508                 };
 509
 510                 gpio2: gpio@2310000 {
 511                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 512                         reg = <0x0 0x2310000 0x0 0x10000>;
 513                         interrupts = <0 67 0x4>;
 514                         gpio-controller;
 515                         #gpio-cells = <2>;
 516                         interrupt-controller;
 517                         #interrupt-cells = <2>;
 518                 };
 519
 520                 gpio3: gpio@2320000 {
 521                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 522                         reg = <0x0 0x2320000 0x0 0x10000>;
 523                         interrupts = <0 68 0x4>;
 524                         gpio-controller;
 525                         #gpio-cells = <2>;
 526                         interrupt-controller;
 527                         #interrupt-cells = <2>;
 528                 };
 529
 530                 gpio4: gpio@2330000 {
 531                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 532                         reg = <0x0 0x2330000 0x0 0x10000>;
 533                         interrupts = <0 134 0x4>;
 534                         gpio-controller;
 535                         #gpio-cells = <2>;
 536                         interrupt-controller;
 537                         #interrupt-cells = <2>;
 538                 };
 539
 540                 lpuart0: serial@2950000 {
 541                         compatible = "fsl,ls1021a-lpuart";
 542                         reg = <0x0 0x2950000 0x0 0x1000>;
 543                         interrupts = <0 48 0x4>;
 544                         clocks = <&clockgen 0 0>;
 545                         clock-names = "ipg";
 546                         status = "disabled";
 547                 };
 548
 549                 lpuart1: serial@2960000 {
 550                         compatible = "fsl,ls1021a-lpuart";
 551                         reg = <0x0 0x2960000 0x0 0x1000>;
 552                         interrupts = <0 49 0x4>;
 553                         clocks = <&clockgen 4 0>;
 554                         clock-names = "ipg";
 555                         status = "disabled";
 556                 };
 557
 558                 lpuart2: serial@2970000 {
 559                         compatible = "fsl,ls1021a-lpuart";
 560                         reg = <0x0 0x2970000 0x0 0x1000>;
 561                         interrupts = <0 50 0x4>;
 562                         clocks = <&clockgen 4 0>;
 563                         clock-names = "ipg";
 564                         status = "disabled";
 565                 };
 566
 567                 lpuart3: serial@2980000 {
 568                         compatible = "fsl,ls1021a-lpuart";
 569                         reg = <0x0 0x2980000 0x0 0x1000>;
 570                         interrupts = <0 51 0x4>;
 571                         clocks = <&clockgen 4 0>;
 572                         clock-names = "ipg";
 573                         status = "disabled";
 574                 };
 575
 576                 lpuart4: serial@2990000 {
 577                         compatible = "fsl,ls1021a-lpuart";
 578                         reg = <0x0 0x2990000 0x0 0x1000>;
 579                         interrupts = <0 52 0x4>;
 580                         clocks = <&clockgen 4 0>;
 581                         clock-names = "ipg";
 582                         status = "disabled";
 583                 };
 584
 585                 lpuart5: serial@29a0000 {
 586                         compatible = "fsl,ls1021a-lpuart";
 587                         reg = <0x0 0x29a0000 0x0 0x1000>;
 588                         interrupts = <0 53 0x4>;
 589                         clocks = <&clockgen 4 0>;
 590                         clock-names = "ipg";
 591                         status = "disabled";
 592                 };
 593
 594                 wdog0: wdog@2ad0000 {
 595                         compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
 596                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 597                         interrupts = <0 83 0x4>;
 598                         clocks = <&clockgen 4 0>;
 599                         clock-names = "wdog";
 600                         big-endian;
 601                 };
 602
 603                 edma0: edma@2c00000 {
 604                         #dma-cells = <2>;
 605                         compatible = "fsl,vf610-edma";
 606                         reg = <0x0 0x2c00000 0x0 0x10000>,
 607                               <0x0 0x2c10000 0x0 0x10000>,
 608                               <0x0 0x2c20000 0x0 0x10000>;
 609                         interrupts = <0 103 0x4>,
 610                                      <0 103 0x4>;
 611                         interrupt-names = "edma-tx", "edma-err";
 612                         dma-channels = <32>;
 613                         big-endian;
 614                         clock-names = "dmamux0", "dmamux1";
 615                         clocks = <&clockgen 4 0>,
 616                                  <&clockgen 4 0>;
 617                 };
 618
 619                 usb0: usb3@2f00000 {
 620                         compatible = "snps,dwc3";
 621                         reg = <0x0 0x2f00000 0x0 0x10000>;
 622                         interrupts = <0 60 0x4>;
 623                         dr_mode = "host";
 624                         snps,quirk-frame-length-adjustment = <0x20>;
 625                         snps,dis_rxdet_inp3_quirk;
 626                 };
 627
 628                 usb1: usb3@3000000 {
 629                         compatible = "snps,dwc3";
 630                         reg = <0x0 0x3000000 0x0 0x10000>;
 631                         interrupts = <0 61 0x4>;
 632                         dr_mode = "host";
 633                         snps,quirk-frame-length-adjustment = <0x20>;
 634                         snps,dis_rxdet_inp3_quirk;
 635                 };
 636
 637                 usb2: usb3@3100000 {
 638                         compatible = "snps,dwc3";
 639                         reg = <0x0 0x3100000 0x0 0x10000>;
 640                         interrupts = <0 63 0x4>;
 641                         dr_mode = "host";
 642                         snps,quirk-frame-length-adjustment = <0x20>;
 643                         snps,dis_rxdet_inp3_quirk;
 644                 };
 645
 646                 sata: sata@3200000 {
 647                         compatible = "fsl,ls1043a-ahci";
 648                         reg = <0x0 0x3200000 0x0 0x10000>,
 649                                 <0x0 0x20140520 0x0 0x4>;
 650                         reg-names = "ahci", "sata-ecc";
 651                         interrupts = <0 69 0x4>;
 652                         clocks = <&clockgen 4 0>;
 653                         dma-coherent;
 654                 };
 655
 656                 msi1: msi-controller1@1571000 {
 657                         compatible = "fsl,ls1043a-msi";
 658                         reg = <0x0 0x1571000 0x0 0x8>;
 659                         msi-controller;
 660                         interrupts = <0 116 0x4>;
 661                 };
 662
 663                 msi2: msi-controller2@1572000 {
 664                         compatible = "fsl,ls1043a-msi";
 665                         reg = <0x0 0x1572000 0x0 0x8>;
 666                         msi-controller;
 667                         interrupts = <0 126 0x4>;
 668                 };
 669
 670                 msi3: msi-controller3@1573000 {
 671                         compatible = "fsl,ls1043a-msi";
 672                         reg = <0x0 0x1573000 0x0 0x8>;
 673                         msi-controller;
 674                         interrupts = <0 160 0x4>;
 675                 };
 676
 677                 pcie@3400000 {
 678                         compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
 679                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 680                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 681                         reg-names = "regs", "config";
 682                         interrupts = <0 118 0x4>, /* controller interrupt */
 683                                      <0 117 0x4>; /* PME interrupt */
 684                         interrupt-names = "intr", "pme";
 685                         #address-cells = <3>;
 686                         #size-cells = <2>;
 687                         device_type = "pci";
 688                         dma-coherent;
 689                         num-lanes = <4>;
 690                         bus-range = <0x0 0xff>;
 691                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 692                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 693                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 694                         #interrupt-cells = <1>;
 695                         interrupt-map-mask = <0 0 0 7>;
 696                         interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
 697                                         <0000 0 0 2 &gic 0 111 0x4>,
 698                                         <0000 0 0 3 &gic 0 112 0x4>,
 699                                         <0000 0 0 4 &gic 0 113 0x4>;
 700                 };
 701
 702                 pcie@3500000 {
 703                         compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
 704                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 705                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 706                         reg-names = "regs", "config";
 707                         interrupts = <0 128 0x4>,
 708                                      <0 127 0x4>;
 709                         interrupt-names = "intr", "pme";
 710                         #address-cells = <3>;
 711                         #size-cells = <2>;
 712                         device_type = "pci";
 713                         dma-coherent;
 714                         num-lanes = <2>;
 715                         bus-range = <0x0 0xff>;
 716                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 717                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 718                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 719                         #interrupt-cells = <1>;
 720                         interrupt-map-mask = <0 0 0 7>;
 721                         interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
 722                                         <0000 0 0 2 &gic 0 121 0x4>,
 723                                         <0000 0 0 3 &gic 0 122 0x4>,
 724                                         <0000 0 0 4 &gic 0 123 0x4>;
 725                 };
 726
 727                 pcie@3600000 {
 728                         compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
 729                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 730                                0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 731                         reg-names = "regs", "config";
 732                         interrupts = <0 162 0x4>,
 733                                      <0 161 0x4>;
 734                         interrupt-names = "intr", "pme";
 735                         #address-cells = <3>;
 736                         #size-cells = <2>;
 737                         device_type = "pci";
 738                         dma-coherent;
 739                         num-lanes = <2>;
 740                         bus-range = <0x0 0xff>;
 741                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 742                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 743                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 744                         #interrupt-cells = <1>;
 745                         interrupt-map-mask = <0 0 0 7>;
 746                         interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
 747                                         <0000 0 0 2 &gic 0 155 0x4>,
 748                                         <0000 0 0 3 &gic 0 156 0x4>,
 749                                         <0000 0 0 4 &gic 0 157 0x4>;
 750                 };
 751         };
 752
 753 };
 754
 755 #include "qoriq-qman-portals.dtsi"
 756 #include "qoriq-bman-portals.dtsi"